JPH02148865A - Silicon transistor on insulator including connection between body node and source node - Google Patents

Abstract

PURPOSE: To obtain an insulating gate field-effect transistor formed in a semiconductor area positioned on an insulator which is equipped with a body node by forming ohmic connection between a first contact area and a source area of the silicide film of a refractory metal on the first contact area and the source area. CONSTITUTION: A silicide film 22 is provided on the surface of a silicon structure (source area 6, p+ contact, area 30, drain area 8, and gate area 10). For example, ohmic connection can be formed between the p+ contact area 30 and the source area 6 by a mutually connecting means such as a normal contact reaching a metalize layer through an insulator film positioned at the upper side. A silicide film 22 applies the connection of low resistances between both without necessitating any additional making process. When the silicide film 22 is user for applying contact between the source area 6 and the p+ contact area 30, it is desired that a side wall oxide filament 16 is used for preventing the silicide film 22 on the source and drain both areas 6 and 8 from being electrically short-circuited with the silicide film 22 on the surface of the gate electrode 10.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to the field of integrated circuits, and more particularly to insulated gate field effect transistors formed by silicon-on-insulator (SOI) technology.

BACKGROUND OF THE INVENTION Silicon-on-insulator (SOI) technology is becoming increasingly important in the field of integrated circuits. SOI technology deals with the formation of transistors in a layer of semiconductor material overlying an insulating layer, and the most common example of a Sol structure is a single crystal layer of silicon overlying a layer of silicon dioxide. Sol technology reduces the parasitic elements present in integrated circuits formed in bulk (substrate) semiconductors.
High performance, high density integrated circuits are achievable. for example,
In the case of bulk MOS (MOS) transistors, parasitic capacitance exists at the junction between the source/drain region and the lower substrate, and the junction between the source/drain region and the substrate region breaks down (dielectric breakdown). There is also the possibility of doing so. Another example of parasitic elements exists in bulk CMO3 technology where parasitic bipolar transistors formed by n-channel and p-channel transistors in adjacent wells can create latch-up problems. S
The ol structure significantly reduces parasitics and increases the structure's resistance to junction breakdown, making SOI technology highly suitable for high-performance, high-density integrated circuits.

Furthermore, as a technology similar to Sol, silicon on sapphire (
SO3) technology, which offers similar advantages to those discussed above in connection with Sol technology. The invention disclosed herein is
It should be noted that it is also applicable to SOS structures.

(Problem to be solved by the invention) However, the lower insulator film in the SOI structure
This causes several problems with transistor characteristics. In bulk transistors, electrical connections are easily made through the substrate to the body nodes of the MOS transistors. A relatively constant bias at the substrate node provides a stable threshold voltage for the drain-source voltage. However, in the conventional 5ol) transistor, the body node is electrically floating because the body node is insulated from the substrate by the lower insulating film.
That is, it has a non-depleted volume (in the body region located below the gate electrode). Under sufficient drain-source bias, impact ionization can generate electron-hole pairs near the drain, resulting in majority carriers moving toward the body node while minority carriers moving toward the drain. Therefore, a voltage difference occurs between the body node and the source of the transistor. This voltage difference lowers the effective threshold voltage and increases the drain current, resulting in the well-known “
It exhibits a "kink" effect.

Also, the floating body node of the 5ol) transistor provides a parasitic "bank channel" transistor where the substrate is the gate and the insulator film located below the transistor is the gate dielectric. This back channel may provide a drain-source leak path along the body node near the interface with the insulator film. In addition, the dielectrically isolated body node allows capacitive coupling between the body node and the gate and diode coupling between the body node and the source and drain, influencing the threshold voltage by biasing the body node. affect Each of these factors can result in undesirable performance shifts in the transistor compared to design and increased instability in transistor operating characteristics.

It is therefore an object of the invention to provide an insulated gate field effect transistor formed in a semiconductor region located on an insulator, having a body node connected to a source node.

Another object of the invention is to provide the above transistor which can be manufactured with a minimum of additional masking steps.

Another object of the invention is to provide such a transistor which can be fabricated on the basis of silicide cladding of the source and drain diffusions.

Another object of the invention is to provide such a transistor having a body-source connection manufactured in such a way that the specifications of the source and drain nodes of the transistor can be reversed with minimal mask level changes.

Yet another object of the invention is to provide such a transistor with reduced edge leakage due to interfacial dopant diffusion as well as reduced leakage due to exposure to ionizing radiation.

Yet another object of the invention is to provide such a transistor with reduced edge leakage due to interfacial dopant diffusion as well as reduced leakage due to exposure to ionizing radiation.

Yet another object of the invention is to provide such a transistor with reduced edge leakage due to interfacial dopant diffusion as well as reduced leakage due to exposure to ionizing radiation.

Other objects and advantages of the invention will become apparent to those skilled in the art upon reference to this specification and the accompanying drawings.

(Means for Solving the Problems) The present invention can be implemented as a silicon-on-insulator type insulated gate field effect transistor. A highly doped contact region of opposite conductivity type to the source and drain is formed adjacent to the gate electrode on the source side of the gate electrode. This region can be formed in a self-aligned manner with respect to the gate electrode by well-known techniques such as implantation and diffusion. Since the contact region and the body node (located below the gate electrode) are of the same conductivity type, the contact region is electrically connected to the body node.

The source region and the body node-contact region are thus connected together by silicidation of the structure surface and can be connected to the source region body node.

Another embodiment of the invention may be implemented as a silicon-on-insulator type insulated gate field effect transistor with a graded junction. A highly doped contact region of opposite conductivity type to the source and drain is formed adjacent to the lightly doped drain region on the source side of the gate electrode. The contact region may be formed in a self-aligned manner by well-known techniques such as implantation and diffusion, after providing a sidewall oxide filament extending down the sides of the gate to the lightly doped drain region on the source side of the transistor. Since the contact region and the body node (located below the gate electrode) are of the same conductivity type, the contact region is electrically connected to the body node. The source region and the body node-contact region are thus connected together by silicidation of the structure surface, allowing the source region to be connected to the body node. The lightly doped drain region on the source side of the transistor remains between the body node and the contact region at the surface, so that the channel width of the transistor is equal to the width of the contact region, as when the contact region is contacted with the body node at the surface. will not be reduced by

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS. 1 and 2, a prior art n-channel SOI transistor is shown in top and cross-sectional views, respectively. As shown in FIG. 2, this transistor is formed in a single crystal silicon mesa 5 located on an insulating film 4 formed on a silicon substrate 2. As shown in FIG.

Insulator film 4 is typically silicon dioxide. Insulator film 4
The formation of the mesa 5 on top can be done by any one of a number of well-known methods, such as SIMOX (separation with implanted oxygen), oxygenated porous silicon (FIPO3), and thin film zone-melt recrystallization (ZMR). An example of the SIMOX method is
Transferred to Instruments Inc. 1987 4
The date of May 7 is set forth in the application, US Pat. No. 035,126.

thermally grown silicon dioxide, deposited silicon nitride,
A gate insulator 14, such as a gate insulator 14 or a combination thereof, is provided on the surface of the single crystal mesa 5. A gate electrode 10, typically formed of highly doped polycrystalline silicon, is located on the gate insulator 14 and defines the gate of the MOS transistor of FIGS. 1 and 2. The source region 6 and drain region 8 are highly doped n-shaded regions formed by ion implantation followed by diffusion. As shown in FIG. 2, this example of a conventional transistor is formed with a well-known lightly doped drain structure in which the implantation of lightly doped regions 18 (generally prior to the formation of sidewall oxide filaments 16) at the gate This is done in a self-aligned manner with respect to the electrode 10. An example of a method for forming lightly doped drain transistors using sidewall oxide filaments is the Texas In
Transferred to Struments Inc. November 2, 1982
The date is set forth in issued US Pat. No. 4,356,623, which is hereby incorporated by reference. The highly doped portions of the source and drain doublets 6.8 in FIGS. 1 and 2 are shown as being formed in a self-aligned manner to the gate electrode 10 and the sidewall oxide filaments 16, and the insulator is removed from the surface of the mesa 5. It extends completely to the boundary with membrane 4. The body node region 12 is a p-channel region that is undoped with the n-type dopant used to form the source and drain doublets 6.8.
It remains in the same conductivity type and concentration as originally formed (slightly doped p-type silicon with respect to the dopant concentration of the source and drain regions 6.8).

In FIG. 2, a silicide film 22 of a refractory (refractory) metal such as titanium disilicide is shown as the cladding of the source and drain regions 6.8 and the gate electrode 10. Such silicidation is useful for reducing the sheet resistance of semiconductor layers, for example in Texas
Transferred to Instruments Inc. 19879
Preferably, the method is made in accordance with the well-known self-aligned direct reaction silicidation process as described in U.S. Pat. No. 4,690,730, published and incorporated herein by reference. shall be taken as a thing. However, such silicidation is of course not essential for the operation of the transistor. Any one of the well-known adhesive flux metals commonly used in silicidation, such as molybdenum, tungsten, and cobalt, may be used in the formation of the silicide film 22 in place of titanium.

In the case of transistor 1 in FIGS. 1 and 2, body node 1
2 are electrically isolated within the transistors of FIGS. The source and drain double head regions 6.8 extend to the full thickness of the mesa 5 and reach the insulator film 4, and due to the self-alignment of the source and drain double head regions 6.8, the body node 12 is connected to the gate electrode 10 (and It is inconvenient to make contact with the body node 12 in the structure of FIGS. 1 and 2 because it is present only below the sidewall oxide filaments 16). Therefore, in the conventional Sol technology, the body node 12 of each MOS transistor is in a floating state.

The floating body node of the SO transistor poses several problems in transistor performance and performance stability. The first problem is the presence of a parasitic "back channel" transistor with substrate 2 as the gate electrode and insulator film 4 as the gate dielectric. This back channel may provide a leak path between the drain and the source along the body node 12 near the interface with the insulating film 4, depending on the local potential of the substrate 2 at the location of the transistor.

Furthermore, it is well known that the voltage at body node 12 influences the threshold voltage (Vt) of a transistor. In bulk devices, the body nodes of the MOS transistors are biased by the substrate, but the first and second
The dielectrically isolated body node 12 of the illustrated transistor 1 allows capacitive coupling between the body node 12 and the gate electrode 10 and diode coupling between the body node 12 and the source and drain regions 6.8; body node 1
2 to an undesired potential.

Additionally, when impact ionization occurs when carriers near the drain are at a high enough potential to generate electron-hole pairs, the result is that minority carriers move toward the drain, while majority carriers move toward the body node. This creates a voltage difference between body node 12 and source region 6, lowering the effective threshold voltage and increasing drain current (ie, causing the well-known "kink" effect).

3 and 4, a transistor 100 constructed in accordance with the present invention is shown;
The same reference numerals are used to designate the same components as used in the conventional transistor 1 of the figure. Transistor 100 includes contacts between the source and body nodes to alleviate the floating body node problem discussed above with respect to conventional transistor 1, as described below.

The top view of FIG. 3 shows a p+ contact region 30 located at the edge of the mesa adjacent to gate electrode 10 (and sidewall oxide filament 16).

The conducting channel of the transistor 100 remains along the edge of the gate electrode 1o on the source side, between the edge contact regions 30. Note that the plan view in FIG. 3 shows the transistor 100.
This is the state before silicide; as explained below,
Preferably, silicide cladding is used to provide an electrical connection from source region 6 to body node 12 below gate electrode 10 by connecting source region 6 to p-contact region 30 at the surface.

It should also be noted that placing the p+ contact region 30 at the edge of the mesa 5 is not essential to providing contact between the body node 12 and the source region 6. However, as described in parent U.S. patent application Ser. decrease.

Furthermore, it should be noted that the active semiconductor formed on the insulator film 4 may contain a relatively large number of dislocation defects compared to the active region in the bulk in many Sol technologies. These dislocations, particularly along the edges of silicon mesas such as mesa 5, prevent the diffusion dopants forming the source and drain double head regions 6.8 from diffusing through the body region 12, especially along the edges of mesa 5. It may be allowed. This multiplicative diffusion can cause short channel effects such as subthreshold leakage in transistor 100, and if the diffused dopant extends as far as the source region 6 and drain region 8, it may cause the drain region 8 to This causes a short circuit to the source region 6. The arrangement of the contact region 30 to the edge of the mesa 5 is achieved by separating the dopant of the source region 6 from the edge of the mesa 5 on the side of the gate electrode 10, thereby creating a source/bis 4-layer interface based on multiplication diffusion as described above. Leakage is reduced so that multiplication diffusion into the body region 12 occurs only from the drain side. Additionally, the placement of contact region 30 to the edge of mesa 5 provides a p+fif between dopants from drain region 8 that diffuse through body region 12 along the edge of mesa 5.
Since the f-region is located, the dopants arriving from the drain region 8 completely below the gate electrode form only a reverse biased diode (the contact region 3o is at the same potential as the source region 6). Therefore, placement of contact region 30 at the edge of mesa 5 reduces source/bis leakage due to enhanced interfacial diffusion of source/drain dopants.

Referring now to FIG. 4, transistor 100 is shown in cross-section. In this embodiment, the source region 6 and the drain region 8 are p
Like the contact area 3o, it extends through the entire thickness of the mesa 5. Note that the p contact region 30 does not necessarily have to completely extend to the insulating film 4 in this way in order to make contact with the body node 12. However, the contact region must extend to a depth sufficient to contact the body region that remains in a depletion layer below the channel of transistor 100 when conductive.

FIG. 4 also shows that a silicide film 22 is provided on the surface of the silicon structure (source region 6, p contact region 30, drain region 8, and gate region 10). Although the ohmic connection between the p-contact region 30 and the source region 6 can be formed by other interconnection means, such as, for example, a conventional contact through an overlying insulator film to a metallization layer. Silicide film 22 provides a low resistance connection between the two without the need for additional masking steps.

Still referring to FIG. 4, the p+ contact region 30 includes a lightly doped drain extension 38 located below the sidewall filament 16 on the gate electrode 10 side. The lightly doped drain extension 38 is, of course, not essential to making contact with the body node 12. However, if a silicide film 22 is used to provide contact between the source region 6 and the p-contact region 30, the silicide film 22 on the source and drain regions 6.8 (as well as the p-contact region 30), respectively, is It is preferable to use sidewall oxide filaments 16 to avoid electrical short-circuiting with the silicide film 22 on the surface of the gate electrode 10.

As is known in the art, the use of sidewall oxide filaments 16 not only facilitates the formation of graded junctions in transistors, but also facilitates the formation of graded junctions in the source, drain, and gate regions while minimizing the risk of shorting as described above. Silicidation by self-alignment is also possible. According to this embodiment of the invention, these advantages are achieved without appreciably affecting the connection between p+ contact region 30 and body node 12, even including the lightly doped drain extension 38 of p+ contact region 30. be done. As discussed below, the inclusion of a lightly doped drain extension 38 in the p+ contact region 30, particularly in CMO5 applications, also allows for the formation of source-body contacts without the need for additional masking steps.

Note that in the transistors of FIGS. 3 and 4, there is no contact between the p+ contact region 30 and the drain region 8. Therefore, the p+ contact region 30 is the body node 1
In order to achieve the best contact with 2, it can be doped as strongly as possible without concern for drain-source junction breakdown through the p-domain contact region 30. When the channel length is 1 micron, in an example of the doping concentration of each region of the transistor 100 according to the present invention, the body node 12
has an impurity concentration of 10"/cJ, the impurity concentration of the contact region 30 is 10I11~10z1/a11
is within the range of The source and drain doublets 6.8 can typically have an impurity concentration of 1Q18 to 10"/cJ, while the lightly doped drain regions 18 and 38 range from IQIII to 10"/c11 depending on the desired dopant slope.

5a-5e, the steps in the formation of an n-channel transistor 100n and a p-channel transistor 100p as formed in a CMO3 circuit are discussed, and the source-to-body connection according to the present invention This shows that it can be formed without requiring an additional masking step during the manufacturing process. The cross-sectional views of FIGS. 5a-50 are along similar locations as FIG. 4, ie, through portions of transistor 100 with source-to-body contact. In Figure 5a, two mesas 5n and 5p are connected to the insulator N4.
Mesa 5n is shown as n-type silicon and mesa 5p is p-type silicon. Similar to the patterned polysilicon gate electrode 10, each mesa 5n
and 5p; therefore, gate oxide 14 is present on 5p;
The structure shown is ready for forming source and drain doublets 6.8 and contact areas 30.

FIG. 5a shows a lightly doped drain extension 18 for p-channel transistor 100p while covering certain portions of the structure.
Also shown is a mask layer 40 that exposes where a p-type implant will be made to form a lightly doped drain extension 38p for the source-body contact of p- and n-channel transistor 100n. Mask 1i40 may be a patterned photoresist or a hard mask layer such as is commonly used to block ion implantation. Mask layer 4
The .degree. pattern is preferably designed such that the mask layer 40 overlaps the gate electrode 10 and also overlaps the edges of the mesa 5 for maximum alignment tolerance. Fifth
As shown in FIG. Form.

Referring to FIG. 5b, after the injection of FIG. 5a and after the injection of FIG.
The structure is shown after the formation of a mask J'i42 which protects the regions where the p-type implants of figure a have been made and which exposes the regions of the structure where the n-type lightly doped drain implants are to be made. Figure 5b shows the lightly doped drain extension 1
It shows that 8p and 38p are each driven (driven) to almost the final depth. Furthermore, Section 5a
Note that each of the implants shown in Figures ~5b is not implanted immediately after each masking step, but one implant anneal is performed after all four previous implants are performed. The point in time at which the implant anneal or implants are performed is not critical to the fabrication of structures according to the invention; however, for ease of explanation of the masking process, the implant anneal after each implant is shown in Figures 5a-5d. It is. Figure 5b shows the structure ready to accept an n-type (arsenic, phosphorus, or other conventional dopant) lightly doped drain implant at conventional doses and energies.

Referring now to FIG. 5C, transistors 100n and 100p receive strong p-type source/drain implants.
is the indication. A sidewall oxide filament 16 is placed between each gate electrode 10 to protect a portion of region 18p of transistor 100p and region 38p of transistor 100n from strong source/drain implants to provide a graded junction as is well known in the art. It is placed at a predetermined location adjacent to both sides. The sidewall oxide filament 16 is TE0
It is formed by depositing an oxide layer, such as by decomposition of 1, and then anisotropically etching the oxide, leaving sidewall oxide filaments 16 behind.

Mask 1150 connects n-type implant regions 18n and 38n to p-type implant regions 18n and 38n.
The p-type implant region (excluding the portion protected by filament 16) is exposed. In addition, mask layer 5
The pattern used to form the 0's may be the same as the pattern used to form the mask layer 40. A p-type source/drain implant is then performed as shown in Figure 5c.
The doses and energies customary for such implants are followed.

FIG. 5d shows that transistor 100p has a source region 6p and drain region 8p, and transistor 100n has a p contact region 30p that contacts the body node of transistor 100n. FIG. 5d also shows pII regions 6p, 8p and 30p as n-type sources/
Also shown is a final source/drain patterned mask layer 52 exposing regions of transistors 100n and 100p that protect from and receive drain implants. The implantation of FIG. 5d therefore ultimately forms the source and drain regions 6n, 8n of transistor 100n, respectively, and the implantation of transistor 10n shown in FIGS. 3 and 4.
Transistor Loop similar to p+ contact region 30 of 0
n10 contact regions 30n for contact between the source region 6p and the body node are also formed.

After the implant anneal, the result of the implant in Figure 5d is shown in Figure 5e.
It is shown in the figure. Similar to that shown in FIG. 4, a source region 6n and a drain region 8n are formed in the transistor 100n. In the p-channel transistor 100p,
A lightly doped drain extension 3 is formed to contact between the source region 6p and the body node 12n of the transistor 100p.
There are n ten contact areas 30n with 8n. The structure of FIG. 5e is then subjected to a direct reaction silicidation step as described above to connect the source nodes 6p, 6n and the body node 12n via their respective contact areas 3.n and 30p.
, 12p are obtained, respectively.

As is clear from the steps shown in FIGS. 5a to 58, So
When implemented in the manufacturing process of l CMO3, no additional masking steps are required to form the source-body contact according to the invention. It should be noted that the order in which the implants are performed (ie, p-type implants before n-type implants) is arbitrary. The resulting structure can equally be formed with an n-type implant before a p-type implant, if desired.

FIG. 6 illustrates in plan view a transistor 200 constructed in accordance with a second embodiment of the invention.

Transistor 200, like transistor 100 of FIG. 3, is shown prior to silicidation to connect p-contact region 30 to source region 6. Transistor 200, like transistor 100 of FIG.

Transistor 200 has a number of p+ contact regions 30 located not only at the edges of mesa 5 but also inside transistor 200. In SO transistors, such as transistor 200, which require additional drive capability due to their large channel width-to-length ratio, the body node 12 is connected from the source region 6 through the p+ contact region 30 due to the relatively low doping concentration. , the bias may not be uniform over a relatively long width. Therefore, an inner p+ contact region 30 is provided to provide a more uniform bias across the width of the underlying body node 12. The characterization of a transistor fabricated according to a certain set of process parameters and geometries is such that contact area 30 provides a constant bias as described above.
may indicate that the distance must be less than a certain distance.

Therefore, in this case, the intervals between the plurality of contact areas 30 do not necessarily have to be uniform as shown in FIG. 6, but the contact areas 30 are spaced apart by a certain distance or less.

Note that for particularly narrow transistors, a single contact region 30 at one edge of the source region 6 may be sufficient to uniformly bias the body node 12. Since each contact region 30 reduces the effective channel width of the transistor, the number and size of contact regions 30 are determined by the body node 12.
Preferably, it is the minimum necessary to provide a sufficiently similar bias to .

Furthermore, it is noted that the contact area 30 provided according to the invention does not require any additional patterning during the formation of the mesa 5 or the gate electrode 10, except for the mask used in the implantation step. Therefore, there is no need to specify which side of the transistor will be the source and which side will be the drain until the implantation step is performed. Thus, the present invention is particularly advantageous for forming transistors in gate arrays and other mask programmable logic circuits. This is because the mask used to form mesa 5 and gate 10 is common to all devices fabricated in the same process, and the individualization of the gate array (and identification of sources and drains) is done by the implant mask. be.

Additionally, such devices may include transistors for which contact with the body node is undesirable, such as pass control transistors; in such cases, contact region 3
0 can be excluded using the same implant mask level.

7 and 8, a transistor 100 constructed in accordance with the present invention is shown;
The same reference numerals are used to designate the same components as used in the conventional transistor 1 of the figure. Transistor 100 includes contacts between the source and body nodes to alleviate the floating body node problem discussed above with respect to conventional transistor 1, as described below.

The plan view of FIG. 7 shows a p+ contact region 30 provided at the edge of the mesa on the source side of the gate electrode 10.

Sidewall oxide filaments 16 are not shown in FIG. 7 to indicate the presence of an n-type lightly doped drain extension 19 disposed at the surface between p-contact region 30 and gate electrode 10. The conduction channel of transistor 100 thus extends along the entire edge of gate electrode 10 on the source side and p
The contact area 30 is remote from the conducting channel. The plan view of FIG. 7 shows the state of the transistor 100 before silicidation; as explained below, the source region 6 is formed on the surface.
Preferably, silicide cladding is used to provide an electrical connection from source region 6 to body node 12 below gate electrode 10 by connecting p to contact region 30.

On the drain side of gate electrode 10, a lightly doped drain extension 18 is shown.

It should also be noted that placing the p+ contact region 30 at the edge of the mesa 5 is not essential to providing contact between the body node 12 and the source region 6. However, the application was filed on February 1, 1988, and Tecas In
1. As described in pending U.S. Patent Application No. 150,799, assigned to Struments, Inc. The presence of the p+ contact region 30 at the edge of the mesa ensures that the source of the transistor 100 when exposed to ionizing radiation
Reduces leakage between drains.

Furthermore, it should be noted that the active semiconductor formed on the insulator film 4 may contain a relatively large number of dislocation defects compared to the active region in the bulk in many SOI technologies. These dislocations, particularly along the edges of silicon mesas such as mesa 5, prevent the diffusion dopants forming the source and drain double head regions 6.8 from diffusing through the body region 12, especially along the edges of mesa 5. It may be allowed. This multiplicative diffusion can cause short channel effects such as subthreshold leakage in transistor 100, and if the diffused dopant extends as far as the source region 6 and drain region 8, it may cause the drain region 8 to This causes a short circuit to the source region 6. The placement of the contact region 30 at the edge of the mesa 5 reduces the source 71147 leakage due to multiplication diffusion as described above by isolating the dopant of the source region 6 from the edge of the mesa 5 on the gate electrode 10 side. , so that multiplication diffusion into the body region 12 occurs only from the drain side. Additionally, the placement of contact region 30 to the edge of mesa 5 is such that the dopant from drain region 8 diffuses along the edge of mesa 5 through body region 12 between p+'p1
Since four regions are placed, the dopants arriving from the drain region 8 completely below the gate electrode form only a reverse biased diode (the contact region 30 is at the same potential as the source region 6). Therefore, placement of contact region 30 at the edge of mesa 5 reduces source-to-source leakage due to enhanced interfacial diffusion of the source/drain hunt.

Referring now to FIG. 8, transistor 100 is shown in cross-section. FIG. 8 shows that a p+ contact region 30 is disposed adjacent to the n-type lightly doped drain extension 19 located below the sidewall filament 1G on the source side of the gate electrode 10. ing. Since the lightly doped drain extension 19 is n-type, it is ohmically connected to the n+ source region 6. In this embodiment, as in the first and second transistors 1, the source region 6 and the drain region 8 extend through the entire thickness of the mesa 5 as well as the p-contact neck region 30. Note that the p contact region 30 does not necessarily have to completely extend to the insulating film 4 in this way in order to make contact with the body node 12.

However, the contact region must extend to a depth sufficient to contact the body region that remains in a depletion layer below the channel of transistor 100 when conductive.

FIG. 8 also shows that a silicide film 22 is provided on the surface of the silicon structure (source region 6, p contact region 30, drain region 8, and gate e1M10). Although the ohmic connection between the p-contact region 30 and the source region 6 can be formed by other interconnection means, such as, for example, a conventional contact through an overlying insulator film to a metallization layer. Silicide film 22
provides a low resistance connection between the two without the need for additional masking steps. As known in the art,
The use of sidewall oxide filaments 16 not only promotes the formation of graded junctions in the transistor, but also ensures that the silicide film 22 on the source and drain regions 6.8 (as well as the p-contact region 30), respectively, overlaps the silicide on the surface of the gate electrode 10. While minimizing the risk of electrical short circuit with the membrane 22,
It also enables silicidation by self-alignment of the source, drain, and gate regions.

Note that in the transistors of FIGS. 7 and 8, there is no contact between the p+ contact region 30 and the drain region 8. Therefore, the p+ contact region 30 is the body node 1
2 can be doped as strongly as possible without concern for drain-source junction breakdown through the contact region 3o. If the channel length is 1 micron, an example of the doping concentration of each region of the transistor 100 according to the present invention is podinode 2.
has an impurity concentration of 10'7/cm', p +
Contact region 30 (D impurity concentration C10I11~1o
21/cII+1. The source and drain double head area 6.8 is typically 10” to 10”/cmff (7
) impurity concentration and low doped drain regions 18 and 19
is 10111 to 10211 depending on the desired dopant gradient.
/cm” range.

9a-98, steps in the formation of an n-channel transistor 100n and a p-channel transistor 100p as formed in a CMO3 circuit will now be discussed. The cross-sectional views of Figures 9a-9e are taken along a similar location to that of Figure 8, ie, through the portion of transistor 100 where the source-to-body contact is present. In FIG. 9a, two mesas 5n and 5p are shown formed on insulator layer 4; mesa 5n is n-type silicon and mesa 5p is p-type silicon. There is a gate oxide 14 on each mesa 5n and 5p as well as a patterned polysilicon gate electrode 1o; thus the structure of FIG.
The source and drain doublets 6.8 and the contact areas 30 are now ready to be formed. FIG. 9a shows p-channel transistor 100 while covering certain portions of the structure.
Also shown is a mask layer 40 that exposes the areas where p-type implants are to be made to form lightly doped p drain extensions 18p and 19p. Mask N4o may be a patterned photoresist or a hard mask layer such as commonly used to block ion implantation. The pattern of the mask layer 4o is such that the mask layer 4° overlaps the gate electrode 10 and the mesa 5
Preferably, the design is such that it also overlaps with the edges of the

As shown in Figure 9a, the structure is exposed to a p-type implant of boron or another p-type dopant, using doses and energies conventional in such implants to form lightly doped drain extensions 18 and 19. form.

Referring to FIG. 9b, after the injection of FIG. 9a and after the injection of FIG.
The structure is shown after the formation of a mask layer 42 which protects the regions where the p-type implants of figure a have been made and which exposes the regions of the structure where the n-type lightly doped drain implants are to be made. FIG. 9b shows the lightly doped drain extension 18p.
and 19p are each shown to have been driven (driven) to almost the final depth. In addition, No. 9a-9
Note that each implant shown in Figure b is not implanted immediately after each masking step, but one implant anneal is performed after all four previous implants are performed. The point in time at which the implant anneal or implants are performed is not critical to the fabrication of structures according to the present invention; however, for ease of explanation of the masking process, the implant anneal after each implant is shown in Figures 9a-9d. It is. Figure 9b shows an n-type (arsenic, phosphorus, or other conventional dopant) lightly doped drain implant.
The structure is shown to be acceptable under normal doses and energies.

Referring now to FIG. 9c, transistors 100n and 100p receive strong p-type source/drain implants.
is the indication. A sidewall oxide filament 16 is attached to each gate electrode 1 to protect a portion of region 18p of transistor 100p and region 19n of transistor 100n from strong source/drain implants so that a graded junction is obtained.
It is placed at a predetermined location adjacent to both sides of 0. Sidewall oxide filaments 16 are described in U.S. Pat. No. 4,356, supra.
623, by depositing an oxide layer, such as by decomposition of TE01, and then anisotropically etching the oxide, leaving sidewall oxide filaments 16 behind. Mask layer 50 is formed to protect n-type implant region 18n and most of region 19n from p-type source/drain implantation. A portion of region 19n adjacent sidewall oxide filament 16 is not protected by mask layer 50 so that p-type contact region 30p (indicated by ill) can be formed by p-type source/drain implantation. The mask layer 50 also includes the p-type implanted region 1
8p (excluding the portion protected by filament 16) and most of region 19p are exposed to the p+ source/drain implant; n+ contact region 30n (
The implantation required to form a p+ source/
A portion of region 19p adjacent sidewall oxide filament 16 is covered with mask layer 50 so that no drain implant is required.
Not protected by. Then, as shown in FIG. 9C, p
Type source/drain implants are performed according to the doses and energies customary for such implants.

FIG. 9d shows that transistor 100p has a source region 6p and drain region 8p, and transistor 100n has a p contact region 30p that contacts the body node of transistor 100n. Also shown in FIG. 9d is a final source/drain pattern mask layer that protects plff regions 6p, 8p, and 30p from n-type source/drain implants and exposes regions of transistors 100n and 100p that receive the implants. 52 is also shown. The implantation of FIG. 9d therefore ultimately forms the source and drain regions 6n, 8n of transistor 100n, respectively, and the implantation of transistor 100n shown in FIGS. 7 and 8.
Transistor 100 similar to p10 contact region 30 of 00
An n+ contact region 30n for contact between the p source region 6p and the body node is also formed.

After the implant anneal, the result of the implant in Figure 9d is shown in Figure 5e.
It is shown in the figure. Similar to that shown in FIG. 8, a source region 6n and a drain region 8n are formed in the transistor 100n. In the p-channel transistor Loop,
The contact region 30n is a p-type lightly doped drain extension 19p so as to contact between the source region 6p and the body node 12n of the transistor 100p when silicided.
Adjacent to. The structure of FIG. 9e is then subjected to a direct reaction silicidation step as described above to connect the source node 6p, via the respective contact regions 30n and 30p.
6n and body node 12n.

An ohmic connection between 12p and 12p is obtained, respectively.

As is clear from the steps shown in Figures 9a to 9e, So
When implemented in the manufacturing process of l CMO3, no additional masking steps are required to form the source-to-body contact according to the invention. It should be noted that the order in which the implants are performed (ie, p-type implants before n-type implants) is arbitrary. The resulting structure can have an n-type before the p-type if desired.
It can be equally formed by injection of the shape.

FIG. 10 shows in plan view a transistor 200 constructed in accordance with a fourth embodiment of the present invention.

Transistor 200, like transistor 100 of FIG. 7, is shown prior to silicidation to connect p-contact region 30 to source region 6.

Transistor 200 has a number of p+ contact regions 30 located not only at the edges of mesa 5 but also inside transistor 200. In a 5OII-transistor, such as transistor 200, which needs to have additional drive capability due to its large channel width-to-length ratio, the body node 12 is separated from the source region 6 to the contact region 30 due to its relatively low doping concentration. may not receive a uniform bias over a relatively long width. Therefore, an inner p+ contact region 30 is provided to provide a more uniform bias across the width of the underlying body node 12. The characterization of a transistor fabricated according to a certain set of process parameters and geometry is:
To provide a constant bias as described above, the contact area 3
0 may indicate that the distance must be less than or equal to a certain distance.

Therefore, in this case, the intervals between the plurality of contact areas 300 do not necessarily have to be uniform as shown in FIG. 10, but the contact areas 30 are spaced apart by a certain distance or less.

Note that for particularly narrow transistors, a single contact region 30 at one edge of the source region 6 may be sufficient to uniformly bias the body node 12. Since each contact region 30 reduces the effective channel width of the transistor, the number and size of contact regions 30 is determined by the body node 12.
Preferably, it is the minimum necessary to provide a sufficiently similar bias to .

Furthermore, it is noted that the contact area 30 provided according to the invention does not require any additional patterning during the formation of the mesa 5 or the gate electrode 10, except for the mask used in the implantation step. Therefore, there is no need to specify which side of the transistor will be the source and which side will be the drain until the implantation step is performed. Thus, the present invention is particularly advantageous for forming transistors in gate arrays and other mask programmable logic circuits.

This is because the mask used to form mesa 5 and gate 10 is common to all devices fabricated in the same process, and the individualization of the gate array (and identification of sources and drains) is done by the implant mask. be. Additionally, such devices may include transistors for which contact with the body node is undesirable, such as pass control transistors; in such cases, contact region 30 may be excluded using the same implant mask level.

In the transistor described above, a lightly doped drain region 19 of the same conductivity type as the source region 6 is provided between the contact region 30 and the body node 12 on the surface of the transistor. given the connection. However, because of this structure, the current flow through the portion of the lightly doped drain region 19 adjacent to the contact region 30 is stronger (because it has to travel a longer path to reach the doped source region 6) However, the increased resistance is parallel to the low resistance current path where the lightly doped drain region 19 adjoins the source region 6. The increase in resistance is minimal.Thus, the present invention provides a body-source connection without reducing the channel width, with minimal impact on the source/drain resistance of the transistor when conducting.

Referring now to FIG. 11, a top view of another embodiment of the present invention is shown. As mentioned above, 5OII due to multiplicative diffusion of drain dopants, especially along the edges of mesa 5.
- Edge leakage of the transistor is reduced by placing the contact area 30 at the edge of the mesa 5. Multiplying diffusion that causes edge leakage can occur not only at the bottom of mesa 5 (i.e., at the interface with insulator layer 4) but also at the top surface under gate dielectric 14, so that in transistor 300 shown in FIG. , a further reduction in edge leakage is obtained.

The transistor 300 has a lightly doped drain extension region 19 of the same conductivity type as the source region 6 (n-type in this example), and the region 19 is connected to the transistor 300 located below the gate electrode 10 and inside the body region 12. So, each contact area 3
It is arranged on the surface between 0 and 0. However, transistor 3
In the contact area 30 located at both edges of the mesa 5 of 00,
A lightly doped drain extension region 39 of the same conductivity type as the contact region 30 (p-type in this example) is provided at the surface of the structure. As a result, the dopant source for multiplication diffusion is removed, i.e., the dopant diffusion from region 39 is reduced to body region 1.
Edge leakage is minimized by providing diode isolation also at the top surface of mesa 5 when such multiplication diffusion occurs (same conductivity type as 2). The overall width of the channel is of course reduced by the lightly doped drain extension regions 19, but it is also reduced by the contact regions 3 located on both edges of the mesa 5.
It is only due to 0.

The transistor 300 of FIG. 11 is unique in that the region 39 to be formed must be masked from receiving the lightly doped drain implant provided for the source and drain doublets 6.8, and of course of the opposite conductivity type. The transistors 100 and 200 can be fabricated in much the same way as transistors 100 and 200, except that they must be exposed to a lightly doped drain implant.

Although the invention has been described in detail with reference to preferred embodiments, it is to be understood that the foregoing description is intended to be illustrative only and not to be construed in a limiting sense. It is also to be understood that numerous changes in the details of the embodiments of the invention and additional embodiments of the invention will be apparent and may be made to those skilled in the art upon reference to this specification. Such modifications and additional embodiments are intended to be embraced within the spirit and true scope of the invention as defined by the claims.

In connection with the above description, the following items are disclosed.

1. In a transistor formed on a semiconductor layer located on an insulating film: a gate electrode located on a body node portion of the semiconductor layer, the body node portion being of a first conductivity type, and having first and second conductivity types;
a drain region of the semiconductor layer, the drain region having a second side surface;
a conductivity type and is disposed adjacent to the first side surface of the body node portion; a source region of the semiconductor layer, the source region being the second
a first contact region of the semiconductor layer, the first contact region being of the first conductivity type and disposed adjacent to a second side surface of the body node portion; and an ohmic connection between the first contact region and the source region, the ohmic connection being located on the first contact region and the source region or in a fracture. A transistor made of a metal silicide film.

2. The transistor of claim 1, wherein the first contact region is disposed along an edge of the semiconductor layer.

3. The transistor of clause 1, wherein the drain, source and first contact regions extend through the entire thickness of the semiconductor layer.

4. The transistor of item 1 further comprising a gate dielectric layer disposed between the gate electrode and the body node portion.

5. The transistor of item 1 further comprising sidewall dielectric filaments disposed along both sides of the gate electrode.

6. The transistor of claim 5, wherein the drain region includes a lightly doped region adjacent the first side of the semiconductor layer and underlying a sidewall dielectric filament.

7. The transistor of claim 6, wherein the source and first contact regions each include a lightly doped region adjacent a second side of the body node portion and each underside a sidewall dielectric filament.

8. The transistor of item 1, wherein the semiconductor layer is a mesa located on the insulating film.

9. An eighth contact region further comprising a second contact region of the first conductivity type disposed adjacent to a second side surface of the body node portion.
term transistor.

IO0 The transistor of claim 9, wherein the second contact region is disposed adjacent the second edge of the mesa.

(2) The transistor according to item 1, further comprising a second contact region of the first conductivity type disposed adjacent to the second side surface of the body node portion.

12. The transistor of clause 1, wherein the second contact region is disposed adjacent a second edge of the semiconductor layer.

13. In a transistor formed on a semiconductor layer located on an insulating film: a gate electrode located on a body node portion of the semiconductor layer, the body node portion being of a first conductivity type, and having first and second conductivity types;
a drain region of the semiconductor layer, the drain region having a second side surface;
a conductivity type and is disposed adjacent to the first side surface of the body node portion; a source region of the semiconductor layer, the source region being the second
a plurality of contact regions of the semiconductor layer, the contact regions being of the first conductivity type and disposed adjacent to a second side surface of the body node portion; and an ohmic connection between each of the contact regions and the source region, the first and second of the contact regions being adjacent an edge of the semiconductor layer; Transistor located.

14. The transistor of clause 13, wherein the plurality of contact regions are spaced apart from each other by a distance less than a predetermined distance along the second side surface of the body node portion.

15. The transistor according to item 13, wherein the semiconductor layer is a mesa located on the insulating film.

16. The transistor of claim 15, wherein said first and second contact regions are disposed along first and second edges of said mesa, respectively.

17. The transistor of item 13, wherein the ohmic connection comprises a refractory metal silicide film located on the source region and each contact region.

18. In an integrated circuit formed overlying an insulating film: In a first transistor formed in a semiconductor layer located on the insulating film: A body node portion of the semiconductor layer having a first conductivity type; the body a gate electrode located on a node portion; a drain region of the semiconductor layer, where the drain region is a second
a source region of the semiconductor layer, the source region being of the second conductivity type and disposed adjacent to the body node portion;
a contact region of the semiconductor layer, the contact region being of the first conductivity type and disposed adjacent to the body node portion on a side opposite to the drain region; and a first transistor disposed adjacent to the source region; and an ohmic connection between the contact region and the source region; and a second transistor formed in the semiconductor layer; a body node portion of the semiconductor layer that is of a conductive type; a gate electrode located on the body node portion; a drain region of the semiconductor layer, the drain region being a first
a conductivity type and is disposed adjacent to the body node portion; a source region of the semiconductor layer, the source region being the first
a contact region of the semiconductor layer, the contact region being of the second conductivity type and disposed adjacent to the body node portion on a side opposite to the drain region; and a second transistor disposed adjacent the source region; and an ohmic connection between the contact region and the source region.

19. The integrated circuit of claim 18, wherein the ohmic connections of the first and second transistors each comprise a refractory metal silicide film located over the source regions and contact regions of the first and second transistors.

20. The first transistor is formed in a first semiconductor mesa located on the insulating film; and the second transistor is formed in a second semiconductor mesa located on the insulating film. Term integrated circuit.

21. The integrated circuit of clause 18 further comprising sidewall dielectric filaments disposed along both sides of the gate electrode.

22. The integrated circuit of claim 21, wherein the drain region includes a lightly doped region adjacent the first side of the semiconductor layer and underlying a sidewall dielectric filament.

23. The integrated circuit of claim 22, wherein the source and first contact regions each include a lightly doped region adjacent a second side of the body node portion and each underside a sidewall dielectric filament.

24. The integrated circuit of claim 23, wherein said ohmic connection comprises a refractory metal silicide film located over said source region and first contact region.

25. In a method for fabricating an integrated circuit in a semiconductor layer located on an insulating film: in the step of defining first and second portions of the semiconductor layer, the first and second portions are defined as first and second portions, respectively. forming a gate electrode on each of the first and second portions; applying a first mask layer on the first and second portions; and forming a gate electrode on each of the first and second portions; exposing a contact region adjacent to the source side of the gate electrode on the second portion; and exposing a contact region adjacent to the source side of the gate electrode on the second portion; doping exposed portions of the first and second portions with a dopant of the first conductivity type; a second mask layer is applied over the first and second portions, exposing contact areas of the second portion and source and drain regions of the first portion; coating the source and drain regions of the fourth and second
A method comprising: doping exposed portions of the portions with a dopant of the second conductivity type; and forming a silicide film over source and contact regions of the first and second portions.

26. The doping step includes: implanting dopant ions of the first conductivity type into the portion exposed by the first mask layer; implanting dopant ions of the second conductivity type into the portion exposed by the second mask layer; 26. The method of claim 25, comprising the steps of implanting dopant ions; and annealing and diffusing the implanted ions.

27. The method of claim 25, wherein the doping step dopes the doped portion of the semiconductor layer through the entire thickness of the semiconductor layer.

28. Before the step of forming the silicide film: forming sidewall dielectric filaments on both sides of the gate electrode;
coating a portion of the semiconductor layer adjacent to the gate electrode; applying a third mask layer over the first and second portions to expose contact regions of the first portion and source and drain regions of the second portion; while coating contact regions of the second portion and source and drain regions of the first portion; additionally doping exposed portions of the first and second portions with a dopant of the first conductivity type; a fourth mask layer is applied over the first and second portions, exposing contact areas of the second portion and source and drain regions of the first portion; coating the source and drain regions of;
and additionally doping exposed portions of the first and second portions with a dopant of the second conductivity type.

29. The method of clause 28, wherein the additional doping step dopes the semiconductor layer more highly than the doping step.

30. The method of claim 25, wherein the defining step comprises forming a semiconductor layer mesa on the insulating film.

31. In a transistor formed on a semiconductor layer located on an insulating film: a gate electrode located on a body node portion of the semiconductor layer, the body node portion being of a first conductivity type and having first and second side surfaces; the gate electrode is located on a surface of the semiconductor layer opposite to the insulating film; a drain region of the semiconductor layer, the drain region being a second
a conductivity type and is disposed adjacent to the first side surface of the body node portion; a source region of the semiconductor layer, the source region being the second
a first portion adjacent to the second side surface of the body node portion; and a second portion adjacent to the first portion, the conductivity type being relatively stronger (doped) than the first portion; a first contact region of said semiconductor layer, said first contact region being of said first conductivity type, and comprising: a second portion of said source region and a second portion of said source region; disposed on the surface of the semiconductor layer in a direction perpendicular to the gate electrode between and having a depth greater than the first portion of the source region such that a first contact region contacts the body node portion; A transistor comprising: an ohmic connection between a first contact region and the source region.

32. The transistor of claim 31, wherein the ohmic connection comprises a refractory metal silicide film located over the first portion of the source region and the first contact region.

33. The transistor of clause 32, wherein the drain, source and first contact regions extend through the entire thickness of the semiconductor layer.

34. The transistor of item 31, further comprising a gate dielectric layer disposed between the gate electrode and the body node portion.

35. 32. The transistor of clause 31 further comprising a sidewall dielectric filament adjacent the gate electrode.

36, the drain region includes: a first portion adjacent to the first side surface of the body node portion; and a second portion adjacent to the first portion, the drain region being doped relatively more strongly than the first portion. 32. The transistor of clause 31, comprising two parts;

37. The transistor of item 36, wherein the ohmic connection comprises a refractory metal silicide film located on the deep portion of the source region and the first contact region.

38. The transistor according to item 31, wherein the semiconductor layer is a mesa located on the insulating film.

39. The transistor of clause 38, wherein the first contact region is disposed adjacent the first edge of the mesa.

40, the first conductivity type and the second portion of the mesa between the first portion of the source region and the second portion of the source region;
40. The transistor of claim 39, further comprising a second contact region disposed on the surface of the semiconductor layer along an edge and having a depth greater than the first portion of the source region so as to contact the body node portion.

41, the first conductivity type and the second conductivity type of the source region;
a second contact region disposed on the surface of the semiconductor layer in a direction perpendicular to the gate electrode adjacent to the first portion of the source region and having a deeper depth than the first portion of the source region so as to be in contact with the body node portion; The transistor of item 31, further comprising:

42. The semiconductor layer is a mesa located on the insulating film; the second contact region is disposed adjacent to an edge of the mesa; and the second contact region is: of the body node portion. 42. The transistor of clause 41, comprising: a first portion adjacent to a second side surface; and a second portion adjacent to the first portion, the second portion being relatively more heavily doped than the first portion.

43. In a transistor formed on a semiconductor layer located on an insulating film: a gate electrode located on a body node portion of the semiconductor layer, the body node portion being of a first conductivity type and having first and second side surfaces. the gate electrode is located on a surface of the semiconductor layer opposite to the insulating film; a drain region of the semiconductor layer, the drain region being a second
a conductivity type and is disposed adjacent to the first side surface of the body node portion; a source region of the semiconductor layer, the source region being the second
a lightly doped portion adjacent to the second side surface of the body node portion; and a highly doped portion adjacent to the doped portion, extending deeper from the surface of the semiconductor layer than the lightly doped portion. a plurality of contact regions of said semiconductor layer, said contact regions being of said first conductivity type, each comprising a lightly doped portion of said source region and a highly doped portion of said source region; disposed on the surface of the semiconductor layer in a direction perpendicular to the doped electrode between and having a depth greater than the lightly doped portion of the source region such that each contact region contacts the body node portion; an ohmic connection between a contact region and the source region.

44. The plurality of contact areas are spaced apart from each other such that the body node portions are substantially uniformly biased.
Term 3 transistor.

45. The transistor according to item 43, wherein the semiconductor layer is a mesa located on the insulating film.

46. The transistor of clause 45, wherein the first contact region is disposed adjacent the first edge of the mesa.

47. The transistor of clause 46, wherein the second contact region is disposed adjacent the second edge of the mesa.

48. In an integrated circuit formed overlying an insulating film; In a first transistor formed in a semiconductor layer located on the insulating film; In a body node portion of the semiconductor layer having a first conductivity type; In the insulating film; a gate electrode located on the body node portion on the opposite surface of the semiconductor layer; a drain region of the semiconductor layer, the drain region being a second
A source region of the semiconductor layer, the source region being of the second conductivity type and disposed adjacent to the body node portion.
The semiconductor has a conductivity type of: a first portion disposed adjacent to the body node portion on a side opposite to the drain region; and a second portion disposed adjacent to the first portion; a contact region of the semiconductor layer, the contact region being of the first conductivity type, between the first portion of the source region and the second portion of the source region in a direction perpendicular to the gate electrode; a contact region extending from the surface of the semiconductor layer deeper than a first portion of the source region to contact the body node portion; and an ohmic connection between the contact region and the source region; a first transistor comprising; an integrated circuit comprising;

49. In the second transistor formed in the semiconductor layer: a body node portion of the semiconductor layer that is of a second conductivity type; a gate electrode located on the body node portion on the surface of the semiconductor layer; a drain region, the drain region being a first
a conductivity type and is disposed adjacent to the body node portion; a source region of the semiconductor layer, the source region being the first
The semiconductor has a conductivity type of: a first portion disposed adjacent to the body node portion on a side opposite to the drain region; and a second portion disposed adjacent to the first portion; a contact region of the semiconductor layer, the contact region being of the second conductivity type, between the first portion of the source region and the second portion of the source region in a direction perpendicular to the gate electrode; a contact region extending from the surface of the semiconductor layer deeper than a first portion of the source region to contact the body node portion; and an ohmic connection between the contact region and the source region; 49. The integrated circuit of clause 48, further comprising; a second transistor;

50. The ohmic connection of the first and second transistors is comprised of a metal silicide film located on the second portion of the source region and the contact region of the first and second transistors, respectively. integrated circuit.

51, wherein the first transistor is formed in a first semiconductor mesa located on the insulating film; and 48, wherein the second transistor is formed in a second semiconductor mesa located on the insulating film. Term integrated circuit.

52. The integrated circuit of clause 48 further comprising a sidewall dielectric filament adjacent the gate electrode.

53. In a method for fabricating an integrated circuit in a semiconductor layer located on an insulating crotch: defining first and second portions of the semiconductor layer, the first and second portions forming first and second portions, respectively; forming a gate electrode on each of the first and second portions; applying a first mask layer on the first portion to form a source and a drain adjacent to the gate electrode on the first portion; doping source and drain locations of the second portion adjacent to the gate electrode with a dopant of the first conductivity type; applying a second mask layer on the second portion; doping source and drain regions of the first portion adjacent to the gate electrode with a dopant of the second conductivity type; coating both sides of the gate electrode; forming a sidewall dielectric filament to cover a portion of the semiconductor layer adjacent to the gate electrode; applying a third masking layer over the first and second portions and covering the sidewall dielectric filament on the side of the gate electrode; a contact area of the second portion adjacent to the sidewall dielectric filament on the source side of the gate electrode, while exposing a contact area of the first portion adjacent to the sidewall dielectric filament and a source and drain region of the second portion; coating the source and drain regions of the first portion; additionally doping the exposed portions of the first and second portions with a dopant of the first conductivity type;
a fourth masking layer is applied over the portion exposing the contact region of the second portion and the source and drain regions of the first portion; additionally doping exposed portions of the first and second portions with a dopant of the second conductivity type; and depositing a silicide film over the source and contact regions of the first and second portions. A method comprising: forming.

54. The doping step includes: implanting dopant ions of the first conductivity type into the portions exposed by the first mask layer; implanting dopant ions of the second conductivity type into the portions exposed by the second mask layer; 54. The method of clause 53, comprising the steps of: implanting dopant ions of; and annealing and diffusing the implanted ions.

55. The method of clause 53, wherein the doping step dopes the doped portion of the semiconductor layer through the entire thickness of the semiconductor layer.

56. The method of clause 53, wherein the additional doping step dopes the semiconductor layer more highly than the doping step.

57. The method of claim 53, wherein the defining step comprises forming a semiconductor layer mesa on the insulating film.

58. In a method of fabricating an integrated circuit in a semiconductor layer located on an insulating film: defining an active part of the semiconductor layer of a first conductivity type; forming a gate electrode on the active part; doping source and drain locations of the active portion adjacent to the gate electrode with a dopant of a second conductivity type; forming sidewall dielectric filaments on both sides of the gate electrode; coating a portion adjacent to a gate electrode; applying a first mask layer over the active portion to cover a contact area of the active portion adjacent to the sidewall dielectric filament on the source side of the gate electrode; exposing the source and drain regions of the portion; doping the source and drain regions exposed by the first mask layer with a dopant of the second conductivity type; exposing the contact region and doping the source and drain regions exposed by the first mask layer; doping contact areas exposed by the second mask layer with a dopant of the first conductivity type; and forming a silicide film over the source and contact areas. ; A method including;

59. The method of claim 58, wherein the step of applying a first mask layer and doping the source and drain regions exposed by the first mask layer precedes the step of applying a second mask layer and doping the contact regions. Method.

60. The method of claim 58, wherein the step of applying a second mask layer and doping the contact regions precedes the step of applying a first mask layer and doping the source and drain regions exposed by the first mask layer. Method.

61, silicon-on-insulator (So I) MOS l-transistor (1) with an implanted region (3o) in contact with the body node (12) on the source side (6) of the gate electrode (1o)
00) is disclosed. A contact region (3o) of the same conductivity type as the body node (12) (for example a p-region in an n-channel transistor) is formed in the source region (6) in a self-aligned manner with respect to the gate electrode (1o). There is. The adjacent source regions (
An ohmink connection is formed between 6) and the contact area (3o). Since the contact region (3o) is of the same conductivity type as the body node (12), a non-rectifying ohmic connection is formed between the source (6) and body (12) nodes of the transistor. For SOI CMOS technology, no additional masking steps are required for forming the contact regions, since the source/drain implant mask required to mask regions of opposite conductivity type can be used to form the contact regions.

[Brief explanation of the drawing]

Figures 1 and 2 are a plan view and a cross-sectional view of a conventional Sol MOS transistor, respectively, and Figure 3 is a diagram of a conventional Sol MOS transistor before silicide.
4 is a cross-sectional view of the transistor of FIG. 3 after silicidation; FIGS. 5a-5e are respective views of p-channel and n-channel transistors according to the invention. 6 is a plan view of a SOT MOS transistor constructed according to the second embodiment of the present invention, and FIG. 7 is a cross-sectional view showing the manufacturing process, and FIG. 7 is a plan view of a SOT MOS transistor constructed according to the third embodiment of the present invention before silicide A plan view of the SOI MOS transistor, FIG. 8 is a cross-sectional view of the transistor of FIG. 7 after silicide, and FIG. 9a is a cross-sectional view of the transistor of FIG.
9e are cross-sectional views showing each manufacturing process of p-channel and n-channel transistors according to the present invention, and FIG. 10 is a SOI MO3I constructed according to a fourth embodiment of the present invention.
- Plan view of transistor; FIG. 11 is a plan view of an soI MOS transistor constructed in accordance with a fifth embodiment of the present invention; 100.200,300...Transistor, 4
...Insulating (body) film, 5...Semiconductor N (
mesa), 6...source region, 8...drain region, 1o...gate electrode, 12...
. . . Body node portion, 14 . . . Gate dielectric layer, 6 . . . Side wall dielectric filament, 18.19
, 38.39...Low doped region, 22...
・・Silicide film, 30・Old・・Contact area, 40° 42
．． 50.52・Old・・Mask layer. An engraving of the drawing (no changes to the content)

Claims (1)

[Claims] In a transistor formed in a semiconductor layer located on an insulating film: a gate electrode located on a body node portion of the semiconductor layer, the body node portion being of a first conductivity type, and a first conductivity type; and second
a drain region of the semiconductor layer, the drain region having a second side surface;
a conductivity type and is disposed adjacent to the first side surface of the body node portion; a source region of the semiconductor layer, the source region being the second
a first contact region of the semiconductor layer, the first contact region being of the first conductivity type and disposed adjacent to a second side surface of the body node portion; and an ohmic connection between the first contact region and the source region, the ohmic connection being a refractory metal silicide on the first contact region and the source region. A transistor comprising: a film;