JPH02148125A - Magnetic disk controller - Google Patents

Abstract

PURPOSE:To transfer data at a high speed and to reduce the bit unit price by dividing a system bus into plural bit areas and providing magnetic disk control circuits and magnetic disk devices whose number corresponds to the division number to change serial transfer to apparent parallel transfer. CONSTITUTION:A system bus 14 is divided into plural bit areas. and data of respective divided bit areas are processed by data processing mechanisms consisting of a memory 13 as the main storage device, magnetic disk controllers 4 to 7, and magnetic disk devices 8 to 11 respectively. Consequently, data is apparently transferred in parallel to increase the transfer speed. Thus, a magnetic disk controller is obtained which is capable of high-speed transfer and has the bit unit price reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a magnetic disk control device, and particularly to high-speed data transfer.

C. Problems to be solved by the conventional technology and invention WJ. Conventional magnetic disk control devices transfer a large amount of data to and from the magnetic disk device, and when this is desired to be done in a short period of time, the main body of the magnetic disk device is However, such magnetic disk drives are expensive and have a special interface, so they cannot be easily adopted.

There are also magnetic disk devices for parallel transfer (for example, magnetic disk devices for high-speed transfer that have multiple data input/output channels on the same cylinder), but they are special.
It was extremely expensive.

An object of the present invention is to obtain a magnetic disk control device that enables high-speed transfer and lowers the bit unit cost by arranging and using a plurality of general-purpose magnetic disk devices in parallel.

[Means for Solving the Problems] A magnetic disk control device according to the present invention includes a plurality of data holding means each connected to a system bus by dividing its bits and having a storage capacity of at least one track of a magnetic disk device. a plurality of magnetic disk control circuits each connected to the plurality of data holding means and configured to exchange data between the plurality of data holding means and the plurality of magnetic disk devices; and a plurality of magnetic disk control circuits that directly access data to the main storage device. a DMA controller that performs data transfer between the main storage device and the plurality of data holding means;
It has a plurality of data holding means, a plurality of magnetic disk control circuits, and a control means for controlling the operation timing of the DMA controller.

[Function] In the present invention, the system bus is divided into a plurality of bits, and each data in each divided bit area is processed by a data processing mechanism consisting of a data holding means, a magnetic disk control circuit, and a magnetic disk device. Since the data is processed, it appears to be a parallel transfer and the transfer speed is increased.

Embodiment FIG. 1 is a block diagram showing the configuration of a magnetic disk control device according to an embodiment of the present invention. In the figure, (1)
is a CPU, (2) is a dual port RAM, and H) is a sub CPU. (4) to (7) are magnetic disk controllers, mainly first-in/first-out circuits (hereinafter referred to as FIFO) (4a) to (7a) and magnetic disk control LSI (hereinafter referred to as IDC) (4b).
) to (7b).

(8) to (II) are magnetic disk devices, and (I2) is D
This is an MA controller (hereinafter referred to as DMAC). (1
3) is a memory as a main storage device, and (14) is a system bus. In addition, F I F O (4a) to (7a
) has a capacity for one track of each magnetic disk device (8) to (11).

Commands from CPU (1) (magnetic disk device read and write commands, transfer address, data amount, etc.)
is stored in the dual port RAM (2), and its commands and status (such as magnetic disk devices and
MAC status), etc. are exchanged. Sub C
The P U (3) allocates commands from the CPU (1) to the respective magnetic disk controllers (4) to (7) to manage their information, and also controls the DMAC (12).

F I F O (4) of magnetic disk controller (4)
a) is connected to DO~7 bits of the system bus (14), and FIFO of the magnetic disk controller 5).
(5a) is connected to bits D8 to D15 of the system bus (14), and is connected to the FIFO of the magnetic disk controller (6).
The circuit (6a) is connected to bits D16 to D23 of the system bus (14) and is connected to bits F of the magnetic disk controller (7).
IFO (7a) is 024-31 of system bus (14)
are connected to the respective bits, and the F I F O (4
It is connected to all bits of the system bus (14) from a) to (7a).

In addition, I of the magnetic disk controllers (4) to (7)
D C (4b) to (7b) are each relatively slow,
Each of them is connected to a small capacity magnetic disk device (8) to (11).

FIG. 2 is a flowchart showing the operation of the above magnetic disk control device, and the operation will be explained below with reference to this flowchart.

Commands from CPU (1) are sent to dual port RA
Since − time is stored in M (2), the sub CPU U (
3) checks whether there is a command from the CPU (1) based on the memory contents of the dual port RAM (2) (Sl). Below is the command (S
2), the case where it is a format command, read command, or write command will be explained respectively.

(1) For formatting instructions; Sub CPU (3) is for each HDC (4b) to (7b)
A command is output to (S3). Each HDC (4
b) to (7b) are each magnetic disk device (8) to (11)
Execute the format command for all H
When D C (4b) to (7b) finish executing the format command, the sub CPU (3) converts the dual port RAM
(3) Set the status to CPU (12)
is notified that the execution of the format command has finished (S
5), return to the first step (Sl).

(2) In case of read command; Sub CPU (3) is dual port RAM (2
), the logical address, data amount, and save address are read from (S6). Then, the sub CPU (3) converts the logical address and data amount for each magnetic disk controller (4) to (7) (S7). Next, the sub CPU (3) executes each FIFO (4a) to (
Set the disc read mode in 7a) and S8), each H
Output commands to DC (4b) to (7b) (S9
).

Each HD C (4b) to (7b) is a magnetic disk device (8
) to (11), read the data, send it to the corresponding FIFOs (4a) to (7a), and save the data in FIFOs (4a) to (7a). Then, the HD C (4
b) to (7b) read the data and perform F I F O (
4a) to (7a) (SIO), at this time,
Data of Do~7 bits is saved in FIFO (4a), and similarly, data of D8~15 is saved in FIFO (5a).
Bit data, F I F O (Ba> is Dl[i
~23 bits of data, and FIFO (7a) has D
24 to 31 bits of data are each saved.

The sub CPU (3) activates the DMAC (12) to start DMA, and performs F I F O (4a) to (
Transfer the data saved in 7a) onto the system bus (14) and write it to the memory (13) <811)
, and the above data transfer continues until the data transfer for one sector by the DMAC (12) is completed (91
2).

Then, the data of all FIFOs (4a) to (7a) are transferred and become empty, and all the HDCs (4a) are empty.
Data transfer is performed by repeating the arithmetic operations from step (SIO) until the read commands for b) to (7b) are completed (813).

When the data transfer is completed as described above, the sub CP
U (3) sets the status in the dual port RAM (2) and notifies the CPU (12) that the execution of the read instruction has ended (S14).

(3) In case of write command; Sub CPU (3) is dual port RAM (2
) to read the logical address, data amount, and save address (S15).Next, the sub CPU (3) sets the write mode to each FlFO (4a) to (7a) (316), and the DMAC ( 12) i,: DM for
A is started (S17).

Next, the sub CPU (3) converts the logical address and data amount for each magnetic disk controller (4) to (7) (818). D for one sector worth of data in each divided bit area on the system bus (14)
When MA is performed and DMA for one sector is performed (S19), a command is output to each HDC (4b) to (7b) (S20).

F I F O (4a) to (7a) have memory (13
) is transferred via the system bus (13), the data is saved, and the data is transferred to the F I F O (4a
) to (7a) are transferred until the data is full (S21).

At this time, data of Do to 7 bits is saved in FIFO (4a), data of D8 to 15 bits is saved in FIFO (5a), and data of D16 to 23 is saved in FIFO (6a). bit data, and FIFO (7a
), the data of bits D24 to D31 are saved respectively.

Next, each HDC (4b) to (7b) accesses the magnetic disk device (8) to (11) to
O(4a) to (7a) Write data. and,
When all HDCs (4b) to (7b) have completed their write operations (S22), the sub CPU (3) then sets the status in the dual port RAM (2) and sends a message to the CPU (12). It is notified that the execution of the read command has ended (S23).

[Effects of the Invention] As described above, according to the present invention, a system bus is divided into a plurality of parts, and magnetic disk control circuits and magnetic disk devices are provided according to the number of divisions, and serial transfer is apparently changed to parallel transfer. Therefore, the transfer speed increases according to the number of divisions, and the storage capacity also increases according to the number of divisions. For this reason, high-speed transfer is possible even when using a general-purpose magnetic disk device, and the cost per bit can therefore be reduced.

Furthermore, since the data processing mechanism for each divided bit area is provided with a data holding circuit for one track, it is possible to absorb rotational deviations of each magnetic disk device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a magnetic disk control device according to an embodiment of the present invention, and FIG. 2 is a flowchart showing the operation of the device shown in FIG. In the figure, (1) is the CPU, (2) is the dual port RAM, (3) is the sub CPU, (4) to (7) are the HD controllers, (8) to (11) are the magnetic disk devices, (
12) is pMAe, (13) is memory, and (14) is a system bus. Agent Patent Attorney Muneharu Sasaki

Claims (1)

[Scope of Claims] A plurality of data holding means each having a storage capacity of at least one track of a magnetic disk device, the bits of which are divided and connected to the system bus, respectively; a plurality of magnetic disk control circuits for exchanging data between the plurality of data holding means and the plurality of magnetic disk devices; A magnetic disk control characterized by having a DMA controller that sends and receives data to and from a holding means, a plurality of data holding means, a plurality of magnetic disk control circuits, and a control means that controls the operation timing of the DMA controller. Device.