JPH02144915A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent upper and lower passivation films from being separated from each other by stopping part of the upper passivation film located above the lower passivation film on the side of a substrate at a portion in an opening section of the lower passivation film, said opening section being made narrower at an inlet thereof. CONSTITUTION:A mask is formed on a second lower passivation film 7b in lower passivation films 7a, 7b located on the side of a substrate 1, and thereafter etched to form an opening section 9. Thereupon, the first lower passivation film 7a comprising a PSG film is more rapidly corroded by etching compared with the second lower passivation film 7b comprising an NSG film, so that the opening section 9 has its size at an inlet side narrower that that at a deep side. After formation of the opening section 9, varnish yielded by dissolving polyimide in a solvent is applied as an upper passivation film 8. Thereupon, part of the varnish enters the opening section 9. Therefore, part of the upper passivation film 8 is captured and stopped by the opening section 9 of the lower passivation films 7a, 7b.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices such as diodes, transistors, or thyristors.

[Conventional technology]

In semiconductor devices, passivation is a technology to stabilize the characteristics of semiconductor elements formed on semiconductor substrates, that is, to improve the long-term reliability of semiconductor devices by preventing them from being influenced by the outside world. . The specific functions of this passivation are to prevent moisture from entering, which has a negative effect on the metal electrodes of the device, and to prevent impurity ions from entering. The surface of the semiconductor substrate on which the semiconductor element is provided is covered with a passivation film.

FIG. 3(a) shows a partial cross section of an example of a conventional semiconductor device using a passivation film.

Although not shown, this is a vertical FET provided with a source terminal (electrode) on the front surface and a drain terminal (electrode) on the back surface. This semiconductor device has a substrate 11
Silicon is used as the material, and a guard ring region (P+ region) 12 for increasing the withstand voltage is formed on the front side of the silicon so as to surround the FET function region. A channel stopper 15 is also formed. For this channel stopper 15, EQR (
Equi Potential Ring: Equi Poten-
tial Ring) electrode 16 is connected to the field oxide film 1.
The contact is made through a through hole 14 made in 3.

The surface of the substrate 11 is covered with a two-layer passivation film 17.1.
A lower passivation film 17 located on the substrate side (lower side) directly covers the field oxide film 13 and the EQR electrode 16. This lower passivation film 17 is formed by CVD (vapor phase growth).
This is an oxide film formed by a cal vapor deposition method, and serves to prevent impurities such as Na ions from entering. The upper passivation film 18 located above it is laminated directly on the lower passivation film 17, but the lower passivation film is made by melting moisture-resistant polyimide in a solvent to form a varnish. It is formed by coating and drying on the semiconductor device 17 and prevents moisture from entering the semiconductor device.

A single layer passivation film has its own strengths and weaknesses, and cannot ensure the long-term reliability of a semiconductor device.Usually, two or more layers are used to prevent impurity ions and moisture. We are trying to prevent the intrusion of

[Problem to be solved by the invention]

The passivation film having the above structure has a problem in that the excellent moisture resistance of polyimide cannot be fully utilized. In other words, as shown in the figure, since the lower passivation film 17 and the upper passivation film 18 are only bonded together by the adhesiveness of the polyimide that constitutes the upper passivation film 18, the upper passivation film 18
However, due to the internal stress of the polyimide, it peels off from the lower passivation film 17 over time, and as shown in FIG. 3(b),
This is because a gap 20 is created between the two, moisture enters through this gap 20, and the excellent moisture resistance of polyimide is not fully exhibited.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a semiconductor device including a multi-layered passivation film in which peeling between upper and lower passivation films does not occur.

[Means to solve the problem]

In order to solve the above problems, a semiconductor device according to the present invention has a semiconductor device in which a substrate surface on which a semiconductor element is provided is covered with a plurality of layers of passivation films, and a lower passivation film on the substrate side has a dimension on an inlet side. An opening is provided which is narrower than the dimension on the back side, and a part of the upper passivation film located on the lower passivation film enters the opening, whereby the upper passivation film is locked to the lower passivation film. That's what I do.

[For production]

A part of the upper passivation film located on the lower passivation film on the substrate side enters an opening with a narrow entrance of the lower passivation film, so that the upper passivation film is locked to the lower passivation film. Therefore, the upper and lower passivation films are firmly bonded to each other.

〔Example〕

Embodiments of the semiconductor device of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1(a) shows an embodiment of the semiconductor device equipped with a passivation film according to the present invention. A partial cross section of a shrunken FET chip is shown. Since the source and drain regions of the FET and their electrodes are provided in the middle of the substrate 1, illustration thereof is omitted here.

In this FET, an N-silicon single crystal substrate is used as the substrate 1. In addition to the guard ring region (P'' region) 2 for increasing withstand voltage, the field oxide film 3, and the channel stopper layer (N'' region) 5, the substrate 1 is provided with AI! It is equipped with an EQR electrode 6 made of a vapor deposited film. Field oxide film 3 is formed by thermally oxidizing substrate 1 . The EQR electrode 6 is provided to prevent the withstand voltage from decreasing due to the depletion layer extending to the end of the chip.

In this FET, a passivation film 7a with a 3N structure,
7b and 8 cover the substrate surface. The lower passivation films 7a and 7b located on the substrate side are both formed by the CVD method, and the first lower passivation film 7a is P
SG (phosphorus-doped silicon oxide film: Phospho
The second lower passivation film 7b is an N5C (non-doped silicon oxide film).
It is a glass film. The upper passivation film 8 located above these is made of a polyimide film formed by applying polyimide varnish.

Unlike conventional semiconductor devices, in this semiconductor device, an opening 9 with a narrow entrance is formed in both the lower passivation films 7a and 7b, and a portion of the upper passivation film 8 enters into this opening. I'm here.

Specifically speaking, when etching is performed after forming a mask on the surface of the second lower passivation film 7b, the portions of the rain passivation films 7a and 7b that are not covered by the mask are corroded, resulting in openings. At this time, among the rain passivation films 7a and 7b, the first lower passivation film 7a made of the PSG film is compared with the second lower passivation film 7b made of the NSC film. In this case, since the rate of corrosion due to etching is high, the dimension on the entrance side of the opening 9 becomes narrower than the dimension on the back side, as shown in FIG. 1 fa). In other words, the cross-sectional shape of the opening 9 becomes inversely tapered. Note that the lower end of the opening 9 is the field oxide film 3.
It has reached this point.

After the openings 9 are formed, when a varnish made by melting polyimide in a solvent is applied as the upper passivation film 8 as in the prior art, a portion of the polyimide varnish enters the inside of the openings 9 because the polyimide varnish is liquid. Therefore, Fig. 1(b)
As shown in the enlarged view, a part of the solidified (bost-cured) upper passivation film 8 is part of the lower passivation film 7a.
, 7b, and the upper passivation film 8 is locked to the lower passivation films 7a, 7b. Therefore, peeling of the upper badging film 8 due to internal stress of the polyimide film is eliminated, and the long-term reliability of the semiconductor device is improved.

The material for the upper passivation film 8 is not particularly limited, but in addition to the above-mentioned polyimide, for example, silicon nitride film or liquid spin code material (SOG) for forming 5ift film; spin-on glass; It may also be a SiOg film obtained by spin-coding and drying Sing)). An example of SOG is 0CD (0hka coat diffusion source: 0hka coat diffusio) on the Tokyo Ohka Kogyo side layer.
n-5ourse). This OCD is obtained by dissolving a silicon compound [Ryu5i(OH)4-yu, silanol] and additives in an organic solvent. In short, any material is sufficient as long as it can enter the opening 9 during formation and solidify.

As shown in FIG.
If it is provided in a groove shape along the entire outer periphery of the semiconductor device so as to surround the outside of the R electrode 6 (not shown), the effect of preventing moisture from entering will be very high. However, opening 9
The arrangement and shape of these are not limited to this, and may be provided intermittently along the periphery. Also, it may not be provided around the surrounding area.

The semiconductor device according to the present invention is not limited to the above embodiments. For example, the method for forming the opening 9 is not limited to the method of etching two materials having different etching rates at the same time, but may be other methods. The cross-sectional shape of the opening 9 is not limited to an inversely tapered shape, and it is sufficient that the opening has a narrower dimension on the inlet side than on the back side. The lower end of opening 9 does not necessarily have to reach field oxide film 5.

The lower passivation film does not have to be two layers, but can be one layer or three layers.
There may be more than one layer. The upper passivation film 8 is not the final passivation film, and another passivation film may be formed thereon.

〔Effect of the invention〕

The semiconductor device according to the present invention prevents the upper and lower passivation films from peeling off from each other due to the locking action of the opening provided in the lower passivation film, and therefore has a high effect of preventing the intrusion of moisture, etc., and has excellent long-term reliability. has.

[Brief explanation of the drawing]

FIG. 1(a) is a cross-sectional view of a part of an embodiment of the semiconductor device according to the present invention, FIG. 1 (bl is an enlarged cross-sectional view of the vicinity of the opening in this semiconductor device, and FIG. FIG. 3 is a plan view showing the opening provided in the
a) is a cross-sectional view of a part of a conventional semiconductor device;
FIG. fbl is a cross-sectional view illustrating peeling of passivation in a conventional semiconductor device. 1... Board 7a, 7b... Lower passivation 8
... Upper passivation film 9 ... Opening agent
Patent Attorney Takehiko Matsumoto 1st 3rd Edition ``4th Tune City Book'' (Subject of self-amendment January 26, 1999 Contents of drawing amendments In the attached drawings, Figure 1 was corrected as shown in the attached sheet. 1988) Patent Application No. 299097. Relationship with the case of person amending the name of the invention semiconductor device

Claims (1)

[Claims] 1. In a semiconductor device in which the surface of a substrate on which a semiconductor element is provided is covered with multiple layers of passivation films, an opening is provided in the lower passivation film on the substrate side, the dimension on the entrance side being narrower than the dimension on the back side, A semiconductor device characterized in that the upper passivation film is locked to the lower passivation film by entering a portion of the upper passivation film located above the lower passivation film into the opening.