JPH0213859A - Abnormality detection circuit of three-phase power supply voltage - Google Patents

Abstract

PURPOSE:To detect abnormality such as the voltage drop and phase variation of three-phase power supply voltage by comparing levels at every phases of three-phase power supply voltage to output the first - third pulses corresponding to respective phases in parallel and comparing the same with various timing pulses. CONSTITUTION:When the power supply voltage of at least one phase of three- phase power supply voltage is lower to the single reference voltage or less in a level comparing circuit 5, at least either one of the first - third pulses is not generated. Therefore, the first and second timing pulses are not generated normally or at least either one of the second and third pulses becomes absent or a pulse extinction signal is generated. Therefore, the logical values of two output signals from a latch circuit 7 are different from those t a normal time and a signal of the second logical value different from that at a normal time is taken out of a logical circuit 8 as an abnormality detection signal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a three-phase fin voltage abnormality detection circuit, and particularly relates to a three-phase fin voltage abnormality detection circuit for detecting abnormalities such as voltage drops and phase fluctuations in the three-phase power supply voltage. This invention relates to an abnormality detection circuit.

Three-phase power supply voltage is often used as the power supply voltage for inductive loads such as motors, and if there is a voltage drop or a phase error, it becomes impossible to ensure the specified performance of the motor. For this reason,
When a drop in three-phase power supply voltage or phase fluctuation occurs,
It is important to detect this as an abnormality and output a warning.

[Conventional technology]

Conventional three-phase power supply voltage abnormality detection circuit detects three-phase power [voltage φ
The DC voltages obtained by half-wave rectifying A, φB, and φC and then adding them are compared in level with a first reference voltage and a first comparator, and the first comparator outputs different logics between normal and abnormal times. The value detection signal was extracted. According to this conventional circuit, when the power supply voltage of even one of the three phases becomes excessive, the output of the first comparator differs from the normal state.

Further, one phase φB of the three-phase power supply voltages φA to φC is phase-shifted, for example, by 120'' to make it in phase with a predetermined one phase φA, and then added, and the rectified DC voltage is transferred to a second voltage by a second comparator. A detection signal with a different logical value is extracted depending on whether it is normal or abnormal by comparing the level with the reference voltage of In other words, when a phase fluctuation occurs in the interphase voltage, the rectified DC voltage becomes lower than the second reference voltage, so that an abnormality in the phase fluctuation can be detected from the output signal level of the second comparator.

Furthermore, the conventional abnormality detection circuit has a three-phase power supply voltage φA to φ
C is first added, then the added signal is rectified, and then the third
Some had a configuration in which the level was compared with a third reference voltage using a comparator. According to this conventional abnormality detection circuit, when the three-phase power supply voltage is normal, the addition signal becomes a voltage near zero volts, but when the amplitude of the voltage gm voltage of each phase becomes unbalanced, Since the amplitude of the addition signal increases and its rectified voltage increases, it is possible to detect an abnormality in the imbalance of the amplitudes of the three-phase power supply voltages based on the output signal level of the third comparator.

[l1ffl to be solved by the invention] However, in the above conventional abnormality detection circuit, the three-phase power supply voltage φA to φC
If only the amplitude of
Even when A and φC were in opposite phase, no abnormality could be detected.

That is, the conventional abnormality detection circuit could only detect an abnormality in limited abnormality modes, such as a 5mlt pressure drop in one or two phases of the three-phase power supply voltage, or a phase fluctuation that does not reverse the phase fluctuation.

Therefore, in order to perform abnormality detection for all abnormal modes, it has conventionally been necessary to use a plurality of abnormality detection circuits.

The present invention has been made in view of the above points, and is a three-phase system that can accurately detect abnormalities in both voltage fluctuations and phase fluctuations.
An object of the present invention is to provide an abnormality detection circuit for Il source voltage.

(Means for Solving the Problems) In order to achieve the above object, the present invention has a configuration as shown in the principle block diagram shown in FIG. In the figure, reference numeral 5 denotes a level comparison circuit which compares the level of each phase of the three-phase Ti power supply voltage with a single reference voltage separately and outputs first to third pulses corresponding to each phase in parallel.

A timing pulse generation circuit 6 generates first and second timing pulses and a pulse extinction signal, respectively, based on the first pulse. The first and second timing pulses are generated at such timing that their leading edges are located in the pulse width periods of the second and third pulses, respectively, under normal conditions.

A latch circuit 7 latches the second and third pulses at the leading edges of the first and second timing pulses.

A logic circuit 8 performs a logical operation on the two output signals output from the latch circuit 7 and the pulse extinction signal, and outputs an abnormality detection signal having a different logical value depending on whether it is normal or abnormal.

[Effect]

Under normal conditions, each leading edge of the first and second timing pulses is located within the pulse width period of the second and third pulses from the level comparison circuit 5, so the latch circuit 7 outputs the second timing pulse.
The logic level of each pulse width period of the second pulse and the third pulse is respectively taken out.

Further, no pulse extinction signal is output. Therefore, the two output signals from the latch circuit 7 are logically operated by the logic circuit 8, and the abnormality detection signal of the first logical value is always taken out during normal operation.

On the other hand, when the power supply voltage of at least one phase of the three-phase M power supply voltage drops below the single reference voltage in the level comparison circuit rH5, at least one of the first to third pulses is It will no longer occur. Therefore, the first and second timing pulses are not normally generated, at least one of the second and third pulses ceases to exist, or a pulse extinction signal is generated. Therefore, the logic values of the two output signals from the latch circuit 7 are different from those in the normal state, and a signal with a second logic value different from the normal state is taken out from the logic circuit 8 as an abnormality detection signal.

In addition, if a phase fluctuation occurs in the three-phase power supply voltage, the first
and the leading edge of the second timing pulse is the second and third timing pulse.
is no longer located within the pulse width period of . This is the same even in the case of phase fluctuation in which the phase-to-phase connections are in opposite phases. Therefore, even when this phase fluctuation occurs, at least one of the output signals of the latch circuit 7 has a logic value different from the normal state, so that an abnormality detection signal having a second logic value different from the normal state is taken out from the logic circuit 8.

〔Example〕

FIG. 2 shows a circuit diagram of an embodiment of the present invention.

In the figure, the same components as in FIG. 1 are denoted by the same reference numerals, and their explanations will be omitted. In FIG. 2, 10 to 13 are terminals, respectively, and terminals 10, 11 and 12 are Δ-connected.
For example, Ao 115V, 400Hz three-phase NWA'
R pressures φA, φB, and φC are input, and the terminal 13 is set to neutral. Terminal 13 is grounded and terminal 10
．． Input load resistors R+, R2, and R3 are connected between 11 and 11 and 12, respectively.

Further, R4 to RI2 are voltage dividing resistors, respectively, and the first phase power supply voltage (indicated by a in Fig. 3), which is set to a predetermined level by resistor voltage division, is taken out at the connection point of resistors R4゜Rs and Rm. , and the connection point of the resistors Re, Ry, and Rs+, and the connection point of the resistors Rs, Rs, and RI2 are connected to the second and third phase power supply voltages (as shown in Figure 3), which are set to predetermined levels by resistor voltage division. , c) are taken out, respectively.

The level comparison circuit 5 is composed of comparators 14, 15 and 16, and a single reference voltage l117. Compare the levels of each.

The timing pulse generation circuit 6 includes monostable multivibrators (hereinafter referred to as rM, M, and J) 18, 19, 23, and M connected in cascade in three stages.

- Consists of an inverter 20 that inverts the phase of the output signal of M, 18. M, M, 18 are triggered by the leading edge (rising edge in this case) of the input pulse and output a pulse of a predetermined width TW +. M, M, 19 are 1M that are triggered by the trailing edge (falling edge in this case) of the input pulse and output a pulse with a predetermined width TW2.

M, 23 has a time constant set to a predetermined time constant longer than one cycle of the input power supply voltage, and outputs a signal at the "yes" level only when input pulses are input at intervals longer than the predetermined time constant. It is a retrigger pull type.

The latch circuit 7 is a D type flip 70 tube 21 and 22
The logic circuit 8 is composed of a three-person AND circuit 24.

Next, the operation of this embodiment will be explained.

■ During normal operation, each of the non-inverting input terminals of the comparators 14, 15 and 16 receives power supply voltages for each of the three phases, which have the same amplitude but differ in phase by 120°, as shown by a, b, and C in Figure 3. The voltage is input and the level is compared with the reference voltage Ev. This reference voltage Ev is set to a value slightly smaller than the positive peak values of the power supply voltages a, b, and C during normal operation, as shown by the broken line in FIG. Therefore, comparators 14, 15 and 1
As shown by d, e, and f in FIG. 3, first to third pulses having relatively short widths are taken out in parallel at a phase and frequency corresponding to the phase of the input power supply voltage.

The first pulse d is applied to M, M, 18 and is triggered at its rising edge to generate a positive pulse of pulse width TWI, as shown by Q in FIG. The pulse width T W 1 is set so that the falling edge of the positive pulse 9 is located at approximately the middle of the pulse width of the second pulse e.

This pulse q is applied to M, M, 19, and is triggered at the falling edge of the pulse q, as shown by h in FIG.
A negative polarity pulse with a pulse width TW2 is generated and output. The pulse width T W z is adjusted so that the rise of this negative pulse h is located at approximately the middle of the pulse width of the third pulse f.
The above pulse Q, in which the value of
It is applied to the clock input terminal of knob 21. At the same time, the negative pulse h is applied as a second timing pulse to the clock input terminal of the D-type flip 70 tube 22.

The D-type flip 70 tubes 21 and 22 have a pulse f of a second pulse width period 3 applied to each data input terminal, and a pulse e is applied at the rising edge of the pulses i and h.
, f are latched and the obtained signals are outputted from their Q output terminals. Therefore, the "H" level signal obtained by latching the "H" level during the pulse width period of the second pulse e is taken out from the Q output terminal of the O type flip 70 tube 21, as shown by j in FIG. Also, from the Q output terminal of the D-type flip-flop 22, as shown by k in FIG. taken out.

On the other hand, M, M, 23 are retriggerable monostable multivibrators whose time constant is set to a predetermined time constant longer than one cycle of the power supply voltage, and ff1J! [By being triggered by the rising edge of the pulse h which is input at a period equal to the period of the pressure, a signal of "H# level" is always output. 24
is applied to one input terminal of

The signals j and k are supplied to a three-man power AND circuit 24 together with the output signals of M, M, and 23, respectively, where they are ANDed to produce a signal as shown at 2 in FIG.
5. In this way, under normal conditions, a signal that is held at the "H" level is output from the AND circuit 24 to the output terminal 25 after a period slightly shorter than one cycle of the power supply voltage.

(2) In the event of an abnormality, for example, when the power supply voltage drops and its positive peak value becomes less than the reference voltage Ev, the pulse e is not taken out from the comparator 15, and the output signal of the comparator 15 remains at a low level. Therefore, since the output signal of the D-type flip-flop 21 is always at the "high" level, the abnormality detection signal at the "L" level is taken out at the output terminal 25.

Next, a case will be described in which the three-phase power supply voltages a, b, and C decrease simultaneously and their positive peak values become less than the reference voltage Ev. In this case, comparator 14.
Since the respective output signals of 15 and 16 are all at "L" level, M, M, 18 and 19 are not triggered and the pulses i,
h does not occur.

Therefore, since M, M, and 23 are also no longer triggered, the output signals of M, M, and 23 will be changed after the predetermined time constant.
It changes from the previous "H" level to "L" level and maintains that state until the next trigger.

Therefore, the output signal of the AND circuit 24 is M.

Due to the “L” level pulse extinction signal from M, 23,
The D type flip 70 attains the "L" level regardless of the logic value of the Q output signals of the knobs 21 and 22, and outputs the "L" level abnormality detection signal to the output terminal 25.

Note that even if only the -phase flf & voltage a decreases, the output signals of M, M, and 23 will be at the "L" level in the same way as above, so the abnormality detection signal of "L level" will be output to the output terminal 25. I can do it.

Next, a case will be described in which the -phase electric m voltage, for example, the power supply voltage a, becomes an excessive value. At this time, the pulse d
Since the rising edge of pulse q comes much earlier than that shown in Fig. 3, the falling edge of pulse q is positioned outside the pulse width period of pulse e, and the rising edge of pulse h is positioned outside the pulse width period of pulse f. come to a certain position.

Therefore, at this time, the D type flip-flops 21 and 2
Since each Q output signal of 2 is at "L" level, output terminal 2
5, an abnormality detection signal of "HI" level is output.

The above is a description of the case where the voltage fluctuation is abnormal. Next, the case where the phase fluctuation is abnormal will be described. For example, what about the power supply voltage? ! When the phase shifts by 120° to the position of source voltage G, pulses d and f are generated with the same phase as in normal times, but pulse e
occurs in phase with the pulse. Therefore, at the rising edge of pulse i, the output signal of the comparator 15 is “L”.
” level, the output signal of the D type flip 70 knob 21 becomes the “L” level, and an “L” level abnormality detection signal is taken out from the output terminal 25.

Further, even if the phases are reversed, the phases of the output pulses of the comparators 14 to 16 will be different from those shown in FIG. 3 in the same way as described above, and an abnormality detection signal of 'L' level will be obtained.

Note that the present invention is not limited to the above-described embodiments, and for example, a counter that counts the system clock may be used in place of M, M, and M, M, 23.
The inputs M, M, 18 or C may be obtained from the comparator 14, and various other modifications are possible.

〔Effect of the invention〕

As described above, according to the present invention, an abnormality detection signal of a predetermined logical value can be accurately detected in response to abnormalities such as power supply voltage fluctuations, including when the three-phase power supply voltage decreases substantially simultaneously, and phase fluctuations, including phase reversal. In addition, the number of parts per circuit configuration can be simplified compared to conventional circuits, and the rotational performance of the motor can be improved when the rotational direction due to the phase order of a three-phase motor or the rotational speed fluctuates due to voltage drop. It has features such as being suitable for applications such as securing.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a circuit system diagram of an embodiment of the present invention, and Fig. 3 is a block diagram of the principle of the present invention.
It is a time chart for explaining the operation of the figure. In the figure, 5 is a level comparison circuit, 6 is a timing pulse generation circuit, 7 is a latch circuit, 8 is a logic circuit, 14 to 16 are comparators, and 17 is a reference voltage source. Patent Applicant: Fujitsu Ltd. Figure 2: Motion Eclipse Use Im + Yard Fable 3 Men's Job May, 轡, Logic 70/Tsuku Figure 1

Claims (1)

[Claims] A level comparison circuit (5) that compares the level of each phase of a three-phase power supply voltage with a single reference voltage separately and outputs first to third pulses corresponding to each phase in parallel. and the level comparison circuit (
5) Of the first to third pulses extracted from
Based on the first pulse, a first timing pulse whose leading edge is located in the pulse width period of the second pulse under normal conditions, and a second timing pulse whose leading edge is located in the pulse width period of the third pulse. a timing pulse generation circuit (6) that generates a timing pulse and a pulse extinction signal that becomes a predetermined logical value only when the first pulse is not input for a certain period of time; ) latching the second pulse at the leading edge of the first timing pulse from ) and latching the third pulse at the leading edge of the second timing pulse; A logic circuit (8) that performs a logical operation on the two output signals of the circuit (7) and the pulse extinction signal and outputs an abnormality detection signal having a different logical value depending on whether it is normal or abnormal. Phase power supply voltage abnormality detection circuit.