JPH02122724A - Level conversion circuit - Google Patents

Abstract

PURPOSE:To prevent current consumption in a fast operation from being increased by providing a PMOS transistor whose gate electrode is connected to an input terminal, whose source electrode to the cathode side terminal of a diode, and whose drain electrode to an output terminal. CONSTITUTION:The gate electrode of the PMOS transistor 4 is connected to the input terminal 1, and the source electrode to the cathode side terminal of the diode 3, and the drain electrode to the output terminal 5. Meanwhile, the gate electrode of an NMOS transistor 6 is connected to the terminal 1, and the source electrode to the anode side terminal of the diode 7, and the drain electrode to the terminal 5. In such a constitution, assuming the potential of a negative power source 8 as 0 and that of a positive power source as VDD, the voltage of the terminal 5 goes to a value less than the VDD by the voltage drop of the diode 3 when the voltage of the terminal 1 is VDD. Also, when the voltage of the terminal 1 is 0, the voltage of the terminal 1 goes to the value larger than 0 by the voltage drop of the diode 3, which reduces the amplitude of the terminal 5, Therefore, it is possible to prevent the current consumption from being increased even in the fast operation.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a level conversion circuit realized with a semiconductor integrated circuit, and particularly to a level conversion circuit for reducing amplitude, for example, for converting from a CMOS level to an ECL level. This invention relates to a level conversion circuit.

[Conventional technology]

An example of a level conversion circuit in a conventional semiconductor integrated circuit will be described with reference to the drawings.

FIG. 2 is a circuit diagram showing an example of a conventional level conversion circuit.

As shown in FIG. 2, in the conventional level conversion circuit, an input terminal 11 is connected to a terminal a of a resistor element (hereinafter referred to as R) 12, a terminal of R12 is connected to a terminal d of R14, an output terminal 15, The terminal C of R14 was connected to the positive power supply 13, and the terminal f of R16 was connected to the negative power supply 17.

The conventional level conversion circuit sets the negative power supply potential to O1, the positive power supply potential to VDD, the resistance value of R12 to R1, and the resistance value of R14 to R.
2. If the resistance value of R14 is R3, the input terminal voltage is VI, and the output terminal voltage is VO, then VO= (R2XR3XV, I +RI XR3XVD
D)/ (R1xR2+R2xR3+R3xR1), and when VI is equal to VDD, V○= (R2XR
3+RI xR3)xvDD/(R1xR2+R2xR
3+R3xR1) When VI is O, V○=R1xR3xVDD/ (R1xR2+R2xR
3+R3xR1), making it possible to reduce the amplitude of the output terminal.

[Problem to be solved by the invention]

In the conventional level conversion circuit described above, in order to operate at high speed, the resistance value of the resistor element must be reduced, so a large current always flows through the resistor element, resulting in high power consumption and lack of drive capability. Therefore, when a capacitive load is attached to the output terminal, the operation becomes slow.

[Means to solve the problem]

The level conversion circuit of the present invention includes a first series circuit of a plurality of diodes whose anode side terminal is connected to a positive power supply, a second series circuit of a plurality of diodes whose cathode side terminal is connected to a negative power supply, and a gate electrode. Connect the source electrode to the first terminal.
a P-channel type MO3) transistor whose drain electrode is connected to the cathode side terminal of a series circuit of a plurality of diodes and the output terminal thereof; a gate electrode is the input terminal and a source electrode is the anode side terminal of the second series circuit of a plurality of diodes; an N-channel type M having a drain electrode connected to the output terminal;
It has an OS transistor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In FIG. 1, the level conversion circuit of this embodiment includes a diode 3 that connects an anode terminal 11 to a positive power supply 2, a diode 7 that connects a cathode terminal to a negative power supply 8, and a gate electrode that connects a source to an input terminal 11. Connect the electrode to the cathode terminal of diode 3 and the drain electrode to output terminal 5.
A channel type MOS) transistor (hereinafter referred to as PMO3) 4, whose gate electrode is the input terminal 1, whose source electrode is the anode side terminal of the diode 7, and whose drain electrode is the output terminal 5.
N-channel MOS transistor (hereinafter referred to as N0) connected to
(denoted as M5) 7.

Next, the operation of this embodiment will be explained.

Now, if the potential of the negative power supply 8 is 0 and the potential of the positive power supply 2 is VDD, when the voltage of the input terminal 1 is VDD, the voltage of the output terminal 5 will be a value smaller than VDD by the voltage drop of the diode 3, When the voltage at the input terminal 1 is O, the voltage at the output terminal 5 is larger than O by the voltage drop across the diode 3, and the amplitude at the output terminal 5 can be reduced.

On the other hand, instead of diode 3, connect diode 3 in series with 2
When you insert a connected one, the voltage of output terminal 5 becomes VD.
From D, the voltage drop of diode 3 is two times smaller than the value,
In this way, the amplitude of the output terminal 5 can be changed by changing the number of diodes 3.

Further, in this embodiment, when the PMO 34 is in the on state, N
When the MO 36 is in the off state and the NMOS 6 is in the on state, the PMOS 4 is in the off state, so no steady current flows.

On the other hand, in this embodiment, since it is driven by a MOS transistor, high-speed operation is possible even if a capacitive load is attached to the output terminal 5.

〔Effect of the invention〕

As explained above, in the present invention, the input terminal is connected to the gate electrode of a P-channel type MOS transistor and the gate electrode of an N-channel type MOS transistor.
The anode side terminal of the first series circuit of multiple diodes is connected to the positive power supply, the cathode side terminal is connected to the source electrode of the P channel type MO3) transistor, and the P channel type MoS transistor is connected to the gate electrode of the transistor. The drain electrode is connected to the train electrode of the N-channel MOS transistor and the output terminal, the source electrode of the N-channel MOS transistor is connected to the anode side terminal of a series circuit of a second plurality of diodes, and the second plurality of diodes are connected to each other. By connecting the cathode side terminal of the series circuit to the negative power supply, the amplitude of the output terminal can be reduced, so power consumption does not increase even during high-speed operation, and the capacitive load is also reduced. It has the effect of being able to be driven.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional level conversion circuit. 1...Input terminal, 2...Positive power supply, 3...Diode, 4...P channel type MOS transistor (PM○
S>, 5... Output terminal, 6... N-channel type MOS
Transistor (NMO3), 7... Diode, 8...
... Negative power supply, 11 ... Input terminal, 12 ... Resistance element (R), 13 ... Positive power supply, 14 ... Resistance element (R)
, 15... Output terminal, 16... Resistance element (R), 1
7... Negative power supply.

Claims (1)

[Claims] a first series circuit of a plurality of diodes whose anode side terminal is connected to a positive power supply; a second series circuit of a plurality of diodes whose cathode side terminal is connected to a negative power supply; a P-channel MOS transistor whose drain electrode is connected to the cathode side terminal of a series circuit of a plurality of diodes and an output terminal thereof, whose gate electrode is connected to the input terminal and whose source electrode is connected to the anode side terminal of the second series circuit of a plurality of diodes. 1. A level conversion circuit comprising: an N-channel MOS transistor whose drain electrode is connected to the output terminal.