JPH02122576A - Photoelectric conversion device and manufacture thereof - Google Patents
Photoelectric conversion device and manufacture thereofInfo
- Publication number
- JPH02122576A JPH02122576A JP63276979A JP27697988A JPH02122576A JP H02122576 A JPH02122576 A JP H02122576A JP 63276979 A JP63276979 A JP 63276979A JP 27697988 A JP27697988 A JP 27697988A JP H02122576 A JPH02122576 A JP H02122576A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- amorphous silicon
- silicon semiconductor
- layer
- photoelectric conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 title claims description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 77
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 70
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 230000003287 optical effect Effects 0.000 claims abstract description 20
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 10
- 239000001257 hydrogen Substances 0.000 claims abstract description 10
- 230000000737 periodic effect Effects 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 19
- 230000035945 sensitivity Effects 0.000 abstract description 13
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 230000007423 decrease Effects 0.000 abstract description 5
- 241001481828 Glyptocephalus cynoglossus Species 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 109
- 239000007789 gas Substances 0.000 description 11
- 238000000151 deposition Methods 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 7
- 230000003595 spectral effect Effects 0.000 description 7
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 6
- 230000006866 deterioration Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000001782 photodegradation Methods 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 229910000077 silane Inorganic materials 0.000 description 6
- 239000011651 chromium Substances 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 238000010894 electron beam technology Methods 0.000 description 4
- 229910001220 stainless steel Inorganic materials 0.000 description 4
- 239000010935 stainless steel Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000012495 reaction gas Substances 0.000 description 3
- 238000005979 thermal decomposition reaction Methods 0.000 description 3
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 3
- 229910001887 tin oxide Inorganic materials 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000003795 desorption Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000003779 heat-resistant material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 125000004437 phosphorous atom Chemical group 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- MZFIXCCGFYSQSS-UHFFFAOYSA-N silver titanium Chemical compound [Ti].[Ag] MZFIXCCGFYSQSS-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 241000605059 Bacteroidetes Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- -1 Pt) Chemical class 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Light Receiving Elements (AREA)
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業の利用分野〕
本発明は光学的測定装置、光スイツチング素子などに用
いられる光センサ−、太陽電池などの光電変換装置及び
その製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to optical measuring devices, optical sensors used in optical switching elements, etc., photoelectric conversion devices such as solar cells, and methods of manufacturing the same.
現在、P−1−N接合した非晶質シリコン半導体層は、
太陽電池、光センサーなどの光電変換装置に幅広く用い
られている。Currently, the amorphous silicon semiconductor layer with P-1-N junction is
It is widely used in photoelectric conversion devices such as solar cells and optical sensors.
このP−I−N接合した非晶質シリコン半導体層は、光
キャリア(正孔や電子)生成層(一般に1層)の両側に
P層とNJ’5とを配置したものであり、光照射により
発生したキャリアをPF5及びN層の外面に形成した電
極で収集して光起電力を得たり、非晶質半導体層の導電
率の変化を得ていた。This P-I-N junction amorphous silicon semiconductor layer has a P layer and an NJ'5 arranged on both sides of a photocarrier (hole or electron) generation layer (generally one layer), and when exposed to light irradiation. The carriers generated are collected by electrodes formed on the outer surfaces of the PF5 and N layers to obtain photovoltaic force or to obtain changes in the conductivity of the amorphous semiconductor layer.
このような、非晶質半導体層を有する光電変換装置は、
特に1層の非晶質半導体層でスティブラー・ロンスキ−
効果と言われる光劣化現象が発生し、初期特性が1/1
0程度に低下することが知られている。これは太陽電池
、光センサーなどの光電変換装置にとって致命的な欠点
であり、光電変換装置の使用範囲を大きく狭めるもので
あった。A photoelectric conversion device having such an amorphous semiconductor layer is
In particular, in one amorphous semiconductor layer, Stibler-Wronski
A photodegradation phenomenon called the effect occurs, and the initial characteristics are reduced to 1/1.
It is known that the value decreases to about 0. This is a fatal drawback for photoelectric conversion devices such as solar cells and optical sensors, and greatly narrows the scope of use of photoelectric conversion devices.
従来の光電変換装置、例えば、アモルファスシリコン太
陽電池素子は第6図に示すように、透明ガラス基板61
上に、熱分解法や電子ビーム法で透明導電膜62を被着
し、さらに、該透明導電膜62上に、プラズマCVD法
でP−I−N接合した非晶質半導体層である非晶質シリ
コン半導体層63を被着し、さらに、該非晶質シリコン
半導体層63上にAI、Ni、Crなどの金属電極74
を被着して構成していた(特開昭52−16690号参
照)。A conventional photoelectric conversion device, for example, an amorphous silicon solar cell element has a transparent glass substrate 61 as shown in FIG.
A transparent conductive film 62 is deposited thereon by a thermal decomposition method or an electron beam method, and an amorphous semiconductor layer, which is an amorphous semiconductor layer, is further formed by P-I-N bonding on the transparent conductive film 62 by a plasma CVD method. A crystalline silicon semiconductor layer 63 is deposited, and a metal electrode 74 of AI, Ni, Cr, etc. is further deposited on the amorphous silicon semiconductor layer 63.
(Refer to Japanese Patent Laid-Open No. 16690/1983).
従来からP−I−N接合した非晶質シリコン半導体層6
3の膜質の特性上、プラズマCVD法の成膜基板温度は
200〜250℃に設定され、非晶質シリコン半導体層
63が被着されてきた。これは、また透明ガラス基板6
1上に透明導電膜62として、ITO(酸化インジウム
・錫)や酸化錫等を使用するが、透明度が良好で、且つ
低抵抗の膜をえるために、透明導電膜62のプラズマ中
での耐熱温度(最高で300℃前後)に鑑み、設定され
た基板温度であった。Amorphous silicon semiconductor layer 6 with conventional P-I-N junction
Due to the characteristics of the film quality of No. 3, the temperature of the film-forming substrate in the plasma CVD method has been set at 200 to 250° C., and the amorphous silicon semiconductor layer 63 has been deposited. This is also the transparent glass substrate 6
ITO (indium tin oxide), tin oxide, etc. are used as the transparent conductive film 62 on the top of the transparent conductive film 62. In order to obtain a film with good transparency and low resistance, the transparent conductive film 62 must be heat resistant in plasma. The substrate temperature was set considering the temperature (maximum around 300° C.).
そこで、本発明者らは、鋭意研潜し、P−I−N接合し
た非晶質シリコン半導体層63を有する光電変換装置に
おいて、成膜基板温度を高温に設定し、非晶質シリコン
半導体層63中の水素濃度及び光学的ギャプを所定値に
設定することによって、光劣化現象を改善できることを
知見した。Therefore, the present inventors conducted extensive research, and in a photoelectric conversion device having a P-I-N junction amorphous silicon semiconductor layer 63, the temperature of the film-forming substrate was set to a high temperature, and the amorphous silicon semiconductor layer 63 was It has been found that the photodegradation phenomenon can be improved by setting the hydrogen concentration in 63 and the optical gap to predetermined values.
本発明は上述の知見に基づいて案出されたものであり、
その目的はP−1−N接合した非晶質シリコン半導体層
に発生する光劣化現象を低減し、良質な膜質、長波長側
の感度が向上する光電変換装置及びその製造方法を提供
することにある。The present invention was devised based on the above findings,
The purpose is to reduce the photodegradation phenomenon that occurs in P-1-N junction amorphous silicon semiconductor layers, and to provide a photoelectric conversion device with high film quality and improved sensitivity on the long wavelength side, and a method for manufacturing the same. be.
〔目的を達成するための具体的な手段〕本発明によれば
、上述の目的を達成するため、耐熱性金属の導電股上に
、P−1−N接合した非晶質シリコン半導体層を形成し
た光電変換装置において、前記非晶質シリコン半導体層
が、1. 7ev〜1.5evの光学的ギャップで且つ
非晶質シリコン半導体層中に10at%未満の水素濃度
である光電変換装置を提供するものであり、さらに、耐
熱性金属の導電股上に、P−I−N接合した非晶質シリ
コン半導体層を形成した光電変換装置の製造方法におい
て、前記非晶質シリコン半導体層を成膜基板温度が40
0℃以上で被着するとともに、1層非晶質シリコン半導
体層中に、1層非晶質シリコン半導体層に続いて被着さ
れるP層又はN層を決定する周期率表第■族又は第■族
の元素と同一の元素をガス濃度0.2〜1 、 OPP
mで成膜する光電変換装置の製造方法を提供する。[Specific Means for Achieving the Object] According to the present invention, in order to achieve the above-mentioned object, an amorphous silicon semiconductor layer with P-1-N junction is formed on the conductive crotch of a heat-resistant metal. In the photoelectric conversion device, the amorphous silicon semiconductor layer includes 1. The present invention provides a photoelectric conversion device with an optical gap of 7ev to 1.5ev and a hydrogen concentration of less than 10 at% in an amorphous silicon semiconductor layer, and further includes a P-I - In a method of manufacturing a photoelectric conversion device in which an N-junctioned amorphous silicon semiconductor layer is formed, the amorphous silicon semiconductor layer is formed at a temperature of 40° C.
Group Ⅰ of the periodic table or The same element as the group Ⅰ element is used at a gas concentration of 0.2 to 1, OPP
Provided is a method for manufacturing a photoelectric conversion device in which a film is formed using m.
上述の具体的な手段により、P−1−N接合した非晶質
シリコン半導体層を作製する際に、基板温度を400℃
以上に設定することで、光照射による光劣化で最も特性
に大きく影響するI型非晶質シリコン半導体層の水素濃
度を低下させることができる。これにより、光エネルギ
ーの供与により変化する水素が少なく、光照射を長時間
つづけても、I5非晶質シリコン半導体層が安定的とな
り、劣化での少ない出力特性が得られるものと考えられ
る。また、少なくとも1層非晶質シリコン半導体層を高
温基板で被着することにより、1層非晶質シリコン半導
体層前に被着したP型又はN型層からその層の導電型を
決定する元素力q層非晶質シリコン半導体層に拡散され
てしまい、1層のフェルミレベルが変化してしまう。こ
れを補正するために、1層非晶質シリコン半導体層の成
膜中に拡散される元素、(周期率表第■族又は第■族の
元素)とは逆の導電型を決定する元素(周期率第■族又
は第■族の元素)を1層非晶質シリコン半導体に含有さ
せるものである。By the above-mentioned specific method, when producing an amorphous silicon semiconductor layer with a P-1-N junction, the substrate temperature was set to 400°C.
With the above settings, it is possible to reduce the hydrogen concentration of the I-type amorphous silicon semiconductor layer, which has the greatest effect on the characteristics due to photodeterioration due to light irradiation. As a result, less hydrogen changes due to the provision of light energy, and even if light irradiation is continued for a long time, the I5 amorphous silicon semiconductor layer becomes stable, and it is thought that output characteristics with less deterioration can be obtained. In addition, by depositing at least one amorphous silicon semiconductor layer on a high-temperature substrate, an element that determines the conductivity type of the layer from the P-type or N-type layer deposited before the one-layer amorphous silicon semiconductor layer can be added. The force is diffused into the q-layer amorphous silicon semiconductor layer, and the Fermi level of one layer changes. In order to correct this, elements that determine the conductivity type opposite to the elements diffused during the deposition of the single-layer amorphous silicon semiconductor layer (elements in group Ⅰ or group Ⅰ of the periodic table) ( In this method, a single-layer amorphous silicon semiconductor contains an element of periodicity group Ⅰ or group ②.
以下、本発明の光電変換装置の製造方法を図面に基づい
て詳細に説明する。Hereinafter, the method for manufacturing a photoelectric conversion device of the present invention will be explained in detail based on the drawings.
第1図は本発明の光電変換装置に係る太陽電池の構造を
示す断面構造図である。FIG. 1 is a cross-sectional structural diagram showing the structure of a solar cell according to a photoelectric conversion device of the present invention.
本発明に係る太陽電池は、耐熱性導電膜2を被着した基
板1上に、第1の導電型、第2の導電型、第3の導電型
を接合した、即ちP−I−N接合した非晶質シリコン半
導体層3及び透明電極4が被着され、構成されている。In the solar cell according to the present invention, a first conductivity type, a second conductivity type, and a third conductivity type are bonded on a substrate 1 on which a heat-resistant conductive film 2 is adhered, that is, a P-I-N junction. An amorphous silicon semiconductor layer 3 and a transparent electrode 4 are deposited and configured.
即ち、光入射が基板1の反対の面から照射される、所謂
逆タイプである。That is, it is a so-called reverse type in which light is irradiated from the opposite surface of the substrate 1.
基板1はガラス、セラミック、ステンレスなどの耐熱性
を有する材料などから成り、該基Fj、lの一主面には
耐熱性導電膜2が被着されている。The substrate 1 is made of a heat-resistant material such as glass, ceramic, or stainless steel, and a heat-resistant conductive film 2 is deposited on one main surface of the groups Fj and l.
耐熱性導電膜2はチタン(Ti)、ニッケル(Ni)、
チタン−銀(Ti−Ag)、クロム(Cr)、ステンレ
ス、タングステン(W) 、ill(Ag) 、白金(
Pt)、タンタル(Ta)、コバルト(Co)等の金属
が用いられる。具体的には、基板1の一主面上にマスク
を装着した後、上述の金属膜をスパッタリング法、電子
ビーム法、抵抗加熱法などで被着したり、基板1の一主
面上に上述の金属膜を被着した後、レジスト・エツチン
グ処理したりして形成されている。The heat-resistant conductive film 2 is made of titanium (Ti), nickel (Ni),
Titanium-silver (Ti-Ag), chromium (Cr), stainless steel, tungsten (W), ill (Ag), platinum (
Metals such as Pt), tantalum (Ta), and cobalt (Co) are used. Specifically, after a mask is attached on one main surface of the substrate 1, the above-mentioned metal film is deposited by a sputtering method, an electron beam method, a resistance heating method, etc. It is formed by depositing a metal film and then performing a resist etching process.
非晶質シリコン半導体層3は、第1の導電型、第2の導
電型、第3の導電型を接合、叩ちP−I−N接合が形成
されている。具体的には、非晶質シリコン半導体層3は
シラン、ジシランなどのシリコン化合物ガスと水素など
のキャリアガスとをグロー放電で分解するプラズマCV
D法や光CVD法等で被着され、N層は上述のガスにフ
ォスフインなどのN型ドーピングガスを混入した反応ガ
スで形成され、1層は上述の反応ガスで形成され、P層
は上述のガスにジボランなどのP型ドーピングガスを混
入した反応ガスで形成される。In the amorphous silicon semiconductor layer 3, a first conductivity type, a second conductivity type, and a third conductivity type are joined to form a beaten P-I-N junction. Specifically, the amorphous silicon semiconductor layer 3 is formed using plasma CV in which a silicon compound gas such as silane or disilane and a carrier gas such as hydrogen are decomposed by glow discharge.
The N layer is formed using the above-mentioned gas mixed with an N-type doping gas such as phosphine, the first layer is formed using the above-mentioned reaction gas, and the P layer is formed using the above-mentioned reaction gas. It is formed from a reactive gas containing a P-type doping gas such as diborane.
透明電極4は、非晶質シリコン半導体層3を耐熱性導電
膜2とで挟持するように非晶質シリコン半導体層3上の
所定形状に形成されている。具体的には、透明電極4は
非晶質シリコン半導体層3上にマスクを装着し、熱分解
法や電子ビーム法で被着される。透明導電膜として、I
TO(酸化インジウム・錫)や酸化錫等が使用されてい
る。The transparent electrode 4 is formed in a predetermined shape on the amorphous silicon semiconductor layer 3 so that the amorphous silicon semiconductor layer 3 is sandwiched between the heat-resistant conductive film 2 and the amorphous silicon semiconductor layer 3 . Specifically, the transparent electrode 4 is deposited by a thermal decomposition method or an electron beam method by attaching a mask to the amorphous silicon semiconductor layer 3. As a transparent conductive film, I
TO (indium tin oxide), tin oxide, etc. are used.
そして、透明電極4側より、光照射があると、透明電極
4を介して、非晶質シリコン半導体層3に光が到達し、
非晶質シリコン半導体N3の1層からキャリアが発生す
る。そして1層を挟むP層及びN層との界面の電界によ
り、キャリアがP層及びN層にと収集され、耐熱性導電
膜2と、透明電極4との間より光起電力が導出される。When light is irradiated from the transparent electrode 4 side, the light reaches the amorphous silicon semiconductor layer 3 via the transparent electrode 4,
Carriers are generated from one layer of the amorphous silicon semiconductor N3. Then, due to the electric field at the interface between the P layer and the N layer sandwiching one layer, carriers are collected in the P layer and the N layer, and photovoltaic force is derived from between the heat-resistant conductive film 2 and the transparent electrode 4. .
次に、本発明の特徴部分である非晶質シリコン半導体層
3の成膜について詳述する。Next, the formation of the amorphous silicon semiconductor layer 3, which is a feature of the present invention, will be described in detail.
本発明者らは、非晶質シリコン半導体層3の成膜におけ
る基板温度と光劣化との関係を解明すべく、基板温度を
200℃(線a)、300℃(線b)、400℃(線C
)、450℃(線d)と変化させ、夫々の非晶質シリコ
ン半導体層に、AMl、 100 mW/c111の
光を照射した。In order to elucidate the relationship between the substrate temperature and photodeterioration during the deposition of the amorphous silicon semiconductor layer 3, the present inventors set the substrate temperature at 200°C (line a), 300°C (line b), and 400°C (line b). Line C
) and 450° C. (line d), and each amorphous silicon semiconductor layer was irradiated with light of 100 mW/c111 of AMl.
その結果を第2図に示す。特性図で、横軸は光照射時間
を示し、縦軸は初期特性からの低下率を示した。The results are shown in FIG. In the characteristic diagram, the horizontal axis shows the light irradiation time, and the vertical axis shows the rate of decrease from the initial characteristics.
図から明らかなように、基板温度を200℃(線a)、
300°C(線b)テ成膜した従来ノ非晶質シリコン半
導体層は、初期から光劣化して低下する状態が著しく大
きく、照射時間が105分では、光劣化による低下が9
0χにも達してしまう。As is clear from the figure, the substrate temperature is 200°C (line a),
Conventional amorphous silicon semiconductor layers deposited at 300°C (line b) are subject to significant photodegradation and degradation from the initial stage, and when the irradiation time is 105 minutes, the photodegradation decreases by 9%.
It even reaches 0χ.
これに対して、基板温度を400℃(線c)、450℃
(線d)で成膜した本発明の非晶質シリコン半導体層は
、光劣化による初期特性の低下の割合(グラフでの傾き
)が小さく、照射時間が105分では、初期特性の20
χ未満の劣化に留まる。In contrast, the substrate temperature was set to 400°C (line c) and 450°C.
The amorphous silicon semiconductor layer of the present invention deposited according to line d has a small rate of decline in initial characteristics (slope in the graph) due to photodeterioration, and when the irradiation time is 105 minutes, the initial characteristics are 20% lower than the initial characteristics.
The deterioration remains below χ.
さらに、基板温度を300℃(線b)で成膜した本発明
の非晶質シリコン半導体層と、基板温度を400℃(線
C)で成膜した本発明の非晶質シリコン半導体層との分
光感度を調べてみた。その結果は、第3図に示す。Furthermore, the amorphous silicon semiconductor layer of the present invention was formed at a substrate temperature of 300°C (line b), and the amorphous silicon semiconductor layer of the present invention was formed at a substrate temperature of 400°C (line C). I investigated the spectral sensitivity. The results are shown in FIG.
図から明らかなように、基板温度を300℃(線b’
)で成膜した非晶質シリコン半導体層よりも、基板温度
を400℃(線c’ )で成膜した非晶質シリコン半導
体層のほうが、分光感度が長波長側にシフトしており、
長波長側に感度ピークが存在することが確認できる。こ
の様な非晶質シリコン半導体層3を太陽電池に用いれば
、光劣化による特性の低下を抑えられ、エネルギー吸収
量が多くなる。As is clear from the figure, the substrate temperature was set at 300°C (line b'
), the spectral sensitivity of the amorphous silicon semiconductor layer formed at a substrate temperature of 400°C (line c') is shifted to the longer wavelength side,
It can be confirmed that a sensitivity peak exists on the long wavelength side. If such an amorphous silicon semiconductor layer 3 is used in a solar cell, deterioration of characteristics due to photodeterioration can be suppressed and the amount of energy absorbed can be increased.
上述の基板温度を400℃及び450℃で成膜した非晶
質シリコン半導体N3の物性を調べたところ、先の実駿
が納得できる数値、光学的バンドギャップが1 、7e
V〜1.5eV (吸収係数のタウツブロットで測定)
であった。このときの非晶質シリコン半導体層3中の含
有水素濃度を10atχ〜Oatχ(赤外線吸収、水素
放出量、ラザフォートバックスキャンタリングなどで測
定)であった。When we investigated the physical properties of the amorphous silicon semiconductor N3, which was formed at the above-mentioned substrate temperatures of 400°C and 450°C, we found that the optical band gap was 1.7e, a value that Saneshun could accept.
V~1.5eV (measured by Tautz blot of absorption coefficient)
Met. At this time, the concentration of hydrogen contained in the amorphous silicon semiconductor layer 3 was 10atχ to Oatχ (measured by infrared absorption, amount of hydrogen released, Rutherfort back scanning, etc.).
このような非晶質シリコン半導体層3を太陽電池素子と
して用いて、特性を調べても、その劣化の割合を半減す
ることも確認された。When such an amorphous silicon semiconductor layer 3 is used as a solar cell element and its characteristics are investigated, it has been confirmed that the rate of deterioration can be halved.
尚、上述の実験で使用した非晶質シリコン半導体層3は
、P−1−N接合をしており、各層の成膜で基板温度を
高温に設定したが、光劣化の影響を受けやすい■層成脱
時のみを高温基板(400℃以上)に設定してもよい。Note that the amorphous silicon semiconductor layer 3 used in the above experiment has a P-1-N junction, and although the substrate temperature was set at a high temperature during the deposition of each layer, it is susceptible to photodegradation. A high temperature substrate (400° C. or higher) may be used only during layer formation and desorption.
第1図に示した光電変換装置である太陽電池では、耐熱
性導電股上にN層(リンなど周期率表第■族元素が含有
)非晶質シリコン半導体層が被着されているが、基板温
度を400℃以上で1層非晶質シリコン半導体層3をN
N上に成膜すると、N層中のリン原子などが活性化し、
1層中にまで拡散してしまう。これにより、1層のフェ
ルミレベルが0.6eV程度となる。このためI層成脱
時に1層上に成膜される2層非晶質シリコン半導体層の
P型ドープ剤である周期率表第■族元素を含むドープガ
ス、例えばジボラン(B2H6)を前記シランガスとと
もに反応ガスとして供給し、フェルミレベルを適正値に
補正することが重要である。In the solar cell, which is a photoelectric conversion device shown in Fig. 1, an N layer (containing elements of group Ⅰ of the periodic table such as phosphorus) is deposited on a heat-resistant conductive layer. The one-layer amorphous silicon semiconductor layer 3 is made of N at a temperature of 400°C or higher.
When a film is formed on N, phosphorus atoms etc. in the N layer are activated,
It will diffuse into one layer. As a result, the Fermi level of one layer becomes approximately 0.6 eV. For this reason, a doping gas containing an element from group Ⅰ of the periodic table, such as diborane (B2H6), which is a P-type dopant for the two-layer amorphous silicon semiconductor layer formed on the first layer during the I layer formation and desorption, is used together with the silane gas. It is important to supply it as a reaction gas and correct the Fermi level to an appropriate value.
第4図は、I層成脱時に、シランとともに供給されるジ
ボランの流量と、ジボランによって変化するフェルミエ
ネルギーを示す。FIG. 4 shows the flow rate of diborane supplied together with silane during I layer formation and the Fermi energy that changes depending on diborane.
図から明らかなように、非晶質シリコン半導体層3の1
層として、適したフェルミエネルギーに補正するには、
ジボラン/シランの流量比が0.2〜1.OPPmの範
囲、である。As is clear from the figure, 1 of the amorphous silicon semiconductor layer 3
To correct for the appropriate Fermi energy as a layer,
The diborane/silane flow ratio is 0.2 to 1. The range of OPPm.
以上のように、本発明によれば、該基板を400℃以上
に設定することにより、光劣化による初期特性の低下を
良好に抑えることができ、分光感度が長波長側に延びる
ことができ、さらに、適性なフェルミレベルに容易に制
御可能なことが確認できた。As described above, according to the present invention, by setting the substrate at a temperature of 400° C. or higher, it is possible to satisfactorily suppress the deterioration of initial characteristics due to photodeterioration, and the spectral sensitivity can be extended to the long wavelength side. Furthermore, it was confirmed that it could be easily controlled to an appropriate Fermi level.
第5図は、本発明の光電変換装置の製造方法に係る第2
の実施例である光センサーの構造を示す断面構造図であ
る。即ち、分光感度が長波長側にシフトすることにより
、赤色感度に優れた光センサーが達成できる。FIG. 5 shows the second method of manufacturing a photoelectric conversion device of the present invention.
FIG. 2 is a cross-sectional structural diagram showing the structure of an optical sensor according to an embodiment of the present invention. That is, by shifting the spectral sensitivity toward longer wavelengths, an optical sensor with excellent red sensitivity can be achieved.
本実施例の光センサーは、耐熱性導電膜52a。The optical sensor of this embodiment has a heat-resistant conductive film 52a.
52bを被着した基板1上に、耐熱性導電膜52a、5
2bにまたがって、第1の導電型、第2の導電型、第3
の導電型を接合した、即ちp−1−N接合した非晶質シ
リコン半導体層53及び透明電極54を形成し、P−I
−N接合した積層体a。Heat-resistant conductive films 52a and 5
2b, the first conductivity type, the second conductivity type, and the third conductivity type.
An amorphous silicon semiconductor layer 53 and a transparent electrode 54 are formed in which the conductivity types of
-N bonded laminate a.
bが透明電極54を介して抱き合わされている。b are held together via a transparent electrode 54.
基板51、耐熱性導電膜52は、第1図の太陽電池同様
に、基板51はガラス、セラミック、ステンレスなどの
耐熱性を有する材料などから成り、耐熱性導電膜52
a、 52 bは、該基板51上に独立してチタン(
Ti)、ニッケル(Ni)、チタン−銀(Ti−Ag)
、クロム(Cr)、ステンレス、タングステン(W)、
銀(Ag)、白金(Pt)、タンタル(Ta)、コバル
ト(Co)等の金属が用いられる。Similar to the solar cell shown in FIG. 1, the substrate 51 and the heat-resistant conductive film 52 are made of a heat-resistant material such as glass, ceramic, and stainless steel.
a and 52 b are titanium (
Ti), nickel (Ni), titanium-silver (Ti-Ag)
, chromium (Cr), stainless steel, tungsten (W),
Metals such as silver (Ag), platinum (Pt), tantalum (Ta), and cobalt (Co) are used.
非晶質シリコン半導体層53は、少なくとも耐熱性導電
膜52a、52bが形成される積層体a。The amorphous silicon semiconductor layer 53 is a laminate a in which at least heat-resistant conductive films 52a and 52b are formed.
b部分には、第1の導電型、第2の導電型、第3の導電
型を接合、即ちP−I−N接合が形成されている。具体
的には、上述のように基板51側からN層−■層−P層
が積層されている。In the portion b, a first conductivity type, a second conductivity type, and a third conductivity type are joined, that is, a P-I-N junction is formed. Specifically, as described above, the N layer, the ■ layer, and the P layer are stacked from the substrate 51 side.
透明導電膜54は酸化錫、酸化インジウム、酸化インジ
ウム錫などの金属酸化物膜で形成され、少なくとも積層
体a、bに共通の膜となるように形成されている。具体
的には透明基板51の一主面上にマスクを装着した後、
上述の金属酸化物膜を電子ビーム法、熱分解法で被着さ
れる。The transparent conductive film 54 is formed of a metal oxide film such as tin oxide, indium oxide, or indium tin oxide, and is formed to be a film common to at least the laminates a and b. Specifically, after mounting a mask on one main surface of the transparent substrate 51,
The metal oxide film described above is deposited by an electron beam method or a thermal decomposition method.
そして、金属電極52a、52b間に外部回路(図示せ
ず)から一定のバイアス電圧を印加しておく。Then, a constant bias voltage is applied between the metal electrodes 52a and 52b from an external circuit (not shown).
上述の構成の光センサーは、P−1−N接合された#を
屠体a、bのダイオードが抱き合わされた構造になって
いる。The optical sensor having the above structure has a structure in which the diodes of the carcasses a and b are tied together with # connected to the P-1-N junction.
今、積層体aの金属電極52aに+、積層体すの金属電
極52bに−でバイアス電圧をかけておくと、積層体a
側の非晶質シリコン半導体層53aには逆バイアス、積
層体す側の非晶質シリコン半導体層53bには順バイア
スがかかることになる。Now, if a + bias voltage is applied to the metal electrode 52a of the laminate a and a negative voltage is applied to the metal electrode 52b of the laminate A, then the laminate a
A reverse bias is applied to the amorphous silicon semiconductor layer 53a on the side, and a forward bias is applied to the amorphous silicon semiconductor layer 53b on the side of the stack.
暗状態において、金属電極52a、52b間の抵抗は積
層体aの逆方向抵抗Raと積層体すの順方向抵抗Rbの
和になり、金属電極52a、52b間に流れる電流は、
該抵抗(Ra+Rb)に対応する。In the dark state, the resistance between the metal electrodes 52a and 52b is the sum of the reverse resistance Ra of the laminate a and the forward resistance Rb of the laminate A, and the current flowing between the metal electrodes 52a and 52b is
This corresponds to the resistance (Ra+Rb).
上述の光センサーの基板1の反対側より光照射される明
状態では、積層体a及び積層体すに光起電力が生じるが
、互いに逆電位であるため相殺され、実際には光起電流
は流れないものの、金属電極52aに+、金属電極52
bに−でバイアス電圧を印加されているので、積層体a
に逆方向光電流が発生する。なお、積層体すはダイオー
ドの順方向抵抗から成る抵抗体となる。In the bright state where light is irradiated from the opposite side of the substrate 1 of the above-mentioned photosensor, a photovoltaic force is generated in the laminate a and the laminate, but since they are at opposite potentials, they cancel each other out, and in reality, the photovoltaic current is Although it does not flow, there is + on the metal electrode 52a, and the metal electrode 52
Since a negative bias voltage is applied to b, the laminate a
A reverse photocurrent is generated. Note that the laminated body becomes a resistor consisting of a forward resistance of a diode.
そして、2つの金属電極52a、52b間の電流は積層
体aの金属電極52a−非晶質シリコン半導体層53a
のN層−1層−2層−透明導電膜54−積層体すの非晶
質シリコン半導体層53bの2層−■層−NM−金属電
極52bに流れる。The current between the two metal electrodes 52a and 52b is from the metal electrode 52a of the stacked body a to the amorphous silicon semiconductor layer 53a.
The current flows to the N layer, the first layer, the second layer, the transparent conductive film 54, the second layer of the amorphous silicon semiconductor layer 53b of the laminated body, the second layer, the NM layer, and the metal electrode 52b.
ここで、光センサー全体において見かけ上、光照射によ
って光導電率が低下したことになり、光導電型センサー
のようにはたらく。これにより、照度−抵抗値特性がリ
ニアとなり、γ値が約1となる。Here, the photoconductivity of the entire optical sensor appears to have decreased due to the light irradiation, and it functions like a photoconductive type sensor. As a result, the illuminance-resistance value characteristic becomes linear, and the γ value becomes approximately 1.
上述のように、本発明の特徴部分である非晶質シリコン
半導体層53の成膜で、非晶質シリコン半導体層53の
成膜における基板温度を400℃以上に設定すると、第
2図に示したように、初期特性から光劣化を有効に抑え
ることができる。As mentioned above, in the deposition of the amorphous silicon semiconductor layer 53, which is a feature of the present invention, if the substrate temperature in the deposition of the amorphous silicon semiconductor layer 53 is set to 400° C. or higher, the temperature as shown in FIG. As described above, photodeterioration can be effectively suppressed from the initial characteristics.
第3図から明らかなように、基板温度を300℃で作製
した光センサーよりも、基板温度を400℃(線 1)
で作製した光センサーのほうが、分光感度が長波長側に
シフトしており、長波長側に感度ピークが存在すること
が確認できる。これは、光センサーではブルー感度に優
れることになる。As is clear from Figure 3, the optical sensor fabricated at a substrate temperature of 400℃ (line 1)
It can be confirmed that the spectral sensitivity of the optical sensor fabricated using the method is shifted toward longer wavelengths, and the sensitivity peak exists on the longer wavelength side. This means that the optical sensor has excellent blue sensitivity.
さらに、上述のように非晶質シリコン半導体層53のN
層上に1層を形成する際に、N層中のリン原子などが活
性化し、1層中にまで混入してしまいフェルミレベルが
0.6eVに変化するが、この変化を補うために意図的
にP型ドープ剤である周期率表第■族元素を含むドープ
ガス、例えばジポラン(B2H2)を前記シランガスと
ともに反応ガスとして供給するとよい。Furthermore, as described above, N of the amorphous silicon semiconductor layer 53 is
When forming one layer on top of the other, phosphorus atoms in the N layer become activated and mix into the first layer, causing the Fermi level to change to 0.6 eV. In addition, it is preferable to supply a doping gas containing a Group Ⅰ element of the periodic table, which is a P-type dopant, such as diporan (B2H2) together with the silane gas as a reactive gas.
上述のように、基板温度を400℃、450℃で非晶質
シリコン半導体層を作製するために、現段階において透
明電極の膜特性より、ガラス基板上に透明電極−非晶質
シリコン半導体層−金属電極を被着した通常のタイプに
は不適合である。ただし、耐熱性透明電極が安価になり
、量産に適すればこの限りでなく、本出願人が先に提案
した特願昭62−331620号のような光センサーに
も適用できる。As mentioned above, in order to fabricate an amorphous silicon semiconductor layer at a substrate temperature of 400°C or 450°C, a transparent electrode - an amorphous silicon semiconductor layer - is placed on a glass substrate due to the film characteristics of the transparent electrode at this stage. It is not suitable for ordinary types covered with metal electrodes. However, as long as the heat-resistant transparent electrode becomes inexpensive and suitable for mass production, the present invention is not limited to this, and can also be applied to an optical sensor such as that proposed in Japanese Patent Application No. 62-331620 previously proposed by the present applicant.
以上のように、本発明は導電膜を被着した基板上に、P
−I−N接合した非晶質シリコン半導体層を形成する光
電変換装置において、前記導電膜に耐熱性金属を用いて
、該基板温度を400℃以上に設定し、P−I−N接合
した非晶質シリコン半導体層の少なくとも1層を被着す
る際に、高温に晒されることによって、1層中に拡散さ
れる一方の導電型の元素とは逆の導電型を決定する周期
率表第■族又は第■族の元素を0.2〜1.0PPm
供給したため、光劣化による初期特性の低下を良好に
抑えることができ、分光感度が長波長側に延びることが
で、安定した出力特性が得られる光電変換装置となる。As described above, the present invention provides P on a substrate coated with a conductive film.
In a photoelectric conversion device that forms an amorphous silicon semiconductor layer with a P-I-N junction, a heat-resistant metal is used for the conductive film, the substrate temperature is set to 400°C or higher, and the non-crystalline silicon semiconductor layer with a P-I-N junction is When depositing at least one of the crystalline silicon semiconductor layers, exposure to high temperatures determines the conductivity type opposite to the element of one conductivity type that is diffused into the layer. 0.2 to 1.0 PPm of elements of group or group
As a result, the deterioration of initial characteristics due to photodeterioration can be suppressed well, and the spectral sensitivity can be extended to the long wavelength side, resulting in a photoelectric conversion device that can obtain stable output characteristics.
これにより、光電変換装置の使用用途を拡大できるもの
となる。This allows the use of the photoelectric conversion device to be expanded.
第1図は本発明の光電変換装置の製造方法に係る太陽電
池の構造を示す断面図である。
第2図は本発明の光電変換装置の製造方法における基板
温度と光劣化の状態を示す特性図である。
第3図は本発明の光電変換装置の製造方法における基板
温度と分光感度の関係を示す特性図である。
第4図は、I層成脱時にシランに混入されるジボランの
流量とフェルミエネルギーとの関係を示す特性図である
。
第5図は、本発明に係る第2の実施例である太陽電池の
構造を示す断面図である。
第6図は、従来の光電変換装置であるアモルファスシリ
コン太陽電池素子の断面図である。
1.51 ・ ・ ・
2.52a 、 52b
3.53a ・ ・ ・
4.54、 ・ ・ ・
・・・絶縁基板
・・・耐熱性導電膜
非晶質シリコン半導体層
透明電極FIG. 1 is a sectional view showing the structure of a solar cell according to the method of manufacturing a photoelectric conversion device of the present invention. FIG. 2 is a characteristic diagram showing the state of substrate temperature and photodeterioration in the method for manufacturing a photoelectric conversion device of the present invention. FIG. 3 is a characteristic diagram showing the relationship between substrate temperature and spectral sensitivity in the method of manufacturing a photoelectric conversion device of the present invention. FIG. 4 is a characteristic diagram showing the relationship between the flow rate of diborane mixed into silane during I layer formation and Fermi energy. FIG. 5 is a sectional view showing the structure of a solar cell according to a second embodiment of the present invention. FIG. 6 is a cross-sectional view of an amorphous silicon solar cell element, which is a conventional photoelectric conversion device. 1.51 ・ ・ ・ 2.52a, 52b 3.53a ・ ・ ・ 4.54, ・ ・ ・ ...Insulating substrate...Heat-resistant conductive film Amorphous silicon semiconductor layer Transparent electrode
Claims (2)
晶質シリコン半導体層を形成した光電変換装置において
、 前記非晶質シリコン半導体層が、1.7ev〜1.5e
vの光学的ギャップで且つ非晶質シリコン半導体層中に
10at%未満の水素濃度であることを特徴とする光電
変換装置。(1) In a photoelectric conversion device in which a P-I-N bonded amorphous silicon semiconductor layer is formed on a heat-resistant metal conductive film, the amorphous silicon semiconductor layer has a temperature of 1.7ev to 1.5e.
1. A photoelectric conversion device characterized by an optical gap of v and a hydrogen concentration of less than 10 at % in an amorphous silicon semiconductor layer.
晶質シリコン半導体層を形成した光電変換装置の製造方
法において、 前記非晶質シリコン半導体層の少なくともI層を成膜基
板温度が400℃以上で被着するとともに、該I層中に
、I層上に被着されるP層又はN層を決定する周期率表
第III族又は第V族の元素と同一の元素を含有させるこ
とを特徴とする光電変換装置の製造方法。(2) In a method for manufacturing a photoelectric conversion device in which a P-I-N junction amorphous silicon semiconductor layer is formed on a conductive film of a heat-resistant metal, at least an I layer of the amorphous silicon semiconductor layer is formed. An element which is deposited at a substrate temperature of 400° C. or higher and which is the same element in Group III or V of the periodic table that determines the P layer or N layer deposited on the I layer, in the I layer. 1. A method for manufacturing a photoelectric conversion device, comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63276979A JPH02122576A (en) | 1988-10-31 | 1988-10-31 | Photoelectric conversion device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63276979A JPH02122576A (en) | 1988-10-31 | 1988-10-31 | Photoelectric conversion device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02122576A true JPH02122576A (en) | 1990-05-10 |
Family
ID=17577076
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63276979A Pending JPH02122576A (en) | 1988-10-31 | 1988-10-31 | Photoelectric conversion device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02122576A (en) |
-
1988
- 1988-10-31 JP JP63276979A patent/JPH02122576A/en active Pending
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