JPH02121360A - Electronic component mounting substrate - Google Patents
Electronic component mounting substrateInfo
- Publication number
- JPH02121360A JPH02121360A JP63274137A JP27413788A JPH02121360A JP H02121360 A JPH02121360 A JP H02121360A JP 63274137 A JP63274137 A JP 63274137A JP 27413788 A JP27413788 A JP 27413788A JP H02121360 A JPH02121360 A JP H02121360A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- conductor pattern
- electronic component
- component mounting
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title abstract description 8
- 239000004020 conductor Substances 0.000 claims abstract description 47
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 32
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052737 gold Inorganic materials 0.000 claims abstract description 19
- 239000010931 gold Substances 0.000 claims abstract description 19
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052802 copper Inorganic materials 0.000 claims abstract description 13
- 239000010949 copper Substances 0.000 claims abstract description 13
- 238000007747 plating Methods 0.000 claims description 22
- 229910000679 solder Inorganic materials 0.000 abstract description 18
- 239000000463 material Substances 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 8
- 239000000919 ceramic Substances 0.000 abstract description 2
- 239000003822 epoxy resin Substances 0.000 abstract 1
- 229920000647 polyepoxide Polymers 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 7
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 239000008188 pellet Substances 0.000 description 4
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000006071 cream Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Manufacturing Of Printed Wiring (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、電子部品搭載用基板に関し、特に、外部接続
端子となるリードを、電子部品が搭載される配線基板上
の５ｉ４Ｎからなる導体パターンに接続した電子部品搭
載用基板に関する。Detailed Description of the Invention (Industrial Application Field) The present invention relates to a board for mounting electronic components, and in particular, leads serving as external connection terminals are connected to conductor patterns made of 5i4N on a wiring board on which electronic components are mounted. This invention relates to a board for mounting electronic components connected to the board.
（従来の技術）
近年の高密度化された電子部品は、そのままでは各種電
子機器を構成することができないから、これを基板に実
装してから使用することとなる。(Prior Art) Since recent high-density electronic components cannot be used to construct various electronic devices as they are, they must be mounted on a board before use.
そのために、従来より種々の形式の電子部品搭載用基板
あるいは、装置が開発され提案されてきている。To this end, various types of electronic component mounting boards or devices have been developed and proposed.
電子部品とリード等の外部に接続するための端子とを、
基板において接続する形式としては種々なものがある。Connect electronic components to external terminals such as leads,
There are various types of connections on the board.
この電子部品とリード等の外部に接続するための端子と
を所定配列にして接続する形式としては、例えば、所定
配列にして植設した多数の導体ビンと基板上の導体回路
を介して電子部品とを接続する所謂ＰＧＡ、基板上の導
体回路の一部を電子部品が直接搭載されるフィンガーリ
ードとする所謂ＴＡＢ、リードと電子部品とをワイヤー
ボンディングして、その全体をモールドする所ｍ Ｄ
Ｉ ＰあるいはＱＦＰ等がある。For example, the electronic component can be connected to external terminals such as leads in a predetermined arrangement through a large number of conductor bins planted in a predetermined arrangement and a conductor circuit on the board. There is a so-called PGA, which connects a part of the conductor circuit on the board to a finger lead on which an electronic component is directly mounted, a so-called TAB, where the lead and the electronic component are wire-bonded, and the whole is molded.
There are IP, QFP, etc.
これらのうち、例えば互いに電気的に独立した複数のリ
ードを基材から突出させるとともに、この基材上に搭載
した電子部品の接続部と各リードとを電気的に接続した
ＱＦＰ形式の基板を例にとってみても、特開昭５９−９
８５４５号公報等においてその具体化されたものが種々
提案されている。この特開昭５９−９８５４５号公報等
において提案されているのは、
「導電層を形成したペレット取付は基板の上にペレット
を取り付け、前記ペレットのポンディングパッドと前記
導体層とをワイヤーボンディングにより電気的に接続し
、前記ペレット取付板の前記導電層をリードフレームに
接合してなる半導体装置」
であるが、このような混成集積回路装置を代表とする従
来の電子部品搭載用基板の基本構成とじては、第８図に
示すようなものがあげられる。この従来の電子部品搭載
用基板は、配線基板（４）上に導体パターン（３）を形
成し、この導体パターン（３）にニッケルめっき及び金
めつき（７）を施して、このめっきが施された導体パタ
ーン（３）上に、はんだ（６）によりリード（１）を接
続したものであり、このような電子部品搭載用基板は、
第９図に示すように、電子部品（５）が搭載されると共
にこの電子部品（５）と導体パターン＜３）とをワイヤ
ーボンディングした後、樹脂封止等することによって、
電子部品搭載装置（９）を形成するのに用いられるもの
である。Among these, an example is a QFP type board in which multiple leads that are electrically independent of each other protrude from a base material and each lead is electrically connected to the connection part of an electronic component mounted on this base material. Even if you look at it, JP-A-59-9
Various embodiments have been proposed in JP-A No. 8545 and the like. What is proposed in JP-A-59-98545 and others is that ``In the case of attaching a pellet with a conductive layer formed thereon, the pellet is attached on a substrate, and the bonding pad of the pellet and the conductor layer are connected by wire bonding. A semiconductor device which is electrically connected to the conductive layer of the pellet mounting plate and bonded to a lead frame.'' However, the basic structure of a conventional electronic component mounting board typified by such a hybrid integrated circuit device is Examples of closures include those shown in Figure 8. This conventional electronic component mounting board has a conductor pattern (3) formed on a wiring board (4), and this conductor pattern (3) is plated with nickel and gold (7). The lead (1) is connected to the conductor pattern (3) by solder (6), and such a board for mounting electronic components is
As shown in FIG. 9, after mounting the electronic component (5) and wire bonding the electronic component (5) and the conductor pattern <3), the electronic component (5) is sealed with resin, etc.
This is used to form an electronic component mounting device (9).
（発明が解決しようとする課題）
ところが、以上のような構成をとると、第１θ図に示す
ように、リード（１）を配線基板（４）上の導体パター
ン（３）のリード接続部（２）に、安価でかつ十分な精
度で接続することは、非常に困難である。(Problem to be Solved by the Invention) However, with the above configuration, as shown in Fig. 1θ, the lead (1) is connected to the lead connection portion (3) of the conductor pattern (3) on the wiring board (4). 2) is extremely difficult to connect at low cost and with sufficient accuracy.
なぜならば、十分な精度で位置決めする方法として、例
えば、配線基板（４）あるいはリード（１）の一方又は
両方に位置決め用の穴あるいはパターンを設けておき、
それを使用して位置合わせする方法が考えられるが、そ
の場合、画像処理をするシステム等が必要となり、非常
に高価なものとなってしまうからである。This is because, as a method for positioning with sufficient accuracy, for example, holes or patterns for positioning are provided in one or both of the wiring board (4) or the leads (1).
Although it is conceivable to use this method for alignment, this would require a system for image processing, which would be extremely expensive.
一方、安価に接続する方法としては、配線基板（４）の
外形を利用し位置合わせする方法が考えられるが、配線
基板（４）の外形加工を安価な方法で行うと、精度良く
行うことができず、接続不良といった問題が発生し、好
ましくない。又、精度良く外形加工する方法も考えられ
るが、その場合、安価に実現することは非常に難しいも
のである。On the other hand, an inexpensive way to connect may be to use the outer shape of the wiring board (4) for alignment; however, if the outer shape of the wiring board (4) is processed using an inexpensive method, it is possible to achieve high accuracy. This is undesirable because it causes problems such as poor connection. Alternatively, a method of accurately machining the outer shape may be considered, but in that case, it is extremely difficult to realize it at a low cost.
また、次のような課題もあげられる。一般に、金属細線
、特に金細線で接続される電子部品（５）が搭載される
電子部品搭載用基板には、それを十分な強度で接続する
ために、金属細線と同一種類のめっきを厚さ０．５〜１
μｍするものである。しかし、前記リード（１）と前記
リード接続部（２）をはんだ（６）により接続すると、
そこには金とばんだ（６）の非常にもろい金属層が形成
されることとなり、リード（１）と配線基板（４）のリ
ード接続部（２）の接続信頼性を大きく低下させる原因
となるものである。Additionally, the following issues can be raised: In general, electronic component mounting boards on which electronic components (5) connected by thin metal wires, particularly thin gold wires, are mounted are coated with the same type of plating as the thin metal wires to a certain thickness in order to connect them with sufficient strength. 0.5~1
It is μm. However, when the lead (1) and the lead connection part (2) are connected by solder (6),
A very brittle metal layer of gold and solder (6) will be formed there, which will greatly reduce the connection reliability between the lead (1) and the lead connection part (2) of the wiring board (4). It is what it is.
そこで、本発明者等は、以上の課題を解決すべく鋭意研
究してきた結果、配線基板上に形成された銅層からなる
導体パターンのうちリード接続部は露出し、他の導体パ
ターン上にはニッケルめっき及び金めつきが施されて、
前記リード接続部とそれに連なる導体パターンの境界に
リード位置決め用段差を形成することが良い結果を生む
ことを新たに知見し、本発明を完成したのである。Therefore, the inventors of the present invention have conducted intensive research to solve the above problems. As a result, the lead connection portions of the conductor pattern made of a copper layer formed on the wiring board are exposed, and the lead connection portions are exposed on other conductor patterns. Nickel plated and gold plated,
The present invention was completed based on the new finding that forming a lead positioning step at the boundary between the lead connection portion and the conductor pattern connected thereto produces good results.
そして、本発明の目的とするところは、配線基板上のリ
ード接続部とリードを容易にかつ精度良く位置決めさせ
、かつ、接続信頼性の高い電子部品搭載用基板を提供す
ることにある。An object of the present invention is to provide an electronic component mounting board that allows lead connection portions and leads on a wiring board to be easily and precisely positioned, and that has high connection reliability.
（課題を解決するための手段）
以上の課題を解決するために本発明者等が採った手段は
、実施例に対応する第１図〜第７図を参照して説明する
と、
「外部接続端子（１２）となるリード（＋）を、電子部
品（５）が搭載される配線基板（４）上の導体パターン
（３）に接続した電子部品搭載用基板（８）において、
前記導体パターン（３）のうちリード接続部（２）はｆ
ｉｌ！が露出し、このリード接続部（２）に連なる導体
パターン（３）上にはニッケルめっき及び金めつき（７
）が施されて、前記リード接続部（２）とそれに連なる
導体パターン（３）の境界にリード位置決め用段差（ｌ
Ｏ）が形成されていることを特徴とする電子部品搭載用
基板（８）」
である。(Means for Solving the Problems) The means taken by the present inventors to solve the above problems are explained with reference to FIGS. 1 to 7 corresponding to the embodiments. In the electronic component mounting board (8), the lead (+) of (12) is connected to the conductor pattern (3) on the wiring board (4) on which the electronic component (5) is mounted.
The lead connection portion (2) of the conductor pattern (3) is f
Il! is exposed, and nickel plating and gold plating (7
), and a lead positioning step (l
"Substrate for mounting electronic components (8)" characterized in that O) is formed.
以上の本発明者等が採った手段を、図面に示した具体例
に従って詳細に説明すると、次の通りである。The above measures taken by the present inventors will be explained in detail according to the specific example shown in the drawings as follows.
まず、この電子部品搭載用基板（８）は、これに搭載す
る各電子部品（５）を、その配線基板（４）から外部に
突出する各リード（＋）によって他の大型基板等に実装
する形式のものであり、この電子部品搭載用基板（８）
は外部接続端子（１２）となるリード（１）をはんだ（
６）によって、配線基板（４）上の導体パターン（３）
に接続したものである。ここで使用される配線基板（４
）としては、ガラスエポキシ等の樹脂系あるいはセラミ
ック等の材料の片面あるいは両面に、必要な導体パター
ン（３）が形成されており、この導体パターン（３）の
うちリード接続部（２）は銅層が露出し、このリード接
続部（２）に連なる導体パターン（３）上にはニッケル
めっき及び金めっき（７）が施された所謂部分めっきさ
れた配線基板（４）を用いる。この部分めっきの方法と
しては、感光性フィルムを用いてめっきマスクを形成す
る方法等が考えられるが、特に制限を受けるものではな
い。又、はんだ（６）の付与方法とじては、リード（１
）にはんだめっきする方法、あるいはリード（＋）上に
クリームはんだを塗布する方法等が考えられる。First, this electronic component mounting board (8) is used to mount each electronic component (5) to be mounted on another large board etc. using each lead (+) protruding outside from the wiring board (4). This board for mounting electronic components (8)
Solder the lead (1) that will become the external connection terminal (12) (
6), the conductor pattern (3) on the wiring board (4)
It is connected to. The wiring board used here (4
), the necessary conductor pattern (3) is formed on one or both sides of a resin-based material such as glass epoxy or a material such as ceramic, and the lead connection part (2) of this conductor pattern (3) is made of copper. A so-called partially plated wiring board (4) is used in which the layer is exposed and the conductor pattern (3) connected to the lead connection part (2) is coated with nickel plating and gold plating (7). As a method for this partial plating, a method of forming a plating mask using a photosensitive film can be considered, but there are no particular limitations. In addition, the method of applying solder (6) is as follows: lead (1)
), or applying cream solder on the lead (+).
本発明に使用できる配線基板材料としては、前記の他に
、シリコン、ポリイミド、アルミナ、ガラストリアジン
、あるいは金属ベース上にポリイミド、ガラストリアジ
ン等の絶縁層を有する所謂金属ベース基板等、要するに
絶縁層上に導体パターンを形成できるものであれば何で
も良い。In addition to the above, wiring board materials that can be used in the present invention include silicon, polyimide, alumina, glass triazine, or a so-called metal base substrate having an insulating layer of polyimide, glass triazine, etc. on a metal base. Any material that can form a conductive pattern may be used.
リード（＋）の材料においても、必要な導電性を有して
いれば何でも良く、銅系、鉄系あるいは４２７０イ又は
それらの複合材料等でも何ら問題はない。The material for the lead (+) may be any material as long as it has the necessary conductivity, and there is no problem with copper-based, iron-based, 4270I, or composite materials thereof.
なお、この形式の基板は、−例として第２図に示すよう
に電子部品（５）が搭載されると共に電子部品と導体パ
ターンとがワイヤーボンディングされ、さらに樹脂等に
よって封止され、電子部品搭載装置（９）となるもので
ある。Note that this type of board is equipped with an electronic component (5) as shown in FIG. This is the device (9).
（発明の作用）
本発明が以上のような手段を採ることにより、次のよう
な作用がある。(Actions of the Invention) By adopting the above measures, the present invention has the following effects.
配線基板（４）上のリード接続部（２）と、それに連な
る導体パターンの境界（１１）に段差（１０）が形成さ
れているため、リード（１）と配線基板（４）の位置決
めが安価にかつ容易にしかも精度よく行えるという作用
がある。Since a step (10) is formed between the lead connection part (2) on the wiring board (4) and the boundary (11) between the conductor pattern connected thereto, positioning of the lead (1) and the wiring board (4) is inexpensive. It has the effect of being easy to perform and highly accurate.
また、配線基板（４）上のリード接続部（２）には、ニ
ッケルめっき及び金めつき層（７）がないため、リード
（１）とのはんだ接続時に、強度の弱い合金層が形成さ
れることなく、よって信頼性の高い電子部品搭載用基板
を提供するという作用も有するものである。In addition, since the lead connection part (2) on the wiring board (4) does not have nickel plating or gold plating layer (7), a weak alloy layer is formed when it is soldered to the lead (1). Therefore, it also has the effect of providing a highly reliable electronic component mounting board.
（実施例）
次に、本発明を図面に示した各実施例に従って詳細に説
明する。(Example) Next, the present invention will be described in detail according to each example shown in the drawings.
実」１例」−
第１図は本発明の第一実施例を示す部分断面図、第３図
はリード（１）と配線基板（４）を位置合わせした状態
の部分断面図、又、第４図は第３図においてリード接続
部（２）の部分拡大断面図である。なお、第２図は本実
施例の電子部品搭載用基板（８）に電子部品（５）がｔ
ｆ載され、電子部品搭載装置（９）とした状態の部分断
面図である。1 is a partial cross-sectional view showing the first embodiment of the present invention, and FIG. 3 is a partial cross-sectional view showing the lead (1) and wiring board (4) aligned. FIG. 4 is a partially enlarged sectional view of the lead connection portion (2) in FIG. 3. In addition, FIG. 2 shows that the electronic component (5) is mounted on the electronic component mounting board (8) of this embodiment.
FIG. 3 is a partial cross-sectional view of the electronic component mounting device (9).
これらの図において、配線基板（４）としては片面のガ
ラストリアジン上に必要な銅層からなる導体パターン（
３）を形成したものを使用し、リード接続部（２）は露
出させ、かつ他の部分にはニッケルめっき及び金めフき
層（７）が形成されており、そこには、リード（１）位
置決め用の段差（１０）が形成されている。一方、リー
ド（＋）としては４２７０イ系のものを使用し、リード
接続部（２）には部分的にはんだめっきをし、はんだ（
６）を付与している。その後、第４図のごとくリード（
１）と配線基板（４）を前記段差（１０）を使用し位置
合わせし、はんだ（６）をリフローさせ両者を接続し、
第１図のごとく、本発明による電子部品搭載用基板（８
）を完成した。この電子部品搭載用基板（８）は電子部
品（５）が搭載され、第２図のごとく電子部品搭載装置
（９）となるものである。In these figures, the wiring board (4) is a conductor pattern (4) consisting of a necessary copper layer on one side of glass triazine.
The lead connection part (2) is exposed, and the other parts are covered with nickel plating and gold plating layer (7). ) A step (10) for positioning is formed. On the other hand, the lead (+) is of the 4270 series, and the lead connection part (2) is partially plated with solder.
6) is given. After that, lead as shown in Figure 4 (
1) and the wiring board (4) using the step (10), reflow the solder (6) to connect them,
As shown in FIG. 1, an electronic component mounting board (8
) was completed. This electronic component mounting board (8) has electronic components (5) mounted thereon, and serves as an electronic component mounting device (9) as shown in FIG.
寛止皇１
第６図は本発明の第二実施例を示す図であって、リード
（１）と配線基板（４）を位置合わせした状態のり一ト
接続部（２）の部分拡大断面図である。配線基板（４）
上の導体パターン（３）のリード接続部（２）は、銅層
（１）がハーフエツチングされており、かつ他の導体パ
ターン（３）上にはニッケルめっき及び金めつき層（７
）が形成されている。この場合、ハーフエツチングされ
た厚みだけ第一実施例の場合より段差（１０）が大きく
、よって位置決めも容易かつ確実になるものである。一
方リード（１）としては銅系のものを使用し、第一実施
例と同様、リード接続部（２）には部分めっきにより、
はんだ（６）を付与している。その後、第６図に示すよ
うに、配線基板（４）とリード（１）を前記段差（！０
）を使用し位置合わせし、はんだ（６）をリフローさせ
、第５図のごとく本実施例に係る電子部品搭載用基板（
８）を完成したものである。Kanjiko 1 FIG. 6 is a diagram showing a second embodiment of the present invention, and is a partially enlarged sectional view of the glue connection part (2) with the lead (1) and the wiring board (4) aligned. It is. Wiring board (4)
In the lead connection part (2) of the upper conductor pattern (3), the copper layer (1) is half-etched, and the other conductor pattern (3) is coated with nickel plating and gold plating layer (7).
) is formed. In this case, the step (10) is larger than in the first embodiment by the half-etched thickness, and therefore positioning becomes easier and more reliable. On the other hand, the lead (1) is made of copper, and the lead connection part (2) is partially plated as in the first embodiment.
Solder (6) is applied. Thereafter, as shown in FIG.
) to align the position, reflow the solder (6), and as shown in Fig. 5, the electronic component mounting board (
8) has been completed.
寛胤■ユ
第７図は本発明の第三実施例を示す図であって、リード
（１）と配線基板（４）を位置合わせした後のリード接
続部（２）の部分拡大断面図である。本図において、配
線基板（４）は第一実施例と同様に、銅層からなる導体
パターン（３）のリード接続部（２）は鋼表面が露出し
ており、かつ他の導体パターン（３）は、ニッケルめっ
き及び金めつき層（７）が形成され、そこに段差（１０
）を有するものである。また、はんだ（６）は、クリー
ムはんだとしてリード（１）のリード接続部（２）上に
塗布されており、前記めっき層（７）により形成された
段差（ｌＯ）により、リード（＋）と配線基板（４）は
位置合わせされた状態にある。その後、はんだ（６）を
リフローさせ、リード（１）と配線基板（４）を接続し
て、第１図と同様の電子部品搭載用基板（８）を完成し
たものである。Hiratane's Figure 7 is a diagram showing a third embodiment of the present invention, and is a partially enlarged cross-sectional view of the lead connection part (2) after aligning the lead (1) and the wiring board (4). be. In this figure, the wiring board (4) has the steel surface exposed at the lead connection part (2) of the conductor pattern (3) made of a copper layer, and the other conductor pattern (3) is similar to the first embodiment. ), a nickel plating and gold plating layer (7) is formed, and a step (10) is formed thereon.
). Further, the solder (6) is applied as a cream solder on the lead connection portion (2) of the lead (1), and the step (lO) formed by the plating layer (7) connects the lead (+) with the solder (6). The wiring board (4) is in an aligned state. Thereafter, the solder (6) was reflowed, the leads (1) and the wiring board (4) were connected, and an electronic component mounting board (8) similar to that shown in FIG. 1 was completed.
（発明の効果）
以上、要するに本発明にあっては、前記実施例にて例示
した如く、
「外部接続端子（１２）となるリード（１）を、電子部
品（５）が搭載される配線基板（４）上の導体パターン
（３）に接続した電子部品搭載用基板（８）において、
前記導体パターン（３）のうちリード接続部（２）は銅
層が露出し、このリード接続部（２）に連なる導体パタ
ーン（３）上にはニッケルめっき及び金めつき（７）が
施されて、前記リード接続部（２）とそれに連なる導体
パターン（３）の境界にリード位置決め用段差（１０）
が形成されていること」にその構成上の特徴があり、次
に示すような具体的効果を有するものである。(Effects of the Invention) In short, in the present invention, as exemplified in the above embodiment, "the lead (1) serving as the external connection terminal (12) is connected to the wiring board on which the electronic component (5) is mounted. (4) In the electronic component mounting board (8) connected to the upper conductor pattern (3),
The copper layer of the lead connection portion (2) of the conductor pattern (3) is exposed, and the conductor pattern (3) connected to the lead connection portion (2) is plated with nickel and gold (7). A lead positioning step (10) is provided at the boundary between the lead connection portion (2) and the conductor pattern (3) connected thereto.
Its structural feature lies in the fact that it is formed, and it has the following specific effects.
つまり、配線基板（４）上に形成された導体パターン（
３）の銅層が露出したリード接続部（２）と、それに連
なる導体パターン（３）の境界（１１）には、ニッケル
めっき及び金めつき層（７）により形成されたリード（
＋）の位置決め用段差（１０）を有しており、この位置
決め用段差（ｌＯ）により、両者の位置決めが安価であ
り、かつ、容易で、しかも精度良く行うことができると
いう効果がある。In other words, the conductor pattern (
At the boundary (11) between the lead connection part (2) where the copper layer (3) is exposed and the conductor pattern (3) connected thereto, there is a lead (3) formed of a nickel plating and gold plating layer (7).
+) positioning step (10), and this positioning step (lO) has the effect that positioning of both can be performed at low cost, easily, and with high precision.
また、配線基板（４）上のリード接続部（２）には、ニ
ッケルめっき及び金めつきＮ（７）がないため、はんだ
（６）により両者を接続しても、そこにもろく、強度の
弱いはんだ（６）と金の合金層が形成されることがなく
、よって接続信頼性の高い電子部品搭載用基板（８）を
提供することができるという効果もある。In addition, the lead connection part (2) on the wiring board (4) is not plated with nickel or gold (7), so even if they are connected with solder (6), it is brittle and has no strength. There is also the effect that a weak alloy layer of the solder (6) and gold is not formed, and therefore an electronic component mounting board (8) with high connection reliability can be provided.
第１図は本発明に係る電子部品搭載用基板の第一実施例
を示す部分断面図、第２図は第１図の電子部品搭載用基
板を用いた電子部品搭載装置の部分断面図、第３図はリ
ードと配線基板を位置合わせした状態の部分断面図、第
４図は第３図の部分拡大断面図、第５図は第二実施例に
係る電子部品搭載用基板の部分拡大断面図、第６図は第
５図においてリードと配線基板を位置合わせした状態の
部分拡大断面図、第７図は第三実施例に係る電子部品搭
載用基板の部分拡大断面図、第８図は従来の電子部品搭
載用基板を示す部分断面図、第９図は第８図の従来の電
子部品搭載用基板を用いた電子部品搭載装置を示す部分
断面図、第１０図は従来の電子部品搭載用基板において
リードと配線基板を位置合わせした状態の部分断面図で
ある。
符 号 の 説 明
１・・・リード、２・・・リード接続部、３・・・導体
パターン、４・・・配線基板、５・・・電子部品、６・
・・はんだ、７・・・ニッケルめっき及び金めつき、８
・・・電子部品搭載用基板、９・・・電子部品搭載装置
、１０・・・段差、ＩＩ・・・境界、１２・・・外部接
続端子。
第１図
第４図
］］
第５図
第
図
第
図
第１０図FIG. 1 is a partial sectional view showing a first embodiment of the electronic component mounting board according to the present invention, and FIG. 2 is a partial sectional view of an electronic component mounting apparatus using the electronic component mounting board of FIG. 3 is a partial cross-sectional view of the lead and wiring board aligned, FIG. 4 is a partial enlarged cross-sectional view of FIG. 3, and FIG. 5 is a partial enlarged cross-sectional view of the electronic component mounting board according to the second embodiment. , FIG. 6 is a partially enlarged cross-sectional view of the lead and wiring board aligned in FIG. 5, FIG. 7 is a partially enlarged cross-sectional view of the electronic component mounting board according to the third embodiment, and FIG. 8 is a conventional one. 9 is a partial sectional view showing an electronic component mounting device using the conventional electronic component mounting board of FIG. 8, and FIG. 10 is a partial sectional view showing a conventional electronic component mounting board of FIG. FIG. 3 is a partial cross-sectional view of a state where the leads and the wiring board are aligned on the board. Explanation of symbols 1...Lead, 2...Lead connection part, 3...Conductor pattern, 4...Wiring board, 5...Electronic component, 6...
...Solder, 7...Nickel plating and gold plating, 8
... Electronic component mounting board, 9... Electronic component mounting device, 10... Step, II... Boundary, 12... External connection terminal. Figure 1 Figure 4] Figure 5 Figure Figure 10
Claims (1)
線基板上の導体パターンに接続した電子部品搭載用基板
において、 前記導体パターンのうちリード接続部は銅層が露出し、
このリード接続部に連なる導体パターン上にはニッケル
めっき及び金めっきが施されて、前記リード接続部とそ
れに連なる導体パターンの境界にリード位置決め用段差
が形成されていることを特徴とする電子部品搭載用基板
。[Scope of Claims] An electronic component mounting board in which a lead serving as an external connection terminal is connected to a conductor pattern on a wiring board on which an electronic component is mounted, wherein a copper layer is exposed at the lead connection part of the conductor pattern. ,
An electronic component mounting device characterized in that nickel plating and gold plating are applied to the conductor pattern continuous to the lead connection part, and a step for lead positioning is formed at the boundary between the lead connection part and the conductor pattern continuous to the lead connection part. board for.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63274137A JP2652222B2 (en) | 1988-10-28 | 1988-10-28 | Substrate for mounting electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63274137A JP2652222B2 (en) | 1988-10-28 | 1988-10-28 | Substrate for mounting electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02121360A true JPH02121360A (en) | 1990-05-09 |
| JP2652222B2 JP2652222B2 (en) | 1997-09-10 |
Family
ID=17537539
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63274137A Expired - Lifetime JP2652222B2 (en) | 1988-10-28 | 1988-10-28 | Substrate for mounting electronic components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2652222B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0656150A4 (en) * | 1992-08-21 | 1995-11-29 | Olin Corp | Metal electronic package incorporating a multi-chip module. |
| US5655919A (en) * | 1994-09-02 | 1997-08-12 | Yazaki Corporation | Electric connection device interposed between handle and steering column of automotive vehicle |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62243302A (en) * | 1986-04-15 | 1987-10-23 | ロ−ム株式会社 | Method of attaching lead parts in electronic parts |
-
1988
- 1988-10-28 JP JP63274137A patent/JP2652222B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62243302A (en) * | 1986-04-15 | 1987-10-23 | ロ−ム株式会社 | Method of attaching lead parts in electronic parts |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0656150A4 (en) * | 1992-08-21 | 1995-11-29 | Olin Corp | Metal electronic package incorporating a multi-chip module. |
| US5655919A (en) * | 1994-09-02 | 1997-08-12 | Yazaki Corporation | Electric connection device interposed between handle and steering column of automotive vehicle |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2652222B2 (en) | 1997-09-10 |
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