JPH02126679A - Mos transistor - Google Patents

Abstract

PURPOSE:To obtain an excellent element characteristic by means of a fine structure by a method wherein an edge part of a gate electrode in a gate insulating film for a MOS transistor is constituted of a type of material which is different from that on a main part of a channel region. CONSTITUTION:A gate electrode 4 by a polycrystalline silicon film is formed in an element-isolation region of a p-type Si substrate 1 via a silicon oxide film 3 to be used as a gate insulating film. The SiO2 film 3 is, e.g., in about 100Angstrom . A source diffusion layer and a drain diffusion layer 51, 52 are formed in self-alignment with the gate electrode 4. A silicon nitride film 2 as a gate insulating film is inserted in an edge part of the gate electrode 4 separately from a gate insulating film on a main part of a channel region. A film thickness of this Si3N4 film 2 is set, e.g., at two to three times that of the SiO2 film 3. An intrusion amount of the Si3N4 film from the edge part of the gate electrode to the side of the channel region is about 500Angstrom . The surface of the substrate where an element has been formed is covered with a CVD SiO2 film 6; contact holes are made; a source electrode and a drain electrode 71, 72 are arranged and installed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a MOS transistor, and more particularly to a microstructured MOS transistor used in a high-density integrated circuit.

(Prior Art) The scale-up of MO3 integrated circuits represented by semiconductor memories has been remarkable, and MOS transistors used in such integrated circuits have been miniaturized to have gate lengths of 1 μm or less.

Various problems arise with miniaturization of MOS transistors, one of which is an increase in drain leakage current. One reason for the increase in drain leakage current is
Damage may occur during gate electrode patterning using reactive ion etching. That is, the gate insulating film and the substrate under the edge of the gate electrode are hit by ions and damaged, and this damage increases leakage current.

This can be called defective leakage current.

One of the reasons why defective leakage current becomes obvious is that the vertical electric field between the gate and drain becomes extremely large. The miniaturization of MOS transistors includes thinning of the gate insulating film, and MOS transistors with extremely thin gate insulating films
In an S transistor, a high electric field is formed between the drain and the gate in an off state in which a voltage is applied to the drain. Basically, in order to alleviate this vertical electric field, the thickness of the gate insulating film 1v can be increased. However, since I of the gate insulating film is a parameter for obtaining important device characteristics such as threshold value, it is easy to use! We cannot afford to make it thicker than 11.

(Problems to be Solved by the Invention) As described above, in the advanced MOS transistor, large drain and There was a problem with leakage current.

The present invention has solved these problems. It is an object of the present invention to provide a MO3I-transistor that has a fine structure and provides excellent device characteristics.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides, firstly, that the gate electrode edge portion of the gate insulating film of the MOS transistor is made of a material different from that on the main portion of the channel region. It is characterized by

A second feature of the present invention is that the gate electrode edge portion of the gate insulating film of the MO3I-transistor has a 21 steep structure.

(Function) If the gate electrode edge part of the gate insulating film is made of a different material from the main part, the influence of damage during the reactive ion etching process can be reduced by selecting the material and film thickness. In addition, the vertical electric field between the gate electrode and the substrate can be reduced to V. This makes it possible to reduce drain leakage current in miniaturized to 10S transistors. At this time, if the gate insulating film used at the edge of the gate electrode is made of a material with a high dielectric constant, the film thickness may be thicker than that on the main part of the channel region without adversely affecting the device characteristics.

Furthermore, if the gate insulating film has a two-layer structure at the edge of the gate electrode, it is possible to reduce the effects of damage in this area during the reactive ion etching process, and it is also possible to alleviate the vertical electric field. . Therefore, this makes it possible to reduce drain leakage current in the miniaturized MOS transistor.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a MOS transistor of one embodiment. A gate electrode 4 made of a polycrystalline silicon film is formed in an element-isolated region of a p-type S1 substrate 1 with a silicon oxide film (S i 02 film) 3 serving as a gate insulating film interposed therebetween. 5i0
For example, about 100 people formed the second film 3. Source and drain diffusion layers 51 and 52 are formed on this gate electrode 4 in a self-aligned manner. At the edge portion of the gate electrode 4, a silicon nitride film (Si3N4 film) 2 is sandwiched as a gate insulating film in addition to the gate insulating film on the main part of the channel region. This Si3N4 film 2 has a film thickness of 5i02 film 3, for example.
~3 times. Further, the amount of encroachment of this Si3N4 film 2 from the edge of the gate electrode toward the channel region side is approximately 500 degrees.

The substrate on which the elements have been formed is covered with a CVD5 i○2 film 6, and a contact hole is opened in this to form a source.

Drain electrodes 71 and 72 are provided.

FIGS. 2(a) to 2(c) are process diagrams for manufacturing the MOS transistor of this embodiment. To explain the manufacturing process using this, first, an Si3N4 film 2 is deposited by CVD on the entire surface of the element-isolated p-type Si substrate 1 (a). Next, this Si3N4 film 2 is patterned using lithography technology to expose a portion of the substrate surface that will become the channel region of the MOS transistor (b). Thereafter, a 5i02 film 3 is formed on the exposed substrate surface by thermal oxidation, and then a polycrystalline silicon film is deposited and patterned using reactive ion etching to form a gate electrode 4. Then, using the gate electrode 4 as a mask, impurity ions are implanted to form a source/drain diffusion layer 51.5□ (C). Below, the entire surface is coated with CVD5i according to the normal process.
02 membrane 6 and make contact holes to connect electrodes 71 and 72.
form.

According to this embodiment, the Si3N4 film 2 is used as the gate insulating film at the edge of the gate electrode, and is made thicker than the 5i02 film 3 which is the gate insulating film at the main part. As a result, the vertical electric field at the edge of the gate electrode is relaxed compared to conventional elements. Furthermore, damage to the substrate surface at the edge of the gate electrode due to reactive ion etching during gate electrode patterning can be suppressed. These results reduce defective drain leakage current.

The Si3N4 film has a higher dielectric constant than the SiO□ film, so sandwiching a thick Si3N4 film between the edges of the gate electrode will not adversely affect other device characteristics.

FIG. 5 qualitatively shows the gate voltage Vg-drain current 1d characteristic of the MOS transistor according to this embodiment in comparison with the conventional example. Drain voltage below threshold voltage vth
Leakage current is greatly reduced by this embodiment.

FIG. 3 shows a MOS transistor according to another embodiment of the present invention. Portions corresponding to those in FIG. 1 are designated by the same reference numerals as in FIG. 1, and detailed description thereof will be omitted. The difference from the embodiment shown in FIG. 1 is that the 5i02 film 3 as a gate insulating film is formed over the entire region from the source region to the drain region, and the edge portion of the gate electrode 4 is formed by a SiO□ film 3 and a Si3N film 3.
The point is that it has a two-layer structure of four films 2. Approximately 500 Si3N □ films 2 are deposited to penetrate under the gate electrodes 4.

FIGS. 4(a) to 4(c) are diagrams showing the main parts of the manufacturing process. 5 by thermal oxidation on the element-isolated p-type Si substrate 1.
An i02 film 3 is formed, and then a Si3N4 film 2 is deposited by CVD (a).

Then, the Si3N4 film 2 on the channel region is selectively etched away to expose the 5i02 film 3 (b). Thereafter, a gate electrode 4 is formed in the same manner as in the previous embodiment, and impurity ions are implanted using this as a mask to form source and drain diffusion layers 51.5□ (c).

In this embodiment as well, defective drain leakage current can be reduced as in the previous embodiment.

The present invention is not limited to the above embodiments.

For example, in the embodiment shown in FIG. 1, it is possible to replace the Si3N 1 film 2 with another material film. Depending on the selection of the film material, the effect can be obtained even if the film thickness is not thicker than that on the main part of the channel region. In the embodiment shown in FIG. 3, the 5i02 film 3 in the main part is replaced by the Si3N4 film 2.
However, in Fig. 4(b), Si
The 3N4 film 2 and the underlying 5i02 film 3 may be removed once, and then thermally oxidized again to form a 5i02 film. This is particularly effective when patterning the Si3N4 film 2 by dry etching because the underlying film 5i02 is damaged.

The pond water invention can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, by adopting a structure for the gate insulating film at the edge part of the gate electrode that is different from that on the main part of the channel region, defective drains and Reactive current can be effectively reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a MOS transistor according to one embodiment of the present invention, FIGS. 2(a) to (c) are diagrams showing the main parts of the manufacturing process, and FIG. 3 is a diagram showing a MOS transistor according to another embodiment. 4A to 4C are diagrams showing the main parts of the manufacturing process, and FIG. 5 is a diagram showing the characteristics of the MOS transistor of the embodiment in comparison with a conventional MOS transistor. 1...p-type Si substrate, 2...Si3N4 film, 3...
・5i02, 4...Gate electrode, 51.52...
Source, drain diffusion layer, 6...CV D Si
O2 membrane, 7,. 72...Source, drain'rN W
. Figure 1

Claims (4)

[Claims] (1) A MOS transistor characterized in that the gate insulating film at the edge of the gate electrode is made of a different material from the gate insulating film on the main part of the channel region. (2) The gate insulating film on the main part of the channel region is a silicon oxide film, and the gate insulating film at the edge of the gate electrode is a silicon nitride film that is thicker than the silicon oxide film.
The MOS transistor described. (3) A MOS transistor characterized in that the gate insulating film has a two-layer structure at the edge of the gate electrode. (4) The gate insulating film on the main part of the channel region is a silicon oxide film, and the gate insulating film at the edge of the gate electrode has a two-layer structure of a silicon oxide film and a silicon nitride film.
The MOS transistor described.