JPH02125621A - Bump electrode forming method for semiconductor device - Google Patents
Bump electrode forming method for semiconductor deviceInfo
- Publication number
- JPH02125621A JPH02125621A JP63279854A JP27985488A JPH02125621A JP H02125621 A JPH02125621 A JP H02125621A JP 63279854 A JP63279854 A JP 63279854A JP 27985488 A JP27985488 A JP 27985488A JP H02125621 A JPH02125621 A JP H02125621A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- resin film
- bump
- photosensitive resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims description 14
- 239000002184 metal Substances 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000011347 resin Substances 0.000 claims abstract description 22
- 229920005989 resin Polymers 0.000 claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims abstract description 20
- 230000001681 protective effect Effects 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000007747 plating Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 229920001187 thermosetting polymer Polymers 0.000 claims description 2
- 239000010949 copper Substances 0.000 abstract description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052802 copper Inorganic materials 0.000 abstract description 8
- 229920001721 polyimide Polymers 0.000 abstract description 6
- 239000009719 polyimide resin Substances 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 238000009713 electroplating Methods 0.000 abstract description 3
- 239000011229 interlayer Substances 0.000 abstract description 3
- 230000002950 deficient Effects 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 48
- 238000007796 conventional method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 241000544061 Cuculus canorus Species 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000009331 sowing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
- H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電極が設けられた半導体基板上にめっき法によ
りバンプ電極を形成する半導体装置の・バンプ電極形成
方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming bump electrodes of a semiconductor device, in which bump electrodes are formed by plating on a semiconductor substrate provided with electrodes.
ｒ従来の技術〕
１ｆ来、半導体装置のバンプ電極は、次のようにして形
成されていた。rPrior Art] Since 1f, bump electrodes of semiconductor devices have been formed in the following manner.
第２図（ａ）〜（ｄ）は従来の半導体装置のハンプ電極
形成方法を説明するための工程順に示した半導体チップ
の断面図である。FIGS. 2(a) to 2(d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a conventional method of forming a hump electrode in a semiconductor device.
まず、第２図（ａ）に示すように、回路素子が形成され
ている半導体基板１の上に眉間絶縁膜２を設け、ＡＭ電
極パッド３を形成する。カバー絶縁膜４で被覆した俺、
ホトリソグラフィ法てＡρ電極パッド３の所を開口し、
障壁金属膜５を形成する。First, as shown in FIG. 2(a), a glabellar insulating film 2 is provided on a semiconductor substrate 1 on which circuit elements are formed, and an AM electrode pad 3 is formed. I covered with cover insulating film 4,
An opening is made at the Aρ electrode pad 3 using a photolithography method,
A barrier metal film 5 is formed.
次に、第２図（ｂ）に示すように、感光性樹脂１１！
６を設け、露光現像して窓あけし、この感光性樹脂膜６
をマスクとしてめっき法により銅バンプ７と金属８から
成るバンプ電極を形成する。Next, as shown in FIG. 2(b), the photosensitive resin 11!
6 is provided, exposed and developed to open a window, and this photosensitive resin film 6
A bump electrode consisting of copper bump 7 and metal 8 is formed by plating using as a mask.
次に、第２図（ｃ）に示すように、感光性樹脂ｌ摸７を
除去した後バンプ電極７をマス、りにして障壁金属膜５
をエツチング除去する。Next, as shown in FIG. 2(c), after removing the photosensitive resin layer 7, the bump electrode 7 is used as a mask and the barrier metal film 5 is removed.
Remove by etching.
次に、第２図（ｄ）に示すように、保護膜９を形成して
、バンプ電極上部のみが露出する構造となっていた。Next, as shown in FIG. 2(d), a protective film 9 was formed so that only the upper part of the bump electrode was exposed.
上述した従来のバンプ電極形成方法は、めっきによりバ
ンプ電極を形成した後保護膜を形成するｆｉｌＩ ３ａ
になっているのて、数十μｍの高さのバンプ電極を覆う
ためには塗布膜に限られることと、障壁金属膜の障壁性
、ハンプ電極自体の変質の問題から高温の熱処理を行え
ないため、保護膜としての十分な特性が得られないとい
う欠点がある。The conventional bump electrode forming method described above involves forming a protective film after forming a bump electrode by plating.
Therefore, high-temperature heat treatment cannot be performed because coating the bump electrode with a height of several tens of micrometers is limited to a coating film, the barrier properties of the barrier metal film, and the deterioration of the hump electrode itself. Therefore, it has the disadvantage that sufficient characteristics as a protective film cannot be obtained.
また、保護膜形成後、感光性樹脂膜をマスクとして（ぺ
護膜をエツチングしてバンプ電極上部を露出させる工程
に於いて、バンプ電極の高さによる急激な段差のために
感光性樹脂膜によるパターン形成が困難であると共に工
・ソチング工程の制御性、再現性が非常に悪く、不良品
発生率が高いという欠点がある。In addition, after the protective film is formed, the photosensitive resin film is used as a mask (in the process of etching the protective film to expose the upper part of the bump electrode, the photosensitive resin film is It has the drawbacks that pattern formation is difficult, controllability and reproducibility of the machining and sowing processes are very poor, and the incidence of defective products is high.
１課題を解決するための手段〕
本発明のバンプ電極形成方法は、電極が設けられた半導
体基板上に熱硬化性樹脂の保護膜を形成ずろ工程と、前
記電極上の前記保護膜のみ感光性樹脂膜をマスクとして
選択的にテーパー形状になるようにエツチングする工程
と、前記感光性樹脂膜を除去した後障壁金属膜を堆積す
る工程と、前記障壁金属股上に形成された感光性樹脂膜
をマスクとして選択的に前記電極上にめっき法によりバ
ンプ電極を形成する工程と、前記バンプ電極をマスクと
して前記障壁金属膜をエツチングする工程とを含んで構
成される。1. Means for Solving the Problems] The bump electrode forming method of the present invention includes a step of forming a protective film of thermosetting resin on a semiconductor substrate on which an electrode is provided, and a process in which only the protective film on the electrode is photosensitive. A step of selectively etching the resin film into a tapered shape using the resin film as a mask, a step of depositing a barrier metal film after removing the photosensitive resin film, and a step of depositing the photosensitive resin film formed on the barrier metal crotch. The method includes a step of selectively forming a bump electrode on the electrode by plating as a mask, and a step of etching the barrier metal film using the bump electrode as a mask.
］実施例〕
次に、本発明の実施例について図面を参照して説明する
。]Example] Next, an example of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面Ｂ１である。FIGS. 1(a) to 1(d) are cross sections B1 of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention.
まず、第１図（ａ）に示すように、通常の方法によって
回路素子が形成されている半導体基板〕の」二に層間絶
縁膜２、Ａρ電極パッド３、カックー絶縁膜４を設け、
ＡＲ電極パッド３の上のカバー絶イ９膜４に開口部を設
ける。ここまでは従来と同ｉ二である３、
本発明においては、ポリイミド樹脂膜１１を約／、ｌ
）ｔ ｍのＩＩさに塗布し、Ｎ２雰囲気中で１５０°Ｃ
３０分の熱処理を行って硬化させる。First, as shown in FIG. 1(a), an interlayer insulating film 2, an Aρ electrode pad 3, and a cuckoo insulating film 4 are provided on a semiconductor substrate on which circuit elements are formed by a conventional method.
An opening is provided in the cover film 4 above the AR electrode pad 3. Up to this point, the process is the same as the conventional method.3. In the present invention, the polyimide resin film 11 is made of approximately /, l
)t m II and heated at 150°C in N2 atmosphere.
Heat treatment is performed for 30 minutes to harden.
次に、第１図（ｂ）に示すように、感光性樹脂膜のパタ
ーンを形成し、これをマスクとしてＡＩ’１＝ ｌｆｚ
パット３上のポリイミド樹脂膜１１をテーパー状にエツ
チングする。エツチング後怒光性樹脂膜を除去し、ポリ
イミド樹脂膜１１をＮ２雰囲気で２５０ ’Ｃ５６０分
の熱処理と３５０°Ｃ１３０分の熱処理を行う。その後
障壁金属Ｉｌｌ １２として、例えばＣｕ ／ Ｔ ｉ
ｒｐＡをそれぞれ約３００ｎｍずつスノ（ツタ法によ
り形成する。Next, as shown in FIG. 1(b), a pattern of photosensitive resin film is formed, and using this as a mask, AI'1=lfz
The polyimide resin film 11 on the pad 3 is etched into a tapered shape. After etching, the photosensitive resin film is removed, and the polyimide resin film 11 is heat treated at 250°C for 560 minutes and at 350°C for 130 minutes in an N2 atmosphere. Then as barrier metal Ill 12, for example Cu/Ti
Each rpA is formed to a thickness of about 300 nm by the vine method.
次に、第１図（ｃ）に示すように、新しく感光性樹脂１
１！１３のパターンを形成し、これをマスクとして、電
解めっき法により銅バンプ７を電流密度４ Ａ 、’
ｄ ｍ”の条件で約２０μｍの厚さにめっき一３゛ろ。Next, as shown in FIG. 1(c), a new photosensitive resin 1
1!13 pattern is formed, and using this as a mask, the copper bumps 7 are coated with a current density of 4 A,' by electrolytic plating.
Plating was carried out to a thickness of approximately 20 μm under conditions of 13 mm.
次に、銅バンプ７上に組立時のリードとの接着強度を高
めるため、同じく電解めっき法によυ金膜８を電流密度
０．４Ａ／ｄｍ２で約５ノ１ｍの厚さに形成する。Next, in order to increase the adhesion strength with the leads during assembly, a gold film 8 is formed on the copper bump 7 to a thickness of about 5 m by electrolytic plating at a current density of 0.4 A/dm2.
次に、第１図（ｄ）に示すように、感光性樹脂ＩＢ’：
１３を除去した後、銅ハンプ７をマスクとして１（９
１使金属ｌｌＡｌ２をエツチングして図に示すバンプ“
電極横道を得る。Next, as shown in FIG. 1(d), photosensitive resin IB':
After removing 13, remove 1 (9) using copper hump 7 as a mask.
1. Etching the metal llAl2 to form the bumps shown in the figure.
Get the electrode sideways.
ｒ発明の効果〕
以上説明したように、本発明は、電極が設けられた半導
体基板上にまず保護膜を形成することにより障壁金属の
障壁性、バンプ電極の変質という問題を無視して熱処理
を行えるため十分な特性の保護膜を形成できる効果がり
る。バンプ電極形成部の保護膜をエツチングする時に保
護膜にテーパーをつけることにより組立時の衝撃を水平
方向に分散させることができ、半導体基板のクラック発
生を防止することができる効果がある。障壁金属膜形成
前に保護膜により半導体基板表面が平坦１ヒされている
ことにより均一な膜厚の障壁金属膜か形成でき、バンプ
電極形成後不要部の障壁金属膜を除去する場合に均一性
良く除去できる。またカバー絶縁膜にたとえピンホール
が存在していても、障壁金属膜除去時にカバー絶縁股下
の配線がエツチングされることを防止する効果がある。[Effects of the Invention] As explained above, in the present invention, by first forming a protective film on a semiconductor substrate provided with an electrode, heat treatment can be performed while ignoring the problems of the barrier properties of the barrier metal and the deterioration of the bump electrode. Since this process can be carried out, it is possible to form a protective film with sufficient characteristics. By tapering the protective film when etching the protective film at the bump electrode forming portion, the shock during assembly can be dispersed in the horizontal direction, which has the effect of preventing cracks in the semiconductor substrate. By flattening the surface of the semiconductor substrate with a protective film before forming the barrier metal film, a barrier metal film with a uniform thickness can be formed, and uniformity can be achieved when removing unnecessary portions of the barrier metal film after forming the bump electrodes. Can be removed well. Furthermore, even if there are pinholes in the cover insulating film, there is an effect of preventing the wiring under the cover insulating crotch from being etched when the barrier metal film is removed.
第１図（ａ）〜（ｄ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図、第２図（ａ
）〜（ｄ）は従来の半導体装置のハンプ電極形成方法を
説明するための工程順に示した半導体チップの断面図で
ある。
１・・・半導体基板、２・・・層間絶縁膜、３・・・Ａ
、１電乃１パツド、４・・・カバー絶縁膜、５・・・
障壁金属膜、６ 感光性樹脂膜、７・・・銅バンプ、８
・・・金属、（１）・・保護膜、１】・・ポリイミド樹
脂膜、１２・・・障壁金属膜、１３・・・感光性樹脂膜
。1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, and FIG. 2(a)
) to (d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a conventional method for forming a hump electrode in a semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Interlayer insulating film, 3... A
, 1 Denno 1 Pad, 4...Cover insulating film, 5...
Barrier metal film, 6 Photosensitive resin film, 7... Copper bump, 8
... Metal, (1) ... Protective film, 1] ... Polyimide resin film, 12 ... Barrier metal film, 13 ... Photosensitive resin film.
Claims (1)
を形成する工程と、前記電極上の前記保護膜のみ感光性
樹脂膜をマスクとして選択的にテーパー形状になるよう
にエッチングする工程と、前記感光性樹脂膜を除去した
後障壁金属膜を堆積する工程と、前記障壁金属膜上に形
成された感光性樹脂膜をマスクとして選択的に前記電極
上にめっき法によりバンプ電極を形成する工程と、前記
バンプ電極をマスクとして前記障壁金属膜をエッチング
する工程とを含むことを特徴とする半導体装置のバンプ
電極形成方法。a step of forming a protective film of thermosetting resin on a semiconductor substrate provided with an electrode; a step of selectively etching only the protective film on the electrode into a tapered shape using the photosensitive resin film as a mask; , depositing a barrier metal film after removing the photosensitive resin film, and selectively forming bump electrodes on the electrodes by plating using the photosensitive resin film formed on the barrier metal film as a mask. A method for forming a bump electrode for a semiconductor device, the method comprising: etching the barrier metal film using the bump electrode as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63279854A JPH02125621A (en) | 1988-11-04 | 1988-11-04 | Bump electrode forming method for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63279854A JPH02125621A (en) | 1988-11-04 | 1988-11-04 | Bump electrode forming method for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02125621A true JPH02125621A (en) | 1990-05-14 |
Family
ID=17616869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63279854A Pending JPH02125621A (en) | 1988-11-04 | 1988-11-04 | Bump electrode forming method for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02125621A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6593220B1 (en) * | 2002-01-03 | 2003-07-15 | Taiwan Semiconductor Manufacturing Company | Elastomer plating mask sealed wafer level package method |
| CN102347298A (en) * | 2009-11-05 | 2012-02-08 | 台湾积体电路制造股份有限公司 | Bump structure on substrate and forming method of bump structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6325954A (en) * | 1986-07-17 | 1988-02-03 | Nec Corp | Semiconductor device and manufacture thereof |
| JPS6388847A (en) * | 1986-10-01 | 1988-04-19 | Mitsubishi Electric Corp | Manupaciure of semiconductor device |
| JPS6390156A (en) * | 1986-10-02 | 1988-04-21 | Nec Corp | Manufacture of semiconductor device |
-
1988
- 1988-11-04 JP JP63279854A patent/JPH02125621A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6325954A (en) * | 1986-07-17 | 1988-02-03 | Nec Corp | Semiconductor device and manufacture thereof |
| JPS6388847A (en) * | 1986-10-01 | 1988-04-19 | Mitsubishi Electric Corp | Manupaciure of semiconductor device |
| JPS6390156A (en) * | 1986-10-02 | 1988-04-21 | Nec Corp | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6593220B1 (en) * | 2002-01-03 | 2003-07-15 | Taiwan Semiconductor Manufacturing Company | Elastomer plating mask sealed wafer level package method |
| CN102347298A (en) * | 2009-11-05 | 2012-02-08 | 台湾积体电路制造股份有限公司 | Bump structure on substrate and forming method of bump structure |
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