JPH0210913A - Semiconductor integrated circuit logic circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction of the circuit even if any error takes place in the timing of an FF by providing a delay element, a selector connecting selectively the delay element to a terminal and an A/D converter generating a selection signal. CONSTITUTION:A voltage is given at first to a select terminal 41. A voltage V41 given to the terminal 41 is encoded by an A/D converter 31 and an H or L signal is given respectively to outputs DB0-DB3 of the converter 31. Since a voltage Vref is given to the terminal 41 as shown in figure, in H level is given to the output DB0 of the converter 31. Then the value H at the DB0 of the converter 31 is given to a select terminal S of a selector 21 and an item B is selected as the input of the selector 21. As a result, a delay element 11 is connected to a clock terminal of an FF 61 to add a delay ta of the element 11 to a data signal of the FF 61. Since the timing is varied in this way, malfunction of the circuit is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated logic circuit, and particularly to a semiconductor including a flip-flop having a configuration in which a data signal and a tally signal of the flip-flop are controlled by a common external terminal. Relating to integrated logic circuits.

[Conventional technology]

Conventionally, this type of semiconductor integrated circuit has a configuration as shown in FIG. For example, in the time chart shown in FIG.
When the data signal of the flip-flop 61 is delayed by Δt due to an increase in the fan-out of the blocks connected to the data line of the flip-flop 61 or variations in the blocks connected to the clock line, the timing relationship between the data signal and the tarok signal changes. However, the setup time of the flip-flop 61 may not be satisfied, and the circuit may malfunction.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit described above, the timing of the data signal and clock signal of the flip-flop is controlled by a common external terminal. Therefore, even if the above-mentioned timing change occurs between the data signal and clock signal of the flip-flop, the timing between the data signal and clock signal of the flip-flop cannot be changed from the external terminal, and the circuit itself cannot be changed. The drawback was that it required redesign.

[Means to solve the problem]

The semiconductor integrated logic circuit of the present invention includes a delay element connected in parallel with a data line or clock line of a flip-flop configured to control a data signal and a clock signal by a common external terminal, and a delay element connected in parallel with the data line or clock line of the flip-flop. The device includes a selector that selectively connects a line and the delay element to a clock terminal or a data terminal of the flip-flop, and an A/D converter that generates a select signal for the selector.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

The delay element 11 has a delay value ta that ensures sufficient setup time for the flip-flop 61, and the selector 21 outputs the signal at the input terminal A or B to the output terminal Y by inputting a select signal to the input terminal S. The truth table is shown in Figure 2. 31 is an A/D converter that generates a select signal for the selector 21, and 41 is an external terminal that inputs the select signal for the selector 21. A truth table of the A/D converter 31 is shown in FIG.

Next, the operation will be explained using the time chart shown in FIG.

A to C are observed waveforms observed at the points indicated by symbols in FIG. First, a certain voltage is applied to the select terminal 41. The voltage V41 applied to the select terminal 41 is encoded by the A/D converter 31 and outputs an "H" or "L" signal to the outputs DBO to DB3 of the A/D converter 31, respectively.

In the example of FIG. 2, since the voltage of V r a f is applied to the select terminal 41, the output DB of the A/D converter 31
“H” is output to O.

Next, the value "H" of DBO of the A/D converter 31 is input to the select terminal S of the selector 21, and B is selected as the input of the selector 21. As a result, delay element 1
1 is connected to the clock terminal of the flip-flop 61,
Delay element 11 is applied to the data signal of flip-flop 61.
Add the play value t1 of .

FIG. 5 is a circuit diagram of a second embodiment of the present invention, in which a delay is added to the data signal of a flip-flop using the present invention.

11.12 is a delay element, 21.22 is a selector, 3
1 is an A/D converter, 41 is an input terminal into which a select signal of the selector 21 is input, and 42 is a reference voltage input terminal of the A/D converter 31. 3 and 2 show the A/D converter 31. A truth table of the selector 21 is shown.

Next, an example of operation will be explained using the time chart of FIG. (This operation example is a case where the present invention is applied to two flip-flops.) First, a certain voltage is set at the select terminal 41, and a flip-flop to which a delay is to be added is determined.

In this operation example, the input voltage is 2 LSB (LSB=V
, -r/2) and outputs (d, c, b.

Obtain (0, 0, 1, O) as the value of a). Next, the selector 21 is given the value a as data from the selector terminal S, and selects the input based on that value. In the above example, the selector 21 receives "L" from the select terminal S and selects the input terminal A.

As a result, the delay element 11 is connected to the data terminal of the flip-flop processor 1. In this example, no delay value is added to the data signal of the flip-flop 61.

The selector 22 operates in the same way, and in the above example, the value of d ゛H
", and the input terminal B of the selector 22 is selected according to this value. As a result, the delay element 12 is connected to the data terminal of the flip-flop 62, and the delay value ja2 of the delay element 12 is applied to the data signal of the flip-flop 62. can be added.

In this embodiment, the select signal for selecting the flip-flop that provides the delay is obtained by a signal obtained by A/D converting the analog value, so the number of terminals for inputting the select signal is only one, and - Once the voltage of the select terminal is determined in advance, a delay can be added to the selected flip-flop using the determined voltage. Furthermore, in this embodiment, since a delay is added to the data signal, it is possible to provide a margin for hold time.

〔Effect of the invention〕

As explained above, the present invention also applies to a flip-flop having a configuration in which a data signal and a clock signal in a semiconductor integrated circuit are controlled by a common external terminal.
A delay can be added to the data signal or clock signal from an external terminal. Therefore, even if an error occurs in the timing of a flip-flop in the circuit, the timing can be changed from an external terminal to prevent malfunction of the circuit. In addition, since a signal obtained by A/D converting an analog value is used as a signal for selecting a flip-flop to which a delay is added, a voltage determined by − degrees can be set externally to the select terminal of the present invention. For example, this has the effect of operating the flip-flop under conditions to which a delay determined thereafter is added.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a truth table for the selector shown in FIG. 1, and FIG. 3 is a truth table for the A/D converter shown in FIG. 1. 4 is a time chart showing the operation of FIG. 1, FIG. 5 is a circuit diagram showing the second embodiment of the present invention, FIG. 6 is a time chart showing the operation of the circuit shown in FIG. 5, and FIG. 8 is a circuit diagram showing a conventional example, and FIG. 8 is a time chart showing the operation of FIG. 7. 11.12...Delay element, 21. ．． 22... Selector, 31... 4-Bit A/D converter, 41... Input terminal for inputting data for selecting a flip-flop that provides a delay as an analog signal, 42... V of 31
r e r input terminal, 91 to 94...internal circuit, 5
External terminal that operates 1゜52...61.62, a~
I]...Waveform at each observation point in the circuit diagram, t...
・Delay value of 11, ta, ...Delay value of 12,
ts...Set-up time, t)+2...Hold time, Δt...Delay value increment due to variation or fan-out, Vr@f...Reference voltage.

Claims (1)

[Claims] A delay element connected in parallel with a data line or a clock line of a flip-flop configured to control a data signal and a clock signal by a common external terminal; 1. A semiconductor integrated logic circuit comprising: a selector selectively connected to a clock terminal or a data terminal of a circuit; and an A/D converter generating a select signal for the selector.