JPH0194477A - Signal processor - Google Patents

Abstract

PURPOSE:To perform discrete cosine conversion in a short time by providing a multiplicand data storing register file, an adder subtracter input register file and an accumulation register file at the circuit constitution of a multiplication-accumulation-type. CONSTITUTION:The title processor is equipped with a register file consisting of 8 accumulation registers 13-20, and the access of a data memory 2 at every butterfly stage is made unnecessary. Further, adder-subtracter input register files 8-11 to prepare for the 2-input of an adder-subtracter is provided, data are directly transferred from the data memory 2 to them, and a bus neck at the time of a memory access is eliminated. In addition, multiplicand register files 4-6 are provided for the one-input of a multiplier 7, paths to directly store the outputs of the adder-subtracter 12 are provided at them, and the data between the different butterfly stages are efficiently exchanged. Thus, the time necessary for the discrete cosine conversion operation is reduced.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention provides a small-scale [prior art] algorithm for speeding up discrete cosine transform used in image encoding, etc. When an N-dimensional vector is used, CF) = 2/ N(AN)(f)(tl
It can be expressed as However, (AN)=(c(k)cos(2j+l)kπ/2N)
;j=to=LL...5(Nt) However, C(k)-"1/2'/"-...-f o
r k=0c(k)=1・・・・・・・・・・・・・
...for k=1.2. ..., N-1.

An algorithm for quickly implementing the discrete cosine transform operation described above was published in 1977 by the IEEE.
Published by Transactions on Komienikesi! 1
Transactions on Co-paper by W, H, Chen et al.
Discrete cosine transformer 7 ohm (A Fa
st Computational Algo-ri
thm for the Discrete Co51
For example, it can be seen that the above sine conversion requires 26 additions/subtractions and 16 multiplications.

This means that a processor that has one multiplier and one adder and can perform both multiplication and addition/subtraction in each machine cycle can perform 8-point high-speed discrete cosine transformation in 26 steps by performing multiplication and addition/subtraction simultaneously. Theoretically possible.

[Problem that the invention seeks to solve]

In order to realize this operation with a multiplication-accumulation type circuit configuration that has been adopted by many signal processors in the past, that is, a circuit configuration suitable for performing addition and subtraction between the accumulation register output and the multiplier Izuku, the following steps are required: The problem shown arises.

From the signal flow graph in Figure 2, the 8-point discrete cosine transform consists of 4 butterfly stages (some are 3 stages), but if each stage is stored in the data memory, 56 memory accesses are required. , more than 26 steps are required for the calculation. Also, out of a total of 133 butterflies, there are 8 butterflies that only perform addition and subtraction without multiplication.
Addition of the contents of the accumulation register and the multiplier output is difficult to realize the 8-point cosine transformation in the minimum steps using only a suitable circuit configuration.

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal processor that can perform discrete cosine transformation in a short time while having a multiplication-accumulation type circuit configuration.

[Problem t-Means for solving]

A signal processor having a multiply-accumulate circuit configuration according to the present invention includes a data bus, a read/write data memory connected to the data bus, a multiplicand data storage register file for reading and storing, and an output of the coefficient memory. a multiplier for multiplying the output of the multiplicand data storage register file by the output of the multiplier data storage register; and a first adder/subtractor input register file for storing the output of the data memory. , select one of the second adder/subtractor input register file storing the output of the data memory, the output of the first adder/subtractor input register file, and the second processing data as the first input; The output of the second adder/subtractor input register file, the output of the multiplier, and the collapse of data on the data bus are selected as second inputs, and
and the second input to obtain the first
an adder/subtracter that outputs processed data; an accumulation register file that stores the output of the multiplier and the output of the adder/subtracter, outputs the second processed data, and outputs data to the data bus; The control unit includes at least a control unit that controls each of the above-mentioned components.

・I [Operation/Principle] In the signal processor of the present invention, in a multiplication-accumulation type circuit configuration that can efficiently perform product-sum operations, first, by providing a register file consisting of eight accumulation registers, each butterfly stage is In addition to this accumulation register file, an adder/subtracter input register file is provided to prepare two adders/subtracters, and data can be directly transferred from the data memory to this register file. By eliminating the path neck when performing memory access, and by creating a multiplicand register file for one input of the multiplier and providing a path to which the output of the adder/subtractor can be directly stored, different patterns 72
The data receiving and passing between the two stages was made more efficient. This makes it possible, for example, to continuously perform 26 additions and subtractions in an 8-point discrete cosine transform.
At the same time, 16 multiplications can be performed simultaneously while addition and subtraction are being performed.

〔Example〕

The present invention will be described in detail below using the drawings.

Figure t41 is a block diagram showing the configuration of a signal processor that is an embodiment of the present invention. As shown in the figure, this signal processor includes a data bus 1, a data memory 2
, coefficient memory 3, first multiplicand input register 4. Second multiplicand input register 5, multiplier input register 6, multiplier 7
, first adder/subtractor input register 8,! 2 adder/subtractor input register 9, third adder/subtractor input register 101. ig
4 adder/subtractor input register 11, adder/subtractor 12, first accumulator.

register 13, second accumulation register 14. Third accumulation register 15, fourth accumulation register 16, fifth accumulation register 17, sixth accumulation register 18, seventh accumulation register 19, g8 accumulation register 20, and control section Consists of 21. In the above configuration, the data bus 1 is a storage circuit that can select the output of an accumulation register file, which will be described later, and write data on a data memory or tabus 1, which will be described later.

The coefficient memory 3 is a read-only storage circuit that stores coefficients used in discrete cosine transform. Either the first multiplicand input register 4 or the second multiplicand input register 5 can select and store either the output of the data memory 2 or the output of the adder/subtractor 12, which will be described later, within one instruction. can. The multiplier input register 6 stores the output of the coefficient memory 3. The 0 multiplier 7 selects either the output of the first multiplicand input register 4 or the output of the second multiplicand input register 5 as the multiplicand input, and inputs the multiplicand. This is a pipeline multiplier that performs multiplication using the output of the input register 6 as a multiplier input, and outputs the multiplication result two instructions after the input is set. The first addition/subtraction input register 8 and the second addition/subtraction input register 9 are the register 7
Either one of the tails can store the output of the data memory 2 in the 1inst 2 sink. The third adder/subtractor input register 10 and the adder/subtractor input register 11 of 71i4 constitute a register file, and either one can store the output of the data memory 2 within one instruction. The adder/subtractor 12 is the output of either the first adder/subtractor input register 8 or the second adder/subtracter input register 9, or the first accumulation register 1 to be described later.
One of the outputs of the accumulation register file consisting of the third to eighth accumulation registers 20 is selected as the input of the first adder/subtractor, and the output of the third adder/subtractor input register 10 and the fourth adder/subtractor input register 11 is selected. Either one of the outputs of the output 1 multiplier 7 or the data on the data bus is selected as the input of the second force a subtracter, and the addition and subtraction results are output after executing the l instruction. This is a pipeline adder/subtractor. First accumulation register 13, g2 accumulation register 14, third accumulation register 15. Fourth accumulation register 1
6% fifth accumulation register 17, sixth accumulation register 18
゜The seventh accumulation register 19 and the eighth accumulation register 20 constitute a register file, and the adder/subtractor 12. QJ force and the output Tz' of the multiplier 7 can each be stored in different accumulation registers.
It consists of a boat mesori.

The control unit 21 outputs control signals for controlling each of the above-mentioned components according to control commands stored in advance.

Next, by using a signal processor having the above configuration, it is confirmed that the 8-point discrete cosine transformation of each of the first 8-dimensional vector and the second 8-dimensional vector can be executed every 26 steps. Figure 3 (5),
However, this will be explained using

However, each variable used in the following explanation is fO, fl, F2 . F3. F4. F5゜F5
．． F7 is an input vector, gO, gl, K2. K3. K4
゜K5. K6. K7 is @1 stage butterfly output, g'5*
g'6 is! Variables in the 22nd stage, hO, hl, h2. h3. h
4. h5゜h6. h7 is the second stage butterfly output, hIo
, hFx is the third stage intermediate variable, K4. K5. K6. K7
are the third stage butterfly outputs, FO, Fl, F2. F3. F
4. F5°F6. F7 outputs the output vector. Also, coefficient C4 is cos (4r/16), and s6 is 5in (6
r/16), s2 is 5in (2r/16), sl is s
in(π/16), S5 is sin(5ff/16), s
-7 is sin (-7r/16), c-3 is cos(-3
π/16), C1 is cos (π/16), C3 is C0
8 (3π/16), C5 is cos (5π/16), C7
are cos(7π/16) respectively. In addition, in FIGS. 3(5) and (B), RAM is data memory 4, digit memory lJ3, Pl is first adder input register 8, F2 is second adder input register 9, and Ql is Third adder input register 10. Q2 is the fourth adder input register 11, K1 is the first multiplicand input register 4, K2 is the second multiplicand input register 5, and L is the multiplier input register 6.
, A is the output % of the adder 12, M1 is the output of the multiplier 7 with Klt-multiplicand, M2 is the output of the multiplier 7 with 2 as the multiplicand, WHO is the @1 accumulation register 13, and WfLl is the second Accumulation register 14. WB2 is the third accumulation register 15, WK3 is the fourth accumulation register 16. WfL4 is the fifth accumulation register 17, WK5 is the accumulation register 1 of M6
8.WK6 is the seventh accumulation register 19, and Naecho is the eighth accumulation register 20.

First, in the first step, input data fOfc stored in the data memory 2 is transferred to the first adder input register 8.

, in the second step, the input data f7 stored in the data memory 2 is transferred to the adder input register 1° of @3.

In the third step, the input data fl stored in the data memory 2 is transferred to the second adder input register 9. Further, the output of the first adder input register 8 is selected as the first input of the adder/subtracter 12, and the output of the third adder input register 10 is selected as the second input of the adder/subtracter 12. Perform addition of the input and the second input.

In the fourth step, the input data f6 stored in the data memory 2 is transferred to the fourth adder input register 11.

Further, the output of the first adder input register 8 is selected as the first input of the adder/subtracter 12, and the output of the third adder input register 10 is selected as the second input of the adder/subtracter 12. From input.

In the fifth step, the input data f21c stored in the data memory 2 is transferred to the adder input register 8 of $1. Also, the output of the second adder input register 9 is selected as the first input of the adder/subtractor 12, the output of the fourth adder input register 11 is selected as the second input of the adder/subtracter 12, and the output of the fourth adder input register 9 is selected as the second input of the adder/subtracter 12. Addition of the input and the second input is performed. The addition result g7 in the previous step is stored in the eighth accumulation register 20.

In the sixth step, the input data f5 stored in the data memory 2 is transferred to the third adder input register 10.

The output of the second adder input register 9 is selected as the first input of the adder/subtracter 12, and the output of the fourth adder input register 11 is selected as the second input of the adder/subtracter 12. The second input is subtracted from the input. The addition result glt in the previous step is stored in the second accumulation register 14.

In the seventh step, the input data f3t stored in the data memory 2 is transferred to the second adder input register 9.

Further, the output of the first adder input register 8 is selected as the first input of the adder/subtracter 12.

The output of the third adder input register 10 is selected as the second input of the adder/subtractor 12, and the first input and the second input are added. The addition result g6 in the previous step is
, and stores the coefficient C4 stored in the coefficient memory 3 in the multiplicand input register 6 to start multiplication between the output of the first multiplicand input register 4 and the output of the multiplier input register 6. do.

In the eighth step, the input data f4 stored in the data memory 2 is transferred to the fourth adder input register 11.

Further, the output of the first adder input register 8 is selected as the first input of the adder/subtracter 12.

The output of the third adder input register 10 is selected as the second input of the adder/subtractor 12, and the second input is subtracted from the input of fal. The addition result g2 in the previous step is stored in the third accumulation register 15.

In the ninth step, the output of the second adder input register 9 is selected as the first input of the adder/subtracter 12;
As the second input of 2! $4 adder input register 11
selects the output of and performs addition of the first input and the second input. The addition result g5 in the previous step is stored in the multiplicand input register 4 of Kl, the coefficient C4 stored in the coefficient memory 3 is stored in the multiplier input register 6, and the output of the first multiplicand input register 4 and the multiplier input register 6 are output. Begin multiplication between . Further, the multiplication result g'6 whose input was specified two steps ago is stored in the seventh accumulation register 19.

In the tenth step, the output of the second adder input register 9 is selected as the input of the adder/subtracter 12081, and the output of the fourth adder input register 11 is selected as the second input of the adder/subtracter 12.
select the output of and subtract the second input from the first input. The addition result g3 in the previous step is applied to the fourth accumulation register 16 to select the output of the first accumulation register 13, and the output of the fourth accumulation register 16 is selected as the second input of the adder/subtractor 12. Then, the first input and the second input are added. Addition result in previous step g4t@
The multiplication result gIs, which was input two steps earlier, is stored in the sixth accumulation register 17.
Store in 8.

In the twelfth step, the output of the first accumulation register 13 is selected as the first input of the adder/subtractor 12.

a fourth accumulation register 1 as the second input of the adder/subtractor 12;
6 is selected and the second input is subtracted from the first input. The addition result ho in the previous step is stored in the first multiplicand manual register 4.

The coefficient C4 stored in the coefficient memory 3 is stored in the multiplier input register 6, and multiplication between the output of the first multiplicand input register 4 and the output of the multiplier input register 6 is started.

In the thirteenth step, the first input star 15 of the adder/subtractor 12
The output of gt is selected and the input of gt and the second input are added. The addition result in the previous step h3t' is stored in the second multiplicand input register 5, and the coefficient @6t stored in the coefficient memory 3 is stored in the multiplier input register 4 and the output of the second multiplicand input register 4 and the multiplier input register 6. Start multiplication between .

In the fourteenth step, the output of the second accumulation register 14 is selected as the input of Kl of the adder/subtractor 12, and
The output of the third accumulation register 15 is selected as the second input of , and the second input is subtracted from the input of @1. The addition result h1 in the previous step is stored in the multiplicand input register 4 of #I, 1.

The coefficient 04 stored in the coefficient memory 3 is stored in the multiplier input register 6, and multiplication between the output of the first multiplicand input register 4 and the output of the multiplier input register 6 is started. The multiplication result h I o whose input was specified two steps ago is stored in the first accumulation register 13 .

In the fifteenth step, the output of the seventh accumulation register 19 is selected as the first input of the adder/subtracter 12, and the adder/subtracter 12
The output of the sixth accumulation register 1B is selected as the second input, and the input of L2 is subtracted from the first input. The addition result h2i in the previous step is stored in the first multiplicand input register 4, and the coefficient 52 stored in the coefficient memory 3 is stored in the multiplier input register 6, and the output of the first multiplicand input register 4 and the multiplier input register 6 are output. Begin multiplication between . Also, the multiplication result F6' that specified the input two steps ago
is stored in the fourth accumulation register 16.

In the 16th step, the output 'kA' of the 47 accumulation registers 19 is selected as the input value 1 of the adder/subtractor 12.

the sixth accumulation register 1 as the second input of the adder/subtractor 12;
The output of 9 is selected and the first input and the input of 42 are added. The addition result in the previous step h5'ft is stored in the sixth accumulation register 18, and the multiplication result h'1 whose input was specified two steps ago t-the second accumulation register 1
Store in 4.

In the seventeenth step, the output of the fifth accumulation register 17 is selected as the first input of the adder/subtractor 12, the output of the star 18 is selected, and the first input and the second input are added. The addition result h6 in the previous step is stored in the seventh accumulation register 19, the coefficient 36 stored in the coefficient memory 3 is stored in the multiplier input register 6, and the first multiplicand input register 4 output and the multiplier input register 6 output Start multiplication between . Also, the multiplication result F2 that specified the input two steps ago
' is stored in the third accumulation register 15.

In the 18th step, the output of the fifth accumulation register 17 is selected as the first input of the adder/subtracter 12, and the adder/subtracter 12
The output of the sixth accumulation register 18 is selected as the second input of , and the second input is subtracted from the first input. The addition result i4 in the previous step is stored in the first multiplicand input register 4, and multiplication between the output of the second multiplicand input register 5 and the output of the multiplier input register 6 is started.

In the 19th step, the output of the fourth accumulation register 16 is selected as the first input of the adder/subtracter 12, and the adder/subtracter 12
The output of the multiplier 7 is used as the second input. The addition result i5 in the previous step is stored in the second multiplicand input register 5, and the coefficient 31 stored in the coefficient memory 3 is stored in the multiplier input register 6, so that the 41 multiplicand input register 4 output and the multiplicand input register 6 output Begin multiplication between .

In the 20th step, the first input of the adder/subtractor 12 selects the output of the accumulation register 15 of f43, and
The output of the multiplier 7 is selected as the second input of the multiplier 2, and the first input and the second input are added. Addition result F6t in the previous step - Store in the fourth accumulation register 16,
The 55ft coefficient stored in the coefficient memory 3 is stored in the multiplier input register 6 to start multiplication between the output of the second multiplicand input register 5 and the output of the multiplier input register 6.

In the 21st step, the second
The input data fO of the th input vector is transferred to the first adder input register 8. Also, the output of the eighth accumulation register 20 is selected as the first input of the adder/subtractor 12, and the output of the seventh accumulation register 20 is selected as the input of 42 of the adder/subtracter 12, so that the output of the seventh accumulation register 20 is selected as the first input. Addition with the second input is performed. The addition result F2 in the previous step is stored in the third accumulation register 15, the coefficient s-7 stored in the coefficient memory 3 is stored in the multiplier input register 6, and the output of the first multiplicand input register 4 and the multiplier input register are stored. 6 starts multiplication with output. Also, the multiplication result Fl' that specified the input two steps ago is aX
5 is stored in the accumulation register 17.

In the 22nd step, 'g' stored in data memory 2
Input data f7i of the second input vector is transferred to the third adder input register 10. The output of the eighth accumulation register 20 is selected as the first input of the adder/subtractor 12, and the output of the seventh accumulation register 19 is selected as the second input of the adder/subtractor 12, so that the first input to Performs subtraction of 2 inputs. The addition result 17 in the previous step is stored in the first multiplicand input register 4, and the coefficient c-3 stored in the coefficient memory 3 is stored in the multiplier input register 6 to obtain the multiplication result F5' with the input designated as the second previous step. is stored in the sixth accumulation register 18.

In the 23rd step, the second
The input data f1 of the th input vector is transferred to the second adder input register 10. The output of the first accumulation register 13 is selected as the first input of the adder/subtractor 12, and the output of the second accumulation register 14 is selected as the second input of the adder/subtractor 12, so that the first input and the Addition of 2 inputs is performed.

Addition result 16t in the previous step - coefficient C stored in the second multiplicand input register 5 and stored in the coefficient memory 3
1 is stored in the multiplier input register 6 to start multiplication between the first multiplicand input register 4 output and the multiplier input register 6 output. Further, the multiplication result p7F whose input was specified two steps ago is stored in the eighth accumulation register 20.

In the 24th step, the sg stored in the data memory 2
Select the output of the star 13 as the input data f6 of the second input vector, select the output of the second accumulation register 13 as the second input of the adder/subtractor 12, and transfer the input data from the first input to the second input. Perform subtraction.

The addition result FO in the previous step is stored in the first accumulation register 13, the coefficient C3 stored in the coefficient memory 3 is stored in the multiplier input register 6, and the second multiplicand input register 5 output and the multiplier input register 6 output Start multiplication between . Also, the multiplication result F3' with the input specified two steps before
is stored in the seventh accumulation register 19.

In the twenty-fifth step, the output of the fifth accumulation register 17 is selected as the first input of the adder/subtracter 12, and the adder/subtracter 12
The output of the multiplier 7 is selected as the second input, and the first and second inputs are added together. The addition result F4 in the previous step is stored in the second accumulation register 14, and the coefficient C5 stored in the coefficient memory 3 is stored in the multiplier input register 6 to output the second multiplicand input register 5 and the multiplier input register 6. Start multiplication between . Also, the value of the first accumulation register FOf:? -7 Stored in data memory 2
′

In the 26th step, the output of the seventh accumulation register 19 is selected as the input @1 of the adder/subtractor 12.

The output of the multiplier 7 is selected as the second input of the adder/subtractor 12 and the first input and the second input are added.The addition result F1 in the previous step is stored in the fifth accumulation register 17. , stores the coefficient c7 stored in the coefficient memory 3 in the multiplier input register 6, and starts multiplication between the output of the first multiplicand input register 4 and the output of the multiplier input register 6. Further, the value F4 of the second accumulation register is stored in the data memory 2.

In the 27th step, the output of the sixth accumulation register 18 is selected as the first input of the adder/subtractor 12, and the output of the adder/subtractor 12 is selected.
The output of the multiplier 7 is selected as the second input, and the first and second inputs are added together. The addition result F3 in the previous step is stored in the seventh accumulation register 19. Also, the value F2fc of the third accumulation register is stored in the data memory 2.

The output of the eighth accumulation register 20 is selected as the signal, the output of the multiplier 7 is selected as the second input of the adder/subtractor 12, and the input of IIEl and the second input are added. The addition result F5 in the previous step is stored in the sixth accumulation register 18. Il again! The value F6 of the accumulation register J4 is stored in the data memory 2.

In the 29th step, the adder/subtracter 12 performs the first operation for the 8-point discrete cosine transform of the second input vector.
selects the output of the first adder input register 8 as the first input of the adder/subtractor 12 and selects the output of the third adder input register 10 as the second input of the adder/subtractor 12 to connect the first input and gX
Addition of 2 inputs is performed. The addition result F7t in the previous step is stored in the eighth accumulation register 20. Maku #I
The value F1t of the accumulation register 5 is stored in the data memory 2.

In the 30th step, the output of the first adder input register 8 is selected as the first input of the adder/subtractor 12, and the output of the third adder input register 10 is selected as the second input of the adder/subtractor 12.
selects the output of and stores the first input addition result gO in the first accumulation register 3. Also, the value F7 of the eighth accumulation register is stored in the data memory 2.

In the 31st step, the second
The input data f2 of the th input vector is transferred to the first adder input register 8. 1+ select the output of the second adder input register 9 as the first input of the adder/subtracter 12;
The output of the fourth adder input register 1 is selected as the second input of the adder/subtractor 12, and the first input and the second input are added. The addition result g7 in the previous step is
is stored in the accumulation register 20 of.

In the 32nd step, the second
Transfer the input data f5 of the th input vector to the third adder input register O. Also, the output of the second adder input register 9 is selected as the first input of the adder/subtracter 12, the output of the fourth adder input register 1 is selected as the second input of the adder/subtracter 12, and the output of the fourth adder input register 1 is selected as the second input of the adder/subtracter 12. Subtract the second input from the input. The addition result g1 in the previous step is stored in the second accumulation register 14.

In the 33rd step, the second
The input data f3 of the th input vector is transferred to the second power multiplier input register 9. Further, the output of the first adder input register 8 is selected as the first input of the adder/subtracter 12, and the output of the third adder input register 10 is selected as the second input of the adder/subtracter 12. Addition of the input and the input of J2 is performed. The addition result g6 in the previous step is stored in the first multiplicand input register 4, and the coefficient C4 stored in the coefficient memory 3 is stored in the multiplier input register 6.
The multiplication between the multiplicand input register 4 output and the multiplier input register 6 output is started.

In the 34th step 9, the second
Input data f41 of the th input vector is transferred to the fourth adder input register 11. Also, the output of the first adder input register 8 is selected as the first input of the adder/subtractor 12, and the output of the adder taito register lO of 1=73 is selected as the second input of the adder/subtracter 12. The second input is subtracted from the value of . Addition result g2 in the previous step
is stored in the third accumulation register 15.

In the thirty-fifth step, the output of the second adder input register 11 is selected as the first input of the adder/subtracter 12, and the output of the fourth adder input register 11 is selected as the second input of the adder/subtracter 12.
selects the output of and performs addition of the first input and the second input. The addition result g5t'' in the previous step is stored in the first multiplicand input register 4, the coefficient C4 stored in the coefficient memory 3 is stored in the multiplier input register 6, and the output of the first multiplicand input register 4 and the multiplier input register are 6 output is started. Also, the multiplication result g'6, which specified the input two steps ago, is stored in the seventh accumulation register 19.

Also, the value F5 of the sixth accumulation register is stored in the data memory 2.

In the 36th step, the output of the second adder input register 9 is selected as the @10 input of the adder/subtracter 12, and the output of the fourth adder input register 11 is selected as the second input of the adder/subtracter 12.
The second input is subtracted from the first input by selecting the output of . Also, the value F3t of the seventh accumulation register is stored in the data memory 2.

In the 37th step, the output of the first accumulation register 13 is selected as the first input of the adder/subtracter 12, and the adder/subtracter 12
The output of the fourth accumulation register 16 is selected as the second input to perform addition of the first input and the second input. Addition result g4t in previous step - fifth accumulation register 1
7, and the multiplication result g'5 whose input was specified two steps ago is stored in the sixth accumulation register 18.

As shown above, the addition/subtraction processing for the first input vector starts from the third step, whereas the addition/subtraction processing for the second input vector starts from the 29th step.
The process can be started without causing any conflict with the process for the first input vector. Similarly, the addition/subtraction processing for the third and subsequent input vectors can be performed successively every 26 steps without causing conflicts, so it is possible to effectively perform the 8-point discrete cosine transform in 26 steps. I can say that.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, by adding special functions to a signal processor having a multiplication-accumulation type circuit configuration, discrete cosine transform that is repeatedly executed in two-dimensional cosine transform, etc. It can be executed with the theoretical minimum number of steps, and the time required to perform discrete cosine transform operations on images and the like can be shortened.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the overall configuration of a signal processor according to the present invention, Fig. 2 is a diagram showing a signal 70 graph of 8-point discrete cosine transform, Fig. 3 (5), @ indicates 8 points according to the present invention. It is a figure showing each step of discrete cosine processing. In the figure, l... data bus, 2...
・Data memory, 3...Coefficient memory, 4...
...First multiplicand 6...Multiplicand input register,
7... Multiplier, 8... First adder/subtractor input register, 9... Second adder/subtractor input register, 10... Third adder/subtractor input register,
11...Fourth adder/subtractor input register, 12.
...Adder/subtractor, 13...First accumulation register, 14...Second accumulation register, 15...
...Third accumulation register, 16...Fourth accumulation register, 17...Fifth accumulation register,
18...6th accumulation register, 19...
- Seventh accumulation register, 20... Eighth accumulation register, 21... Control unit. Agent Patent Attorney Oto Uchihara

Claims (1)

[Claims] In a signal processor having a multiplication-accumulation type circuit configuration, a data bus, a readable and writable data memory connected to the data bus, a read-only coefficient memory, and an output of the data memory or first processing data a multiplicand data storage register file that selects and stores one of the multiplicand data storage registers, a multiplier data storage register that stores the output of the coefficient memory, and a multiplication of the output of the multiplicand data storage register file and the output of the multiplier data storage register. a first adder/subtractor input register file for storing the output of the data memory, a second adder/subtractor input register file for storing the output of the data memory, and the first adder/subtractor input register file. The output of the second adder/subtractor input register file, the output of the multiplier, and the data on the data bus are selected as the first input. an adder/subtractor that outputs the first processed data by performing addition/subtraction between the first input and the second input, and storing the output of the multiplier and the output of the adder/subtractor; A signal processor comprising at least an accumulation register file that outputs the second processing data and outputs data to the data bus, and a control section that controls each of the aforementioned components. .