JPH0193172A - Thin-film transistor - Google Patents
Thin-film transistorInfo
- Publication number
- JPH0193172A JPH0193172A JP25103687A JP25103687A JPH0193172A JP H0193172 A JPH0193172 A JP H0193172A JP 25103687 A JP25103687 A JP 25103687A JP 25103687 A JP25103687 A JP 25103687A JP H0193172 A JPH0193172 A JP H0193172A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- gate insulating
- gate
- thin film
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims description 32
- 238000004544 sputter deposition Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 8
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000010408 film Substances 0.000 claims description 65
- 239000007789 gas Substances 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 12
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 3
- 229910001882 dioxygen Inorganic materials 0.000 claims description 3
- 229910004613 CdTe Inorganic materials 0.000 claims description 2
- 229910052786 argon Inorganic materials 0.000 claims description 2
- 239000006104 solid solution Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052593 corundum Inorganic materials 0.000 abstract description 2
- 239000011521 glass Substances 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 238000001755 magnetron sputter deposition Methods 0.000 abstract description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract description 2
- 238000003949 trap density measurement Methods 0.000 description 8
- 239000000203 mixture Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010893 electron trap Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Formation Of Insulating Films (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
この発明は、薄膜トランジスタに関し、特にゲート絶縁
膜中の電子トラップに起因する薄膜トランジスタ特性の
不安定性を改良した薄膜トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to thin film transistors, and more particularly to a thin film transistor in which instability in thin film transistor characteristics caused by electron traps in a gate insulating film is improved.
従来の技術
薄膜トランジスタは、ソース・ドレイン電極間の半導体
の電気電導度を半導体と接する絶縁膜を介して設けられ
た第三の電極（ゲート電極）に印加する電圧によって制
御するいわゆる電界効果型トランジスタとして知られて
いる。従来薄膜トランジスタは、大面積竪渡ってスイッ
チングアレーを形成し易い点、あるいは材料が安価なた
め低コストになり得るなどの魚でイメージセンサあるい
は液晶やＥＬ表示装置等の駆動回路やスイッチングアレ
ーを目的に研究が続けられている。このような薄膜トラ
ンジスタにおいて、最も重要な点は、素子特性の変動が
な（長時間にわたって安定に動作することである。Conventional technology Thin film transistors are so-called field-effect transistors in which the electrical conductivity of a semiconductor between source and drain electrodes is controlled by a voltage applied to a third electrode (gate electrode) provided through an insulating film in contact with the semiconductor. Are known. Conventionally, thin film transistors have been used for the purpose of driving circuits and switching arrays for image sensors, liquid crystals, EL display devices, etc. because they can be easily formed into switching arrays over a large vertical area, and because the materials are cheap, they can be made at low cost. Research continues. The most important point in such thin film transistors is that there is no variation in device characteristics (stable operation over a long period of time).
薄膜トランジスタ特性の経時変化の原因としては、半導
体膜中あるいは半導体膜とゲート絶縁膜との界面あるい
はゲート絶縁膜中にあって電子を捕獲することのできる
電荷トラップによるものと考えられている。この内、ゲ
ート絶縁膜中に存在する電荷トラップは他の電荷トラッ
プに比べてその数が多く、また、絶縁膜中の伝導度が低
いため通常長い緩和時間を必要とすることから、薄膜ト
ランジスタ特性の長期的な経時変化の主たる原因である
と考えられている。絶縁膜中に電荷トラップが多く存在
したり、絶縁膜のリーク電流が大きいと、半導体膜と絶
縁膜との界面に形成されたチャネル中を移動する電子が
絶縁膜中に引き込まれ、電荷トラップに捕獲され、実効
的なゲート電圧が変化してドレイン電流が変動したりす
る。以上の点から安定なトランジスタ特性を有する素子
を実現するには、電荷トラップが少なくり−゛り電流の
少ない絶縁膜をゲート絶縁膜として用いることが望まし
い。The cause of changes in thin film transistor characteristics over time is thought to be due to charge traps that can trap electrons in the semiconductor film, at the interface between the semiconductor film and the gate insulating film, or in the gate insulating film. Of these, the number of charge traps that exist in the gate insulating film is larger than other charge traps, and because the conductivity in the insulating film is low, it usually requires a long relaxation time, which affects the characteristics of thin film transistors. It is thought to be the main cause of long-term changes over time. If there are many charge traps in the insulating film or the leakage current in the insulating film is large, electrons moving in the channel formed at the interface between the semiconductor film and the insulating film are drawn into the insulating film and become charge traps. This causes the effective gate voltage to change and the drain current to fluctuate. From the above points, in order to realize a device with stable transistor characteristics, it is desirable to use an insulating film with fewer charge traps and a lower current as the gate insulating film.
従来、上記薄膜トランジスタのゲート絶縁膜としては、
スパッタ法により形成したＡｌｔｏｓ、Ｔａ５ｋｓ、Ｓ
ｔｏｗ、５ｉａＮａ等の薄膜が用いられていた。Conventionally, the gate insulating film of the above thin film transistor is
Altos, Ta5ks, S formed by sputtering method
Thin films such as tow and 5iaNa were used.
発明が解決しようとする問題点
薄膜トランジスタのゲート絶縁膜としてＡｌ２Ｏ３やＴ
ａ２０ｇあるいはそれらの複合絶縁膜等をスパッタ法に
より形成する場合、一般にスパッタ中にプラズマ粒子が
膜に衝突して欠陥を生成して、これが電荷トラップとな
り経時変化が太き（なるという問題があった。Problems to be Solved by the Invention Al2O3 and T are used as gate insulating films of thin film transistors.
When forming a20g or their composite insulating films by sputtering, there is generally a problem that plasma particles collide with the film during sputtering and generate defects, which become charge traps and increase the change over time. .
また、スパッタ時の雰囲気ガスの圧力やパワー密度等の
各種パラメータと電荷トラップとの相関は今までに明ら
かにされておらず、上記した理由や、組成比が化学量論
的組成からずれて酸素欠陥ができて、それが電荷トラッ
プとなるばかりでなくリーク電流が増加する原因となっ
ていた。In addition, the correlation between charge traps and various parameters such as the pressure and power density of the atmospheric gas during sputtering has not been clarified so far, and the reason for the above reasons and the fact that the composition ratio deviates from the stoichiometric composition and oxygen Defects were formed, which not only became charge traps but also caused an increase in leakage current.
以上のような理由から、従来のスパッタ法により形成し
たゲート絶縁膜を用いた薄膜トランジスタでは経時変化
が大きく、ゲートリーク電流が太き（、再現性に乏しい
ものしか得られなかった。For the above-mentioned reasons, thin film transistors using gate insulating films formed by conventional sputtering methods show large changes over time, large gate leakage currents (and poor reproducibility).
そこで、本発明は、以上のような問題点を解決して、長
期にわたり安定した特性を有し、再現性よく製造できる
薄膜トランジスタを提供することを目的としている。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a thin film transistor that has stable characteristics over a long period of time and can be manufactured with good reproducibility.
問題点を解決するための手段
絶縁性基板上に設けた、少なくともドレイン電極、ゲー
ト電極、ソース電極、半導体膜及びゲート絶縁膜で構成
され、前記ゲート絶縁膜が０．８Ｐａ以上２．０Ｐａ以
下の雰囲気ガス中でのスパッタ絶縁膜からなる。Means for Solving the Problems The method comprises at least a drain electrode, a gate electrode, a source electrode, a semiconductor film, and a gate insulating film provided on an insulating substrate, and the gate insulating film has a pressure of 0.8 Pa or more and 2.0 Pa or less. Consists of an insulating film sputtered in an atmospheric gas.
作用
本発明によれば、スパッタ時の雰囲気ガスの圧力を限定
したスパッタ法により形成された絶縁物薄膜が用いられ
ており、これらの膜はプラズマ粒子の衝突による欠陥が
少なく、かつ化学量論的組成からのずれも少ないため電
荷トラップが少なく、また、ゲートリーク電流も非常に
小さい。According to the present invention, insulating thin films formed by a sputtering method in which the pressure of atmospheric gas during sputtering is limited are used, and these films have few defects caused by collisions of plasma particles and have a stoichiometric Since there is little deviation from the composition, there are few charge traps, and gate leakage current is also very small.
これにより本発明の薄膜トランジスタはゲート絶縁膜中
の電荷トラップが少なく、リーク電流を少なくしている
ので、経時変化の小さいものとなる。As a result, the thin film transistor of the present invention has fewer charge traps in the gate insulating film and less leakage current, resulting in less change over time.
実施例
以下、本発明の実施例を添付図面にもとすいて説明する
。Embodiments Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
第１図は本発明の薄膜トランジスタの一実施例を示す断
面図である。FIG. 1 is a sectional view showing an embodiment of a thin film transistor of the present invention.
ガラス等の絶縁性基板１上に１１００ｎ程度の膜厚を有
するＡＩからなるゲート電極２、さらにそのゲート電極
２を含む絶縁性基板１上に３００ｎｍ程度の膜厚を有し
、高周波マグネトロンスパッタ法により形成されたＡｌ
ｔｏｓからなるゲート絶縁膜３、この上に５０ｎｍ程度
の膜厚を有し、抵抗加熱法により形成されたＣｄＳｅか
らなる半導体膜４、さらにその上に、数〜数十ミクロン
の所定の間隔を隔てて１１００ｎ程度の膜厚を有するＡ
Ｉからなるソース電極５及びドレイン電極６がら構成さ
れている。A gate electrode 2 made of AI having a film thickness of about 1100 nm is formed on an insulating substrate 1 such as glass, and a film thickness of about 300 nm is formed on the insulating substrate 1 including the gate electrode 2 by high frequency magnetron sputtering. Formed Al
A gate insulating film 3 made of ToS, on which a semiconductor film 4 made of CdSe having a film thickness of about 50 nm and formed by a resistance heating method, and further on top of this a semiconductor film 4 made of CdSe with a film thickness of about 50 nm, with a predetermined interval of several to several tens of microns apart. A with a film thickness of about 1100n
It is composed of a source electrode 5 and a drain electrode 6 made of I.
第２図はゲート絶縁膜３をスパッタするさいの雰囲気ガ
スの圧力を変化させたときの実効トラップ密度を示して
いる。実効トラップ密度の測定方法は、たとえば、Ｔ、
Ｈ，Ｎｉｎｇ ｅｔ ａｌ： Ｊ、Ａｐｐｌ、ｐｈ
ｙｓ、、４５ （１９７４）５３７３に示されている方
法を用いた。FIG. 2 shows the effective trap density when the pressure of the atmospheric gas during sputtering of the gate insulating film 3 is varied. The method for measuring the effective trap density is, for example, T,
H, Ning et al: J, Appl, ph.
ys, 45 (1974) 5373 was used.
また、第３図は同様にゲート絶縁膜３をスパッタするさ
いの雰囲気ガスの圧力とゲートリーク電流との関係を示
している。ゲートリーク電流は、第一図に示す薄膜トラ
ンジスタにおいてソース電極５とドレイン電極６とをシ
目−ト′シて゛、それらの電極とゲート電極との間にＩ
ＯＶの電圧を印加したときの電流を示している。Further, FIG. 3 similarly shows the relationship between the pressure of the atmospheric gas and the gate leakage current when sputtering the gate insulating film 3. In the thin film transistor shown in FIG.
It shows the current when a voltage of OV is applied.
第２図から明らかなように、ゲート絶縁膜３をスパッタ
するさいの雰囲気ガスの圧力を０．８Ｐａ以上とするこ
とにより実効トラップ密度が十分に小さ（なり、薄膜ト
ランジスタの経時変化を小さ（することができる。また
、第３図からは雰囲気ガスの圧力を２．０Ｐａ以下とす
ることにより、ゲートリーク電流を十分に小さくするこ
とができることがわかる。これは、雰囲気ガスの圧力を
０．８Ｐａ以上とすれば、スパッタ時にプラズマ粒子同
士が衝突する確率が増え、直接ゲート絶縁膜の表面にプ
ラズマ粒子が衝突して欠陥を生成する確率が減少するた
めであり、また、２．０Ｐａ以上では、プラズマの活性
度が低（なり酸素ガスとの反応性が悪くなり、組成比が
化学量論的組成からずれることによりゲートリーク電流
が増えるためと考えられる。As is clear from FIG. 2, by setting the pressure of the atmospheric gas at 0.8 Pa or more when sputtering the gate insulating film 3, the effective trap density becomes sufficiently small, and the aging change of the thin film transistor can be reduced. Also, from Fig. 3, it can be seen that the gate leakage current can be made sufficiently small by setting the pressure of the atmospheric gas to 2.0 Pa or less. This is because the probability that plasma particles collide with each other during sputtering increases, and the probability that plasma particles directly collide with the surface of the gate insulating film and generate defects decreases. This is thought to be because the activity of the oxide is low (and the reactivity with oxygen gas is poor, and the composition ratio deviates from the stoichiometric composition, resulting in an increase in gate leakage current.
以上で示したように、本発明の薄膜トランジスタは、ゲ
ート絶縁膜として雰囲気ガスの圧力を０．８Ｐａ以上、
２．０Ｐａ以下でのスパッタ絶縁膜としているので、経
時変化が非常に小さ（、ゲートリーク電流も少ない。As shown above, in the thin film transistor of the present invention, the pressure of the atmospheric gas as the gate insulating film is 0.8 Pa or more.
Since the insulating film is sputtered at 2.0 Pa or less, the change over time is very small (and the gate leakage current is also small).
第４図はゲート絶縁膜のスパッタ時のパワー密度を変化
させたときの実効トラップ密度を調べた結果である。図
から明らかなように、パワー密度が４．０Ｗ／ａｍ２以
下では十分に実効トラップ密度が小さく、経時変化の小
さい薄膜トランジスタが得られることがわかる。FIG. 4 shows the results of investigating the effective trap density when varying the power density during sputtering of the gate insulating film. As is clear from the figure, when the power density is 4.0 W/am2 or less, the effective trap density is sufficiently small, and a thin film transistor with small changes over time can be obtained.
また、スパッタ時の基板温度が２００℃以上では、上記
した効果が特に顕著であり、さらに実効トラップ密度が
減少することが確認された。Furthermore, it was confirmed that when the substrate temperature during sputtering is 200° C. or higher, the above-mentioned effect is particularly remarkable, and the effective trap density is further reduced.
スパッタ時の雰囲気ガスとしては、アルゴンガスと酸素
ガスとの混合ガス雰囲気が望ましい。The atmospheric gas during sputtering is preferably a mixed gas atmosphere of argon gas and oxygen gas.
また、ゲート絶縁膜の材料をＡＩとＴａとの複合絶縁膜
とすれば誘電率が大きいことから、薄膜トランジスタの
相互コンダクタンスを太き（でき、ゲート電圧を小さ（
できることから、ゲート絶縁膜中へのトンネル効果によ
る電子の注入そのものを小さくできるため、さらに経時
変化を小さくすることができる。In addition, if the material of the gate insulating film is a composite insulating film of AI and Ta, the dielectric constant is large, so the mutual conductance of the thin film transistor can be increased (larger), and the gate voltage can be lowered (
As a result, the injection of electrons into the gate insulating film due to the tunneling effect itself can be reduced, so that changes over time can be further reduced.
本実施例では、半導体膜としてＣｄＳｅを用いた場合に
ついて述べたが、ＣｄＳ、、ＣｄＴｅあるいはそれらの
固溶体の場合にも本発明の効果が大であることがわかっ
た。In this example, the case where CdSe was used as the semiconductor film was described, but it was found that the present invention is also highly effective when using CdS, CdTe, or a solid solution thereof.
発明の効果
以上の説明から明らかなように、本発明の薄膜トランジ
スタでは、ゲート絶縁膜中の電荷トラップが少な（、ま
た、リーク電流が少ないことから電荷トラップへの電子
の注入そのものが起こりに（いため、薄膜トランジスタ
の電気特性や安定性を大きく改善することができ、各種
表示装置やイメージセンサ等の駆動回路等に広く利用で
きるものである。Effects of the Invention As is clear from the above explanation, in the thin film transistor of the present invention, the number of charge traps in the gate insulating film is small (and the leakage current is small, so injection of electrons into the charge traps itself does not occur). , the electrical characteristics and stability of thin film transistors can be greatly improved, and can be widely used in drive circuits for various display devices, image sensors, etc.
第１図は本発明の薄膜トランジスタの一実施例を示す断
面図、第２図はスパッタ時の雰囲気ガスの圧力とゲ−ト
絶縁膜中の実効トラップ密度との関係を示す図、第３図
はスパッタ時の雰囲気ガスの圧力とゲートリーク電流と
の関係を示す図、第４図はスパッタ時のパワー密度とゲ
ート絶縁膜中の実効トラップ密度との関係を示す図であ
る。
１・・・絶縁性基板、２・・・ゲート電極、３・・・ゲ
ート絶縁膜、４・・・半導体膜、５・・・ソース電極、
６・・・ドレイン電極
代理人の氏名 弁理士 中尾敏男 ほか１名第２１！ｌFIG. 1 is a cross-sectional view showing an embodiment of the thin film transistor of the present invention, FIG. 2 is a diagram showing the relationship between the pressure of atmospheric gas during sputtering and the effective trap density in the gate insulating film, and FIG. FIG. 4 is a diagram showing the relationship between atmospheric gas pressure and gate leakage current during sputtering, and FIG. 4 is a diagram showing the relationship between power density during sputtering and effective trap density in the gate insulating film. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Gate electrode, 3... Gate insulating film, 4... Semiconductor film, 5... Source electrode,
6... Name of drain electrode agent Patent attorney Toshio Nakao and 1 other person No. 21! l
Claims (6)
、ゲート電極、ソース電極、半導体膜及びゲート絶縁膜
から構成され、前記ゲート絶縁膜が０．８Ｐａ以上２．
０Ｐａ以下の雰囲気ガス中でのスパッタ絶縁膜からなる
ことを特徴とする薄膜トランジスタ。(1) The gate insulating film is formed of at least a drain electrode, a gate electrode, a source electrode, a semiconductor film, and a gate insulating film provided on an insulating substrate, and the gate insulating film has a pressure of 0.8 Pa or more.
A thin film transistor comprising an insulating film sputtered in an atmospheric gas of 0 Pa or less.
２以下でのスパッタ絶縁膜からなることを特徴とする特
許請求の範囲第１項記載の薄膜トランジスタ。(2) The gate insulating film has a power density of 4.0 W/cm^
2. The thin film transistor according to claim 1, wherein the thin film transistor is made of a sputtered insulating film with a sputtering rate of 2 or less.
パッタ絶縁膜からなることを特徴とする特許請求の範囲
第１項記載の薄膜トランジスタ。(3) The thin film transistor according to claim 1, wherein the gate insulating film is made of a sputtered insulating film at a substrate temperature of 200° C. or higher.
ガスとの混合雰囲気中でのスパッタ絶縁膜からなること
を特徴とする特許請求の範囲第１項記載の薄膜トランジ
スタ。(4) The thin film transistor according to claim 1, wherein the gate insulating film is a sputtered insulating film in a mixed atmosphere of at least oxygen gas and argon gas.
分とする複合絶縁膜からなるスパッタ絶縁膜であること
を特徴とする特許請求の範囲第１項記載の薄膜トランジ
スタ。(5) The thin film transistor according to claim 1, wherein the gate insulating film is a sputtered insulating film made of a composite insulating film containing at least Al and Ta as main components.
はそれらの固溶体であることを特徴とする特許請求の範
囲第１項記載の薄膜トランジスタ。(6) The thin film transistor according to claim 1, wherein the semiconductor film is CdS, CdSe, CdTe, or a solid solution thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62251036A JP2751164B2 (en) | 1987-10-05 | 1987-10-05 | Method for manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62251036A JP2751164B2 (en) | 1987-10-05 | 1987-10-05 | Method for manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0193172A true JPH0193172A (en) | 1989-04-12 |
| JP2751164B2 JP2751164B2 (en) | 1998-05-18 |
Family
ID=17216660
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62251036A Expired - Lifetime JP2751164B2 (en) | 1987-10-05 | 1987-10-05 | Method for manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2751164B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5270229A (en) * | 1989-03-07 | 1993-12-14 | Matsushita Electric Industrial Co., Ltd. | Thin film semiconductor device and process for producing thereof |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57104224A (en) * | 1980-12-22 | 1982-06-29 | Hitachi Ltd | Forming method of insulating thin film |
| JPS59147460A (en) * | 1983-02-10 | 1984-08-23 | Matsushita Electric Ind Co Ltd | Thin-film transistor |
| JPS6027132A (en) * | 1983-07-25 | 1985-02-12 | Mitsubishi Electric Corp | Formation of insulating film |
| JPS60132368A (en) * | 1983-12-20 | 1985-07-15 | Matsushita Electric Ind Co Ltd | Thin film transistor |
| JPS6177329A (en) * | 1984-09-21 | 1986-04-19 | Toshiba Corp | Thin film former |
| JPS61168962A (en) * | 1985-01-22 | 1986-07-30 | Matsushita Electric Ind Co Ltd | Manufacture of thin-film transistor |
| JPS6242564A (en) * | 1985-08-20 | 1987-02-24 | Matsushita Electric Ind Co Ltd | Thin film transistor and manufacture of the same |
| JPS6281060A (en) * | 1985-10-04 | 1987-04-14 | Matsushita Electric Ind Co Ltd | Thin film transistor |
-
1987
- 1987-10-05 JP JP62251036A patent/JP2751164B2/en not_active Expired - Lifetime
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57104224A (en) * | 1980-12-22 | 1982-06-29 | Hitachi Ltd | Forming method of insulating thin film |
| JPS59147460A (en) * | 1983-02-10 | 1984-08-23 | Matsushita Electric Ind Co Ltd | Thin-film transistor |
| JPS6027132A (en) * | 1983-07-25 | 1985-02-12 | Mitsubishi Electric Corp | Formation of insulating film |
| JPS60132368A (en) * | 1983-12-20 | 1985-07-15 | Matsushita Electric Ind Co Ltd | Thin film transistor |
| JPS6177329A (en) * | 1984-09-21 | 1986-04-19 | Toshiba Corp | Thin film former |
| JPS61168962A (en) * | 1985-01-22 | 1986-07-30 | Matsushita Electric Ind Co Ltd | Manufacture of thin-film transistor |
| JPS6242564A (en) * | 1985-08-20 | 1987-02-24 | Matsushita Electric Ind Co Ltd | Thin film transistor and manufacture of the same |
| JPS6281060A (en) * | 1985-10-04 | 1987-04-14 | Matsushita Electric Ind Co Ltd | Thin film transistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5270229A (en) * | 1989-03-07 | 1993-12-14 | Matsushita Electric Industrial Co., Ltd. | Thin film semiconductor device and process for producing thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2751164B2 (en) | 1998-05-18 |
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