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JPH0191478A - Optical connection circuit - Google Patents

Optical connection circuit

Info

Publication number
JPH0191478A
JPH0191478A JP62247962A JP24796287A JPH0191478A JP H0191478 A JPH0191478 A JP H0191478A JP 62247962 A JP62247962 A JP 62247962A JP 24796287 A JP24796287 A JP 24796287A JP H0191478 A JPH0191478 A JP H0191478A
Authority
JP
Japan
Prior art keywords
clock signal
light
semiconductor substrate
package
emitting device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62247962A
Other languages
Japanese (ja)
Inventor
Tomoo Yanase
柳瀬 知夫
Mitsukazu Kondo
充和 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62247962A priority Critical patent/JPH0191478A/en
Publication of JPH0191478A publication Critical patent/JPH0191478A/en
Pending legal-status Critical Current

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  • Semiconductor Lasers (AREA)
  • Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)

Abstract

PURPOSE:To reduce skew of clock signal, and realize small size and low cost, by providing a semiconductor photoelectronic integrated circuit with a light emitting device generating light clock, and a photo detector receiving the light clock signal, and forming a light scattering body on the rear of a package. CONSTITUTION:On a photoelectronic integrated circuit, the follow are integrated; a light emitting device 12 generating light clock signal, a plurality of photo detectors 13 receiving the light clock signal, and a light scattering body 16 which is formed on the surface facing a semiconductor substrate 11 inside a package 15 of the photoelectronic integrated circuit, and scatters the clock signal generated from the light emitting device 12 to make the photo detector 13 detect the scattered light. The clock signal is radiated from the light emitting device 12 formed on the semiconductor substrate 11, and scattered by the light scattering body 16 formed inside the package 15. The clock signal of the scattered light is detected by the plurality of photo detectors 13 formed on the semiconductor substrate 11, and the detected clock signal is delivered to electronic circuits on the semiconductor substrate 11. Thereby reducing the skew of clock signal, and obtaining a small-sized package of low cost.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電子回路が集積された半導体基板に、光で信
号を送る機能を付加した光電子集積回路におけるクロッ
ク信号用の光接続回路に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an optical connection circuit for clock signals in an optoelectronic integrated circuit in which a function of transmitting signals by light is added to a semiconductor substrate on which electronic circuits are integrated. It is.

〔従来の技術〕[Conventional technology]

シリコン集積回路の高密度化が進み、1メガDRAMに
代表される大規模半導体メモリや、32ビツトプロセツ
サに代表される大規模半導体ロジックが市販されている
。これらの素子をより高速度に動かすためには、各素子
を同期がとれた、より高速のクロック信号で動かさなけ
ればならない。
As the density of silicon integrated circuits continues to increase, large-scale semiconductor memories such as 1 mega DRAMs and large-scale semiconductor logics such as 32-bit processors are now commercially available. In order to move these elements at higher speeds, each element must be driven by a synchronized, faster clock signal.

もし、各素子のクロック信号にスキュー(時間ずれ)が
あると、各素子での動作が同期せず、高速動作ができな
くなる。
If there is a skew (time difference) in the clock signals of each element, the operations of each element will not be synchronized and high-speed operation will not be possible.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

通常、この問題を防ぐためには、クロック信号6を線長
をできるだけ等しくなるように各素子のレイアウトを行
っていた。このため、素子のレイアウトに制限を受け、
設計を難しいものにしていた。
Normally, in order to prevent this problem, each element is laid out so that the line lengths of the clock signal 6 are as equal as possible. For this reason, there are restrictions on the layout of the element,
This made the design difficult.

このようなレイアウトでもクロックスキューは、完全に
は解決できない。このような場合には、クロック信号を
ラッチしておき1タイムスロフト分遅らせて、同期をと
っていた。このため、処理速度が低減するという問題が
あった。
Even with this layout, clock skew cannot be completely resolved. In such a case, synchronization was achieved by latching the clock signal and delaying it by one time loft. Therefore, there was a problem that the processing speed was reduced.

この問題を解決する方法として、ビー・デイ−・クライ
マーとジェー・ダブリュ・グツドマン(B、D、Cly
mer and J、W、Goodman)は、刊行物
「オプティカル・エンジニャリングの1986年25巻
(Optical Engineering、 vol
、25+ 1986)Jの1103頁に、第2図に示す
光接続回路の概念を提案している。
As a way to solve this problem, B.D.Climber and J.W.
mer and J.W. Goodman) in the publication ``Optical Engineering, vol. 25, 1986.
, 25+ 1986) J, p. 1103, proposed the concept of an optical connection circuit shown in FIG.

この提案は、実際に試作されたものではなく、概念が提
案されたものに過ぎない。以下に、この概念を説明する
。VLS Iの外部に半導体レーザ22を設け、その半
導体レーザ22で発光した光によるクロック信号を、ホ
ログラム26でシリコン半導体基板21上に形成された
光検知器23に分岐照射する。
This proposal is not an actual prototype, but merely a proposed concept. This concept will be explained below. A semiconductor laser 22 is provided outside the VLSI, and a clock signal generated by light emitted by the semiconductor laser 22 is branched and irradiated onto a photodetector 23 formed on a silicon semiconductor substrate 21 using a hologram 26 .

ホログラム上には、あらかじめシリコン半導体基板の光
検知器23の位置情報を書き込み、効率よく光クロック
信号が光検知器23に照射されるようにされている。
Position information of the photodetector 23 on the silicon semiconductor substrate is written on the hologram in advance so that the photodetector 23 is efficiently irradiated with an optical clock signal.

しかし、この光接続回路では、ホログラム26と半導体
基板21の距離を1cm以上取る必要があり、素子のパ
ッケージの小型化に、大きな制約となっていた。また、
ホログラムの形状をVLS Iの種類が異なるごとに、
作りかえる必要があり、低価格でVLS Iを作るため
の障害になっていた。
However, in this optical connection circuit, it is necessary to maintain a distance of 1 cm or more between the hologram 26 and the semiconductor substrate 21, which poses a major constraint on miniaturization of the element package. Also,
The shape of the hologram is different for each type of VLSI.
It had to be rebuilt, which was an obstacle to making VLSI at a low price.

以上述べてきたように、従来行われてきたVLSIのク
ロック信号の接続を電気で行うと、スキューの問題が起
こり、光で行う光接続では、素子の小型化や低価格化が
障害となっていた。
As mentioned above, when connecting VLSI clock signals using electricity, which has traditionally been done, the problem of skew occurs, and when using optical connections using light, the miniaturization and cost reduction of devices are obstacles. Ta.

そこで、本発明の目的は、VLSIのクロック信号のス
キューを小さく、かつVLS Iのパッケージの大きさ
を小型にかつ低価格に形成することのできる光接続回路
を提供することにある。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an optical connection circuit that can reduce the skew of a VLSI clock signal, reduce the size of a VLSI package, and form a low-cost VLSI package.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、電子回路が集積された半導体基板に、光で信
号を送る機能が付加された光電子集積回路のクロック信
号用光接続回路において、前記光電子集積回路に集積さ
れた、光クロック信号を発光する発光素子および光クロ
ック信号を検知する複数の受光素子と、 前記光電子集積回路のパッケージの内側の前記半導体基
板と相対する表面に形成され、前記発光素子から発光し
た光クロック信号を散乱し前記受光素子に検知させる光
散乱体とを有することを特徴としている。
The present invention provides an optical connection circuit for a clock signal of an optoelectronic integrated circuit in which a function of transmitting a signal by light is added to a semiconductor substrate on which an electronic circuit is integrated. a light-emitting element for detecting an optical clock signal and a plurality of light-receiving elements for detecting an optical clock signal; It is characterized by having a light scattering body that is detected by the element.

〔作用〕[Effect]

本発明では、クロック信号は半導体基板上に形成された
発光素子から出射され、パッケージの内側に形成された
光散乱体によって散乱される。この散乱光のクロック信
号は、半導体基板上に複数形成された受光素子に検知さ
れる。検知されたクロック信号は半導体基板上の電子回
路に配られる。
In the present invention, a clock signal is emitted from a light emitting element formed on a semiconductor substrate, and is scattered by a light scattering body formed inside a package. The clock signal of this scattered light is detected by a plurality of light receiving elements formed on the semiconductor substrate. The sensed clock signal is distributed to electronic circuitry on the semiconductor substrate.

この場合、光で半導体基板上部のクロック信号がつなが
っているために、クロックスキューは小さく問題にはな
らない。
In this case, since the clock signals on the top of the semiconductor substrate are connected by light, the clock skew is small and does not pose a problem.

以上のような散乱反射によれば、光散乱体と発光素子や
受光素子との距離を数ミリメートル以下にすることが可
能で、パッケージが大型になるようなことはない。さら
に、光散乱体は容易に形成可能であり、価格も高価なホ
ログラムを使用せずに済ませることができ、非常に低価
格になる。
According to the scattering and reflection described above, it is possible to reduce the distance between the light scattering body and the light emitting element or the light receiving element to several millimeters or less, and the package does not become large. Furthermore, the light scattering body can be easily formed and can be produced at a very low cost since it does not require the use of expensive holograms.

〔実施例〕〔Example〕

次に図面を用いて本発明の詳細な説明する。 Next, the present invention will be explained in detail using the drawings.

第1図は本発明の一実施例を説明するための斜視図であ
り、VLS Iの上部の蓋のような形状のセラミックパ
ッケージ15を基板14からはずし90゜回転させた状
態である。パッケージの基板14上にシリコン半導体基
板11が形成され、この半導体基板11上には複数の光
検知器13が設けられ、半導体基板11のほぼ中央部に
GaAs半導体レーザ12が設けられている。この半導
体レーザ12は、シリコン半導体基板11に対して垂直
方向にレーザ光がでるように45度反射鏡が集積された
垂直出射型を用いた。
FIG. 1 is a perspective view for explaining one embodiment of the present invention, in which a ceramic package 15 shaped like a top lid of a VLSI is removed from a substrate 14 and rotated 90 degrees. A silicon semiconductor substrate 11 is formed on a substrate 14 of the package, a plurality of photodetectors 13 are provided on this semiconductor substrate 11, and a GaAs semiconductor laser 12 is provided approximately in the center of the semiconductor substrate 11. The semiconductor laser 12 used was a vertical emission type in which 45-degree reflecting mirrors were integrated so that laser light was emitted in a direction perpendicular to the silicon semiconductor substrate 11.

一方、パッケージ15の裏側の面には、表面凹凸の多い
セラミックの上に金属を蒸着して散乱反射面16を形成
した。このとき、散乱反射面16とGaAs半導体レー
ザ12の距離は特に制限を受けないので、数ミリメート
ル以下に近づけることができる。
On the other hand, on the back side of the package 15, a scattering/reflecting surface 16 was formed by vapor-depositing metal on a ceramic having many surface irregularities. At this time, the distance between the scattering/reflecting surface 16 and the GaAs semiconductor laser 12 is not particularly limited, and can be made as close as several millimeters or less.

以上のような構成の光接続回路において、レーザ12を
駆動する電気信号はこのVLS Iのクロック信号であ
る。このレーザから発射した波長0.85ミクロンの光
クロック信号は、上部の蓋のような形状のセラミックパ
ッケージ15の裏側に形成された散乱反射面16で散乱
される。散乱された光クロック信号は、再びシリコン半
導体基板11上に戻り、光検知器13で検知され、電気
クロック信号に戻される。散乱光は平均的にほぼ等しい
距離を伝搬し、光検知器に到達するので、各光検知器に
受光される光クロック信号の間には、はとんどスキュー
がない。
In the optical connection circuit configured as described above, the electrical signal that drives the laser 12 is the clock signal of this VLSI. An optical clock signal with a wavelength of 0.85 microns emitted from this laser is scattered by a scattering/reflection surface 16 formed on the back side of a ceramic package 15 shaped like an upper lid. The scattered optical clock signal returns onto the silicon semiconductor substrate 11, is detected by the photodetector 13, and is converted back into an electrical clock signal. Since the scattered light propagates approximately the same distance on average and reaches the photodetector, there is almost no skew between the optical clock signals received by each photodetector.

以上の実施例では、散乱反射面としてセラミックの表面
に金属蒸着したものを用いたが、金属板の表面を凹凸加
工して形成された散乱反射面であってもよい。これらの
散乱反射面は、ホログラムに比べ、非常に簡易に製造が
可能であり、安価に作ることができる。
In the above embodiments, a ceramic surface with metal vapor deposited thereon was used as the scattering/reflection surface, but a scattering/reflection surface formed by roughening the surface of a metal plate may also be used. These scattering/reflecting surfaces can be manufactured much more easily and at lower cost than holograms.

上記実施例においては、半導体レーザとして、45度反
射鏡が集積された垂直出射型を用いたが、グレーティン
グの高次回折光を用いた垂直出射型半導体レーザでもよ
く、積層方向に発振する固型半導体レーザでもよい。
In the above embodiment, a vertical emission type semiconductor laser with integrated 45-degree reflecting mirrors was used, but a vertical emission type semiconductor laser using higher-order diffracted light from a grating may also be used, and a solid-state semiconductor laser that oscillates in the stacking direction A laser may also be used.

また、上記実施例においては、半導体基板としてシリコ
ン半導体が用いられたが、GaAsや■nPなどの化合
物半4体でも同様な効果が得られる。
Further, in the above embodiments, a silicon semiconductor was used as the semiconductor substrate, but similar effects can be obtained with compound halves such as GaAs or ■nP.

また、上記実施例の各素子やパッケージの形状は前述し
たように選定されたが、本発明はこれらに限定されるも
のではないことは明らかである。
Furthermore, although the shapes of each element and package in the above embodiments were selected as described above, it is clear that the present invention is not limited thereto.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、半寡体光電子集
積回路に光クロック信号を発生する発光素子と、光クロ
ック信号を受光する受光素子とを設け、パフケージの裏
面に光散乱体を形成することによって、従来問題となっ
ていたクロック信号のスキューが小さく、小型でかつ低
価格なVLSIを可能とする光接続回路を得ることがで
きる。
As explained above, according to the present invention, a semi-oligoelectronic integrated circuit is provided with a light emitting element that generates an optical clock signal and a light receiving element that receives the optical clock signal, and a light scattering body is formed on the back surface of the puff cage. By doing so, it is possible to obtain an optical connection circuit which has a small skew of a clock signal, which has been a problem in the past, and which enables a small and low-cost VLSI.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を説明する斜視図、第2図は
従来の光接続回路を説明する斜視図である。 11・・・・・シリコン半導体基板 12・・・・・GaAsレーザ 13・・・・・光検知器 14・・・・・パッケージの基板 15・・・・・セラミックパッケージ 16・・・・・散乱反射面 21・・・・・シリコン半辱体基板 22・・・・・半導体レーザ 23・・・・・光検知器 26・・・・・ホログラム 代理人 弁理士  岩 佐  義 幸 第1図
FIG. 1 is a perspective view illustrating an embodiment of the present invention, and FIG. 2 is a perspective view illustrating a conventional optical connection circuit. 11... Silicon semiconductor substrate 12... GaAs laser 13... Photodetector 14... Package substrate 15... Ceramic package 16... Scattering Reflective surface 21...Silicon half body substrate 22...Semiconductor laser 23...Photodetector 26...Hologram agent Patent attorney Yoshiyuki Iwasa Figure 1

Claims (1)

【特許請求の範囲】[Claims] (1)電子回路が集積された半導体基板に、光で信号を
送る機能が付加された光電子集積回路のクロック信号用
光接続回路において、 前記光電子集積回路に集積された、光クロック信号を発
光する発光素子および光クロック信号を検知する複数の
受光素子と、 前記光電子集積回路のパッケージの内側の前記半導体基
板と相対する表面に形成され、前記発光素子から発光し
た光クロック信号を散乱し前記受光素子に検知させる光
散乱体とを有することを特徴とする光接続回路。
(1) In an optical connection circuit for a clock signal of an optoelectronic integrated circuit in which a function of transmitting a signal by light is added to a semiconductor substrate on which an electronic circuit is integrated, the optical clock signal integrated in the optoelectronic integrated circuit is emitted. a light-emitting element and a plurality of light-receiving elements for detecting optical clock signals; 1. An optical connection circuit comprising: a light scattering body that is detected by a light scatterer;
JP62247962A 1987-10-02 1987-10-02 Optical connection circuit Pending JPH0191478A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62247962A JPH0191478A (en) 1987-10-02 1987-10-02 Optical connection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62247962A JPH0191478A (en) 1987-10-02 1987-10-02 Optical connection circuit

Publications (1)

Publication Number Publication Date
JPH0191478A true JPH0191478A (en) 1989-04-11

Family

ID=17171144

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62247962A Pending JPH0191478A (en) 1987-10-02 1987-10-02 Optical connection circuit

Country Status (1)

Country Link
JP (1) JPH0191478A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5430567A (en) * 1992-09-16 1995-07-04 International Business Machines Corporation Method of clocking integrated circuit chips
GB2340995A (en) * 1998-08-26 2000-03-01 Lsi Logic Corp Low skew signal distribution for integrated circuits

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6161461A (en) * 1984-09-03 1986-03-29 Toshiba Corp Photoelectric integrated element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6161461A (en) * 1984-09-03 1986-03-29 Toshiba Corp Photoelectric integrated element

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5430567A (en) * 1992-09-16 1995-07-04 International Business Machines Corporation Method of clocking integrated circuit chips
US5434524A (en) * 1992-09-16 1995-07-18 International Business Machines Corporation Method of clocking integrated circuit chips
GB2340995A (en) * 1998-08-26 2000-03-01 Lsi Logic Corp Low skew signal distribution for integrated circuits
US6624447B1 (en) 1998-08-26 2003-09-23 Lsi Logic Corporation Low skew signal distribution for integrated circuits

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