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JPH01313969A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH01313969A
JPH01313969A JP63145203A JP14520388A JPH01313969A JP H01313969 A JPH01313969 A JP H01313969A JP 63145203 A JP63145203 A JP 63145203A JP 14520388 A JP14520388 A JP 14520388A JP H01313969 A JPH01313969 A JP H01313969A
Authority
JP
Japan
Prior art keywords
lead pin
wiring board
insulating substrate
printed wiring
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63145203A
Other languages
English (en)
Inventor
Kanji Otsuka
寛治 大塚
Masao Kato
正男 加藤
Takashi Kumagai
熊谷　多加史
Mitsuo Usami
光雄 宇佐美
Shigeo Kuroda
黒田　重雄
Kunizo Sawara
佐原　邦造
Takeo Yamada
健雄 山田
Seiji Miyamoto
誠司 宮本
Masayuki Shirai
優之 白井
Takayuki Okinaga
隆幸 沖永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to JP63145203A priority Critical patent/JPH01313969A/ja
Publication of JPH01313969A publication Critical patent/JPH01313969A/ja
Priority to US07/645,357 priority patent/US5067007A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
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    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
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    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
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    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置のパッケージ技術に関し、特に、
ピン・グリッドアレイ・パッケージの多ビン化に適用し
て有効な技術に関するものである。
〔従来の技術〕
コンビエータの大容量化、高速化に伴い、論理ＬＳＩや
画像処理ＬＳＩなどを実装するパッケージの多ビン化が
急速に進行している。
多ピン化に適したパッケージとしては、ビン挿入タイプ
では、ピン・グリッド・アレイ　（以下、ＰＧＡという
）が、また、表面実装タイプでは、Ｐ　Ｌ　ＣＣ（ｐｌ
ａｓｔｉｃ　Ｉｅａｄｅｄ　ｃｈｉｐ　ｃａｒｒｉｅｒ
）が知られており、それらの動向については、例えば、
株式会社工業調査会、昭和６２年９月１　’Ｂ発行、「
電子材料」Ｐ４０〜Ｐ４６に記載がある。
とりわけ、ＰＧＡ方式は、パッケージの裏面全体をリー
ドピンの取り出しに利用できることがら、３００〜５０
０ピンなどのような超多ピンを必要とするＬＳＩに最適
なパッケージ構造とされ、近年、特に注目されている。
〔発明が解決しようとする課題〕
本発明者は、上記ＰＧＡの多ビン化を促進するにあたっ
ての問題点について検討した。その概要は、下記の通り
である。
すなわち、ＰＧＡを印刷配線板に実装するには、従来、
約０，４６韻径のリードピンを０．７〜０．８舗径のス
ルーホールに挿入する必要があった。
その際、各スルーホールの周囲にランドが形成されるた
め、実効的なスルーホール径は、約０．８５〜１．０　
ｍとなり、スルーホールを標準的な２．５４　ｍ＋ｇ　
（１００ｍ１ｌ）ピッチで格子状に配列した場合、隣接
するランドのピッチは、約１．５　ｍ■となる。
この場合、印刷配線板の表面に例えば、０．１８閣ピツ
チで配線を引き回すと、各ランド間を７本の配線が通過
できるが、３００〜５００ピンを有するＰＧＡでは、設
計上、１０〜１５本の配線を通過させる必要があるため
、もはや単層の印刷配線板では配線設計が不可能となる
。
ところが、３００〜５００のリードピンを２．５４市ピ
ツチで挿入できる多層印刷配線板を設計すると、今度は
、ＰＧＡパッケージの内部配線長および印刷配線板の内
部配線長が長くなり、伝送特性が低下してしまう。
そこで、この伝送特性を考慮してスルーホールピッチを
最適化すると、１．７８１１１１　（７０ｍ１ｌ）ピッ
チ、または１．２７ａｕａ（５０ｍ目）ピッチにする必
要があるため、配線ピッチが０．７８ｆｆＩＩｇまたは
０．２７腸となってしまい、結局、多層印刷配線板を用
いた場合でも、配線設計の限界を超えてしまうことにな
る。
このように、ＰＧＡの多ビン化を促進するためには、ピ
ン挿入方式では、もはや限界があるため、ピン挿入方式
に代わる表面実装方式の採用が不可欠となる。
すなわち、ＰＧＡのリードピン先端を印刷配線板の表面
電極に半田付け、またはろう付けする表面実装方式によ
れば、印刷配線板には、ピン挿入用のスルーホールが不
要となり、配線の引き回し上、ピアホールの必要な箇所
にのみ、リードピンの径と同じか、またはそれよりも僅
かに大径の表面電極を配列するだけでよい。この場合、
表面電極の径は、０．４６〜０．６　ｍｓでよいため、
標準的な２、５４　ｍピッチで格子状に配列した場合の
配線ピッチは、約２１１Ｉ１１となり、３００〜５００
ピン程度の超多ピンＰＧＡでも充分な配線スペースが得
られる。また、リードピンが挿入タイプでないため、そ
の径を０．１〜０．３鵬と細くすることができ、表面電
極を１．２７　ｍピッチで配列した場合でも、約１．Ｏ
Ｂの配線スペースが得られる。
さらに、パッケージの小形化も可能となるため、ＰＧＡ
パッケージの内部配線長および印刷配線板の内部配Ｓ長
が短くなり、伝送特性が改善されるという効果もある。
ところが、半田、またはろう材を用いてＰＧＡを印刷配
線板に表面実装する方式では、半導体チップの発熱によ
って、ＰＧＡパッケージと印刷配線板との間に熱的不整
合が生じた際、熱的および機械的応力がリードピンの半
田付け（または、ろう付け）箇所に集中して接合破壊を
引き起こすという問題がある。この破壊ポテンシャルは
、集積回路の高集積化に比例して増大し、ＰＧＡの多ピ
ン化を妨げる深刻な要因となる。
本発明は、上記問題点に着目してなされたものであり、
その目的は、ＰＧＡを印刷配線板に表面実装する際の接
続信頼性を向上させ、以て、ＰＧへの多ピン化を促進す
ることのできる技術を提供することにある。
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。
〔課題を解決するための手段〕
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。
すなわち、マイクロチップキャリヤの絶縁基板の裏面に
所定の間隔を置いて配設された電極にリードピンの一端
をろう付けするとともに、リードピンの他端を印刷配線
板の主面の電極に半田付け、または、ろう付けし、かつ
、上記リードピンの変形強度をその両端の接合強度より
も弱くした半導体装置構造とするものである。
〔作用〕
上記した手段によれば、マイクロチップキャリヤの絶縁
基板と印刷配線板との間の熱的不整合に起因する熱的機
械的応力をリードピンの変形によって緩和することがで
きるため、リードピン端部の接合破壊がを効に防止され
る。
〔実施例１〕 第１図は、本発明の一実施例である半導体装置を示す要
部断面図である。
本実施例１は、印刷配線板１の上面にマイクロチップキ
ャリヤ２を実装したモジニール構造の半導体装置である
。
印刷配線板１は、ガラス繊維含浸エポキシ樹脂、または
ポリイミド樹脂からなり、その表面には、内部の銅（Ｃ
ｕ）多層配線（図示せず）に接続された電極３が所定の
間隔を置いて多数配列されている。
マイクロチップキャリヤ２は、絶縁基板４とキャップ５
とからなるパッケージ構造を有し、その内部には、所定
の集積回路を形成した半導体チップ６が気密封止されて
いる。
半導体チップ６は、その集積回路形成面に接合された半
田バンブ７を介して絶縁基板４の上面の電極８にフェイ
スダウンボンディングされている。
また、半導体チップ６の裏面は、半田などの接合材９を
介してキャ７７′５の内側に接合され、動作時に半導体
チップ６から発生する熱がキャップ５を経て外部に放散
される構造となっている。
マイクロチップキャリヤ２の絶縁基板４は、ムライトな
どのセラミック材からなり、キャップ５は、窒化アルミ
ニウム（ＡＩＮ）などのセラミック材からなる。この絶
縁基板４とキャップ５とは、絶縁基板４の周縁部に被着
した半田などの接合材９を介して互いに接合され、マイ
クロチップキャリヤ２の内部の気密が維持される構造と
なっている。
絶縁基板４の表面には、薄膜からなる配線（図示せず）
が形成され、その所定箇所には、必要に応じて、チップ
コンデンサ１０などの受動素子が半田付けされる。
絶縁基板４の下面全体には、所定の間隔を置いて多数の
電極８が格子状に配設されており、これらの電極８は、
絶縁基板４の内部を通るタングステン（Ｗ）配線（図示
せず）を介して上面の電極８に接続されている。
絶縁基板４の下面の電極８には、リードピン１１の上端
が銀（Ａｇ）／銅（Ｃｕ）合金などのろう材１２を介し
て接合され、各リードピン１１の下端は、半田１３を介
して印刷配線板１の電極３に接合されている。
絶縁基板４と印刷配線板１とを接続する上記リードピン
１１は、その軸方向から圧縮荷重を受けた際の曲げ強度
（座屈強度）が、ろう材１２の接合強度および半田１３
の接合強度のいずれよりも小さい値となるように設計さ
れている。
すなわち、リードピン１１は、座屈荷重をＰｌまた、ろ
う材１２、半田１３の接合強度をそれぞれＳ、　、　　
Ｓ２　とした場合、ｐ＜ｓ、　、　　Ｓ２　を満足する
ような座屈強度を有している。
ここで、座屈荷重（Ｐ）は、下８己のオイラー式％式％ （Ｅ＝リードピンのヤング率、■＝リードピンの断面二
次モーメント、１＝リードピンの長さ）から導出される
値である（昭和５４年、海文堂発行、「材料力学・上巻
ＪＰ２０１〜Ｐ２Ｏ２）。
上記のような条件を満足するリードピン１１の材質とし
ては、例えば、タングステン、モリブデン、カーボン、
アモルファス金属、ばね性の強い細線などを例示するこ
とができる。また、上記細線を銅（Ｃｕ）などの軟金属
を結合材として束ねた複合線材でもよい。
これらの材料からなるリードピン１１の表面には、通常
金（Ａｕ）メツキあるいは金（Ａｕ）／ニッケル（Ｎｉ
）メツキなどが施されるが、メツキの膜厚は極めて薄い
ため、座屈強度に及ぼす影響は、無視してよい。
以上のように、絶縁基板４と印刷配線板１とを接続する
リードピン１１の座屈強度を、ろう材１２および半田１
３の接合強度のいずれ゛よりも小さくした本実施例１に
よれば、半導体チップ６０発熱によって、絶縁基板４と
印刷配線板１との間に熱的不整合が生じた場合でも、こ
の熱的不整合に起因する熱的機械的応力をリードピン１
１の変形によって緩和することができるため、リードピ
ン１１の端部の接合破壊が有効に防止される。
これにより、リードピン１１を備えたマイクロチップキ
ャリヤ２を印刷配線板１に表面実装する際の接続信頼性
が確保され、その多ピン化を促進することができるため
、超多ビンＰＧＡを実現することが可能となる。
〔実施例２〕 第２図は、本発明の他の実施例である半導体装置を示す
要部断面図、第３図は、この半導体装置のリードピンを
示す正面図である。
本実施例２の半導体装置もまた、絶縁基板４と印刷配線
板１との間に設けたリードピン１１を介してマイクロチ
ップキャリヤ２を印刷配線板１に表面実装したものであ
り、前記実施例１との相違点は、リードピン１１の形状
および材質である。
すなわち、本実施例２のリードピン１１は、熱的機械的
応力が加わった際、変形し易い形状となっている。すな
わち、このリードピン１１は、そのヤング率が１５×１
０１０Ｐａ以下の材質からなり、第３図に示すように、
軸方向からの変位（Δχ）が径（ｄ）の２以上となるよ
う、あらかじめその中央部を弓状に湾曲させである。
１５Ｘ１０１０Ｐａ以下のヤング率を有するり−ドピン
材料としては、例えば、高純度銅（Ｃｕ）、高純度鉄（
Ｆｅ）、高純度ニッケル（Ｎｉ）、銅（Ｃｕ）合金、ば
ね性の強い細線を銅（Ｃｕ）などの軟金属を結合材とし
て束ねた複合線材などの導電材料を例示することができ
る。
リードピン１１を上記のような形状、材質で構成するこ
とにより、その変形強度（降伏強度）がろう材１２およ
び半田１３の接合強度のいずれよりも小さくなり、熱的
機械的応力が加わった際、湾曲部に塑性変形が生じて応
力を緩和することができるため、前記実施例１の場合と
同様、リードピン端部の接合破壊を有効に防止すること
ができる。
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例１．２に限定
されるものではなく、その要旨を逸脱しない範囲で種々
変更可能であることはいうまでもない。
例えば、前記各実施例では、リードピンの下端と印刷配
線板の電極とを半田で接合したが、ろう材で接合しても
よい。この場合には、リードピンの変形強度をろう材の
接合強度よりも弱くすることによって、本発明の目的を
達成することができる。
また、前記各実施例では、半田バンプを介して半導体チ
ップを絶縁基板に実装したが、ＴＡＢ　（テープキャリ
ヤ）方式によって絶縁基板にフェイスダウンポンディン
グしてもよい。
その他、キャップの上面に放熱用の冷却フィンを設けた
り、絶縁基板や印刷配線板の材質を変更したすすること
も任意である。
〔発明の効果〕
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記の通りである
。
すなわち、マイクロチップキャリヤの絶縁基板の裏面に
所定の間隔を置いて配設された電極にリードピンの一端
をろう付けするとともに、リードピンの他端を印刷配線
板の主面の電極に半田付け、または、ろう付けし、かつ
、上記リードピンの変形強度をその両端の接合強度より
も弱くした半導体装置構造とすることにより、マイクロ
チップキャリヤの絶縁基板と印刷配線板との間の熱的不
整合に起因する熱的機械的応力をリードピンの変形によ
って緩和することができるため、リードピン端部の接合
破壊が有効に防止され、これにより、ＰＧＡの超多ピン
化が達成される。
【図面の簡単な説明】 第１図は本発明の一実施例である半導体装置を示す要部
断面図、 第２図は本発明の他の実施例である半導体装置を示す要
部断面図、 第３図はこの半導体装置のリードピンを示す正面図であ
る。 １・・・印刷配線板、２・・・マイクロチップキャリヤ
、３．８日・電極、４・・・絶縁基板、５・・・キャッ
プ、６・・・半導体チップ、７・・・半田バンプ、９・
・・接合材、１ｏ・・・チップコンデンサ、１１・・・
リートピン、１２・・・ろう材、１３・・・半田。 代理人　弁理士　筒　井　大　和 第２ｖＡ 第３図

Claims (1)

  1. 【特許請求の範囲】 １、所定の集積回路を形成した半導体チップを絶縁基板
    の主面の電極にフェイスダウン接続するとともに、前記
    半導体チップをキャップで気密封止したマイクロチップ
    キャリヤ構造を備え、かつ、前記絶縁基板の裏面に所定
    の間隔を置いて配設した電極にリードピンの一端をろう
    付けするとともに、前記リードピンの他端を印刷配線板
    の主面の電極に半田付け、または、ろう付けしてなる半
    導体装置であって、前記リードピンの変形強度をその両
    端の接合強度よりも弱くしたことを特徴とする半導体装
    置。 ２、リードピンの座屈強度をその両端の接合強度よりも
    弱くしたことを特徴とする請求項１記載の半導体装置。 ３、ヤング率が１５×１０＾１＾０Ｐａ以下の材質から
    なるリードピンをその軸方向からの変位が径のに以上と
    なるように湾曲させたことを特徴とする請求項１記載の
    半導体装置。
JP63145203A 1988-06-13 1988-06-13 半導体装置 Pending JPH01313969A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP63145203A JPH01313969A (ja) 1988-06-13 1988-06-13 半導体装置
US07/645,357 US5067007A (en) 1988-06-13 1991-01-24 Semiconductor device having leads for mounting to a surface of a printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63145203A JPH01313969A (ja) 1988-06-13 1988-06-13 半導体装置

Publications (1)

Publication Number Publication Date
JPH01313969A true JPH01313969A (ja) 1989-12-19

Family

ID=15379791

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63145203A Pending JPH01313969A (ja) 1988-06-13 1988-06-13 半導体装置

Country Status (2)

Country Link
US (1) US5067007A (ja)
JP (1) JPH01313969A (ja)

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