JPH01293569A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enhance the degree of freedoms of a ROM of a semiconductor integrated circuit device formed of a 1-chip microcomputer and to improve the functions of the circuit device by providing an EPROM, an EEPROM as nonvolatile memories. CONSTITUTION:In a semiconductor integrated circuit device having a central processing unit 100, and a nonvolatile memory for storing the program data of the unit 100, dictionary data, etc. on one semiconductor chip 1 to form a microcomputer, first nonvolatile memory (EPROM) 105 for electrically writing information and erasing the written information by irradiation with an ultraviolet ray and a second nonvolatile memory (EEPROM) 107 for electrically writing information and electrically erasing the written information are provided as the nonvolatile memories. For example, the program data, the dictionary data necessitating a large storage capacity are stored in the EPROM, and data varying as a time goes are stored in the EEPROM.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and in particular to a technique that is effective when applied to a semiconductor integrated circuit device consisting of a one-chip microcomputer. It is something.

[Conventional technology]

A one-chip microcomputer in which a control section, arithmetic section, a storage section, and an input/output section are mounted on the same half-quad board is, for example, published by Masaharu Hayayoe on April 1, 1980, from CQ Publishing Co., Ltd. As described in his book ``Basics of one-chip microcontrollers and their applied technology'', they are widely used in industrial and home appliances as inexpensive and highly functional control elements. The storage unit of the one-chip microcomputer is an RO in which programs for various information processing, dictionary data, etc. are stored.
M (Read Only Memory) and RAM (Random Access Memory), which temporarily stores programs being executed and data in the middle of calculations.
).

As the ROM, a mask ROM is usually used in which data is written during the manufacturing process, but in order to facilitate system debugging etc., an EPROM (Erasable and
Programi+able ROM) is also widely used. Since the data in EPROM can be erased by irradiating it with ultraviolet light, the information can be rewritten any number of times, making it possible to obtain a one-chip microcomputer with a large degree of freedom.

[Problem to be solved by the invention]

The inventor of the present invention discovered the following problems as a result of studying a one-chip microcomputer equipped with an EPROM as a ROM.

Data in the EPROM is rewritten by irradiating it with ultraviolet light. Therefore, after the one-chip microcomputer is installed in an electronic device, the information in the EPROM cannot be easily rewritten. For this reason, the EPROM has a problem in that it cannot store data that changes over time, such as control data for electronic devices that undergo feedback control. Since the data for feedback control must be stored in the 1-chip microcomputer in preparation for restarting operation even after the electronic device's power is cut off, it is inevitable that it will be stored in non-volatile memory. It is necessary to keep it.

Therefore, EEPROM (Electrically
Easy and programmable
It is conceivable to use ROM). This E E P
If it is a ROM, the data therein can be rewritten even on the system according to a control signal from a control section of a one-chip microcomputer, and the data can be stored even when the power is turned off.

However, EEPROM memory cells have EPR
It has a floating gate electrode like an OM memory cell, and information is stored by injecting carriers into the floating gate electrode.
Forming the gate insulating film under the gate electrode of the MISFET with a two-layer film of a silicon oxide film and a silicon nitride film, and storing information by trapping carriers in the trap level between the silicon nitride film and the silicon oxide film. There are two types of memory cells: one in which data is stored in a storage MISFET, and the other in which a storage MISFET is used during write, erase, and read operations. Two MISFETs with a switch MISFET to connect to the data line
Therefore, there is a problem that the memory cell size becomes large. Therefore, despite the excellent functionality of the EEPROM, it is difficult to install an EEPROM in order to store a large amount of non-volatile information in a single-chip microcomputer with a limited chip size. .

In addition, M for storage in the memory cell of EEPROM
Writing and erasing information in an ISFET is performed by applying a high voltage to a thin tunnel insulating film and using a tunnel current flowing through the tunnel insulating film. Therefore, the reliability of the thin tunnel insulating film becomes a problem, and the large capacity of EEPROM is There was a problem that it was desirable to aim for

An object of the present invention is to provide a technology that can improve the functionality of a semiconductor integrated circuit device consisting of a one-chip microcomputer by increasing the degree of freedom of the ROM included in the device. .

Another object of the present invention is to provide a technique that can reduce the manufacturing process of a semiconductor integrated circuit device consisting of a microcomputer equipped with an EPROM and an EEPROM.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a semiconductor integrated circuit device constituting a microcomputer that includes a central processing unit on one semiconductor chip and a nonvolatile memory in which program data, dictionary data, etc. of the central processing unit are stored, the nonvolatile memory There is a first nonvolatile memory in which information is electrically written and the written information is erased by irradiation with ultraviolet rays, and a second nonvolatile memory in which information is electrically written and the written information is electrically erased. It consists of two nonvolatile memories.

In addition, an EPROM memory cell is formed in a first region of the semiconductor substrate, and a storage MISFE in the EEPROM memory cell is formed in a second region different from the first region of the semiconductor substrate.
manufacturing a semiconductor integrated circuit device constituting a microcomputer, comprising the steps of forming a switch MISFET in a memory cell of the EEPROM in a third region adjacent to the second region of the semiconductor substrate; 1. A method of manufacturing a first semiconductor substrate. forming a first gate insulating film on the surfaces of the second and third regions, respectively; forming a source and a drain in predetermined portions under the first gate insulating film in the second and third regions; forming a floating gate electrode on the first gate insulating film in the first and second regions and forming a gate electrode on the first gate insulating film in the third region; forming a second gate insulating film on the surfaces of the floating gate electrodes in the two regions;
forming a control gate electrode on each gate insulating film, and forming a source and a drain in predetermined portions under the first gate insulating film in the first region,
Each of the steps described above is performed in the order described above.

[Effect]

According to the above-mentioned means, program data and dictionary data that require a large storage capacity are stored in an EPROM, and data contents such as control data for feedback control change over time and can be stored even when the power is cut off. Since the control data that needs to be stored is stored in the EEPROM, the functionality of the semiconductor integrated circuit device consisting of a one-chip microcomputer can be improved.

Furthermore, since a part of the process of forming memory cells of an EPROM on a semiconductor integrated circuit device consisting of a one-chip microcomputer and the process of forming a memory cell of an EEPROM are shared, the manufacturing process of the semiconductor integrated circuit device can be reduced.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor integrated circuit device comprising a one-chip microcomputer according to an embodiment of the present invention.

In FIG. 1, 1 is a semiconductor chip on which a microcomputer is constructed, including a CPU (microprocessor) 100, an OSC (oscillator) 101, an l10 (input/output board) 102, an SI (serial interface) 103, and a TIMER. (Timer) 104, EPROM
(Erasable & Programmable Read Only)
memory) 105, Vc, C (voltage control circuit) 106. E
EPROM (Electrically Erasable & Programmable Read Only Memory) 107, SR
AM (Static Random Access Memory) 1
08, DRAM (Dynamic Random Access Memory) 109, Engineering/○BUS (I/O Bus) 11
0.

The CPU 100 is composed of a control section, an arithmetic section, and various registers. Although not limited to this, the 05CIOI uses a crystal resonator Xta12 provided outside the semiconductor chip 1 to form a highly accurate reference frequency signal, and the CPU 100 uses the reference frequency signal formed here. form the clock pulses needed at The device 10102 includes a data transfer direction register therein. EPROM105, EEPROM1
07, SRAM 108, and DRAM 109 include control circuits necessary for reading, writing, or erasing information from the storage element. V,, C106 is E P R
OM2O3 (7) Controls the word line voltage or data line voltage necessary for the write operation and the write/erase operation of the EEPROM 107. 51103 is serial
It consists of three terminals: clock, serial in, and serial out, and a register with specified bits, and is used as an input/output port for data transfer between microcomputers when multiple microcomputers are used. Ru. TIMER 104 is used to set the time required for multiple processing such as interrupt processing. These CPU100, l10102.511
03, TIMER104, EPROM105, VC, C
106, EPROM105, SRAM108, DRAM
109 is an I 10 B U 5 centering on the CPU 100.
interconnected by ilo. In addition, I 10
B U 51101t, data bus, address bus,
It consists of three control buses.

The EPROM 105 stores programs for various information processing, dictionary data, and the like. and.

The EPROM 105 is used to store programs, dictionary data, etc. that require a relatively small number of data rewrites and require a large capacity. EEPROM107
In addition to storing programs and dictionary data for various information processing, control data for feedback control that changes over time, programs being executed, data in the middle of calculations, data in registers of the CPU 100, etc.
It is also used to store data that needs to be stored even when the power is turned off. In addition, the EEPROM 107 stores EPRO files such as programs and dictionary data for various information processing.
Among the data that can be stored in the M105, the data is frequently rewritten and is used to store data whose data capacity is not small.

The write operation of the EPROM 105 is performed in the following steps.

That is, various control signals output from the CPU 100 put the EPROM 105 into a writable operating state and operate the voltage control circuit (VcXC) 106 to control the externally applied write voltage or the normal operation of the microcomputer. A predetermined word line voltage or data line voltage is generated depending on the applied voltage.

Next, the CPU 100 inputs data directly input to the EPROM 105 from the outside via the processor 10102 or once R
Based on the data input via AM (SRAM 108, DRAM 109), predetermined data is written to a predetermined address of EPROM 105. EPROM 105
After writing various data to the CPU 100
is the write operation of EPROM 105 and voltage control circuit 1
06 operation is completed.

Next, the write and erase operations of the EEPROM 107 will be explained.

Writing and erasing operations of the EEPROM 107 are performed using the CP
The EPROM is controlled by various control signals output from U100.
105 into an operating state capable of writing or erasing, the voltage control circuit 106 is operated to set a predetermined word line voltage or Generate data line voltage. Next, CPU1
00 is E E P directly from outside the city via Engineering 10102.
Data input to ROM107 or once to SRAM
Based on the data input through 108 and DRAM 109, predetermined data is written or erased at a predetermined address of EEPROM 107, or data is rewritten. After writing, erasing, or rewriting various data to this EEPROM 107, the CP
U100 ends the writing or erasing operation of the EEPROM 107 (7).

The normal operation of the microcomputer of this embodiment is based on various control signals, EPROM2O3 and EPROM105.
Based on the programs and dictionary data stored in l1.
After performing predetermined processing on the various data input to 0102, the data is output from l10102 to the outside. Here, among the various data input to the l10102, data that has undergone predetermined processing, or data in the register of the CPU 100, data that needs to be stored even when the power is turned off, that is, re-operation after the power is turned off. Each of the above-mentioned data that is required at a certain time is stored at a predetermined address according to the operation procedure of the EEPROM 107 described above.

The storage in the EEPROM 107 may be performed by storing intermediate data in the EEPROM 2O3 for each process, or by storing the final data in the EEPROM 107 after a predetermined process is completed. good.

On the other hand, when the microcomputer of this embodiment experiences an abnormal power cutoff due to an accident, the microcomputer collects various data necessary to restart operation, that is, l1010.
2, data that has undergone predetermined processing, or predetermined data among the data in the register of the CPU 100 is stored at a predetermined address according to the operation procedure of the EEPROM 107 described above. In this way, the microcomputer of this embodiment maintains the EEP even when the power is cut off.
In order to operate the ROM 107 normally, it has a power supply voltage backup circuit that supplies the voltage necessary for its operation. Although this power supply voltage backup circuit is not particularly limited, it may be composed of a capacitor and a control circuit, and may be configured on the same semiconductor chip as the microcomputer of this embodiment, or it may be constructed on the same semiconductor chip as the microcomputer of this embodiment. It may also be configured on an electronic device that includes the same power source.

Next, using FIG. 1 and FIG.
The circuit operation will be explained.

FIG. 3 is an equivalent circuit diagram showing a schematic configuration of the circuit of the EPROM 105 installed in the microcomputer of this embodiment.

The EPROM 105 of the microcomputer of this embodiment has a logic voltage system such as a power supply voltage Vcc of 5V, and a write voltage Vpp or a high voltage of more than ten V obtained by boosting or stepping down the write voltage VPP by a voltage control circuit 106. Voltage ■. The operating power supply is a write voltage system consisting of . During a normal read operation, the 6EPROM 105, which is operated by a logic voltage system, receives address signals supplied through the address input terminals Xo to Xi and Yo to Yj, and chip signals supplied through the control terminals CE, OE, and PGM. Its operation is controlled by an enable signal, an output enable signal, and a program signal. These control signals are relayed or formed by a control circuit in the EPROM 105 (not shown) under the control of the CPU 100.

The EPROM 105 in this embodiment performs read or write operations for memory cells in units of 8 bits. The memory cell array M-ARY performs electrical writing,
Multiple MI 5FETQ erased by ultraviolet irradiation,
It is composed of pl to Q E P 4, a plurality of word lines including word lines WO to W1, and a plurality of data lines including data lines DO to D1. Memory cell array M-A
MISFETQI placed in the same row in RY:
, Qgpz to QgPffl Q5P4 are connected to corresponding data lines Do and Di, respectively. The X address signal and Y address signal supplied from the CPU 100 via the address terminals XO to X1 and YO to Yj are sent to the X address buffers XADB and Y
It is input to address buffer YADB. The address buffers XADB and YADB operate according to the timing signal ce formed by the control circuit C0NT, and
It takes in the address signal supplied from 00, forms a complementary address signal consisting of internal address signals in phase with it and in phase with it, and supplies it to the X address decoder XDCR and the Y address decoder YDCR.

The X address decoder XDCR supplies a selection signal for selecting a word line of the memory cell array M-ARY in accordance with a complementary address signal supplied by the X address buffer XADB. The voltage level of the word line selection signal formed by the X-address decoder XDCR is the voltage 2 supplied from the voltage control circuit 106. . Determined by During a normal read operation, it is set to the power supply voltage VcC level, which is a logic voltage system, and during a write operation, it is set to the Val level, which is a write voltage system.

Y address decoder YDCR is address buffer YA
A complementary address signal supplied by DB forms a selection signal for selecting a data line of memory cell array M-ARY. The selection signal output from the Y address decoder YDCR is MISFE of the Y group 6 circuit YGATE.
TY□1. It is supplied to the gate electrodes of Y2゜Y2□ and Y22. Data line selection is performed by first selecting a plurality of data line groups using MISFETY1□ and Y□2 of the YGATE 6-circuit YGATE, and then by MISFETY2. ,Y
2. A second selection is performed in which a predetermined data line is selected from the data line group. Here, Y goo 6 circuit YGA
By configuring the TE with two MISFETs connected in series, the load capacitance of each MISFET can be reduced, and high-speed read operation is possible. In addition, the voltage level of the data line during normal read operation is set to be lower than the power supply voltage ■aa level supplied to the word line in order to prevent MISFETQ, □ to Q g #4 from being erroneously written during read. set to a low level. More specifically, it is set at a level of 20 to 40% of Vcc. During a write operation, a predetermined voltage corresponding to the Vcx level, which is a write voltage system, is set. Further, each data line Do, Di is coupled to a common data line CD.

Data output circuit DOB is coupled to the common data line via sense amplifier circuit SA. Although the sense amplifier is not particularly limited, in this embodiment, a current mirror type sense amplifier circuit is used. Further, the data output circuit DOB is coupled to input/output terminals DIO to DI7.

The data input circuit DIB has input/output terminals DIO to DI7.
It consists of an input buffer coupled to a

Data is stored in the EPROM 105 using MI 5FETQ, 1 to Q, which are used as memory cells. .

The threshold voltage of
, I+) or a relatively high voltage (logic II
OI+).

Next, using FIG. 1 and FIG.
The circuit operation of No. 7 will be explained.

FIG. 4 is an equivalent circuit diagram showing a schematic configuration of the EEPROM 107 installed in the microcomputer of this embodiment.

EEP installed in the microcomputer of this example
The ROM 107 has a logic voltage system such as a power supply voltage Vcc of, for example, 5V, and a write or erase voltage vpp or a high level such as 10-odd V obtained by boosting or stepping down the voltage VpP or voltage Vcc by the voltage control circuit 106. The write/erase voltage vcx system is used as an operating power supply. A normal read operation is operated by a logic voltage system. EEP ROM2O3 has address input terminals Xo to X
1 and address signals supplied via Yo to Yi, and E, not shown, under control from the CPU 100.
Its operation is controlled by various control signals that are controlled or generated by a memory control circuit in PROM 105.

The EEPROM 107 in this embodiment performs memory read, write, or erase operations in units of 8 bits. The memory array M-ARY includes a plurality of memories that are electrically written and erased.
1 to Q g, S P 4, and the memory MISFET
Switches MISFETQ8 to Q that control read, write, and erase operations of Q---1 to Qgs□
x4, word lines Wt0 to W61 and Wfo to W3,
It is composed of a plurality of word lines including a plurality of word lines, and a plurality of data lines including data lines D0 to D. Memory array M-A
In RY, memories M, I S arranged in the same row
F E T Qgg-z, Qgg-□ to QgE2
7. The control gate electrodes of Q□□ are connected to the corresponding word lines W6o to W, :, respectively, and the switch 1
viISFETQ, 1. Q, 2 to Q I 3 t Q
The 14 gate electrodes are connected to the corresponding word lines W8° to W,1, respectively, and the switches M arranged in the same column
ISF E T Q-1, QCs to Q M 2 #
The drain of Q14 is the corresponding data line.

Connected to D0 to D0. In addition, the switch MISFETQ
, 1 to Q, 4 sources are memory MISFETQg, .
□ to Qfl (connected to P4, memory MISF
The sources of E T Q g g-□ to Q-14 are grounded.

X address signal and X supplied from CPtJloo via address terminals xO to Xi and YO to Yj
Address signals are sent to X and Y address buffers X, Y
Input to ADB. Address buffer XYAD
B operates according to the timing signal formed by the control circuit C0NT, takes in the address signal supplied from the CPU 100, forms a complementary address signal consisting of internal address signals in phase with it and in phase with it, and sends it to X.
Address decoder XDCR and Y address decoder Y
Supply to DCR. Also, address buffer XYADB
has a latch circuit inside, and can temporarily store an address signal in the latch circuit.

The X address decoder XDCR is the address buffer XY
According to the complementary address signal supplied from ADB, a selection signal for selecting two types of word lines of memory array M-ARY is formed.

Y address decoder YDCR is address buffer YA
Data ADD of memory array M-ARY according to the complementary address signal supplied from DB.

A selection signal for selecting D1 to D1 is formed.

The selection signal output from the Y address decoder YDCR is
Supplied to YG8 circuit YGATE. Y goo 8 circuit Y
GATE is not particularly limited, but the third
This is the same system as the YGATE 8 circuit shown in the figure.

The data input/output circuit 10B includes the data line and the input/output terminal D.
It is coupled to IO to DI7. Further, the data input/output circuit IOB is composed of a sense amplifier circuit, a turnout sofa circuit, and a latch circuit for temporarily storing input data.

The data latch circuit and the program circuit DL temporarily store write or erase data supplied from the input/output terminals DIO to DI7, and also store memory cells M I S F E T Q based on the write or erase data.
, , E-1 to Q, , 6- are used for writing and erasing information.

EEPR○M107 of the microcomputer of this example
By providing various latch circuits as described above, it is possible to prevent erroneous writing or erroneous erasing during a writing or erasing operation.

Memory MISFETQ of the EEPROM 107.

As will be described later, each of the transistors 0 to Q S li P 4 includes a floating gate electrode, a tunnel insulating film below the floating gate electrode through which a tunnel current can flow, and a semiconductor region below the floating gate electrode. The write operation is performed by emitting electrons from the floating gate electrodes of the memory MISFETs QgE, □ to Q. This refers to making the threshold voltage of
4 is set higher than the source voltage.

Emission of electrons during writing and injection of electrons during erasing are performed through the tunnel insulating film.

Next, the circuit operation when writing information to the EEPROM 107 will be explained.

First, various control signals issued from the CPU 100
While putting the EPROM 107 into a writable operating state, the writing address is set in the address buffer XY.
Temporarily stored in the ADB latch circuit. Further, write data is temporarily stored in the data latch circuit and the latch circuit of the program circuit DL. Next, write memory M
Word line W8 of switch MISFETQyo to Q□ to which ISFETQ g g p□ to Q5g#4 are connected
The potentials of ゜ to W6 are set to a high voltage that allows writing, and the switches MISFETQ, □ to Q14 are put into an operating state. At this time, all the word lines WE coupled to the memory MI 5FETQ, . . . to Q E g P 4
o to WE□ are set to low voltages of about O■. After this,
Memory MI 5FETQ for writing
E 11 Data line coupled to P 4 via switches MISFETQ, □ to Q□. A high voltage capable of writing is applied to D□ to D□.

Through the above circuit operation, the memory MISFETs Q11 to Q. Since the potential of the semiconductor region under the tunnel insulating film provided under the floating gate electrode of P4 becomes higher than the potential applied to the control gate electrode, the potential becomes even lower than that of the control gate electrode. Electrons in the floating gate electrode are emitted into the underlying semiconductor region through the tunnel insulating film to perform writing.

Next, a circuit operation for erasing information will be explained.

In this embodiment, the erase operation is performed for each word line, although it is not limited thereto. In the erasing operation, first, the EEP
The ROM 107 is put into an erasable operating state, and the word line W
gffi, W61 to W,. , W8, are set to a low voltage level close to ground voltage. At this time, although not limited to, the data ID. , D□ are also set to a low voltage level close to the ground voltage. Next, the word lines W6 . , W61, the word lines W6° to W81 to be erased are set to a high voltage level that allows erasing. When you do these things, the memory M I S F E
Since the voltage of the control gate electrodes from T Qggpt to Q□□ becomes higher than the voltage of the semiconductor region under the tunnel insulating film, electrons in the semiconductor region are injected into the floating gate electrode through the tunnel insulating film. The deletion is performed by

Next, a circuit operation for reading information will be explained.

In the read operation, first, the word lines WEo to W6° connected to the memories MISFETs Qgg2 to Q614 are always kept in a non-selected state close to the ground voltage, and the switch MISFET
A specific memory cell is selected from among a plurality of memory cells by selecting word lines W5° to W,1 and data lines W,1 coupled to ETQ, □ to Q14.

The memory MISFET (Q
Any of g,, p, to Q□□, hereinafter simply Q661
, to Q 6 E P 4 ), the word lines W8o to W6□ are at a low potential as described above, so the memory interlayer 5FETQ,: +:, z to Q 1
1 E # 4 becomes non-conductive, and the corresponding logic I
IOI+ is read out to data lines D0 to D.

On the other hand, the memory MISF of the selected memory cell
If no electrons are injected into the floating gate electrodes of E T Q, , P, to Q E 11 P 4, the memory MISFETQ, , , to Q E
□ becomes conductive, and correspondingly the logic It I I
+ is read out from the data line to D□.

Next, the SRAM 108 and DRAM 109 included in the microcomputer shown in FIG. 1 will be described.

The SRAM 108 is mainly used for storing programs that are being executed or data that is being calculated.
102 is used as a temporary storage circuit for data that needs to be transferred at high speed.

SRAM included in the microcomputer of this embodiment
108 memory cells, as shown in FIG.
4 N-channel M I S F E T2O3,20
4,207,2O8.

Note that FIG. 2 is an equivalent circuit of the memory cell of the SRAM 108 included in the microcomputer according to the embodiment of the present invention shown in FIG.

Note that the memory cell of the SRAM 108 may be configured with two high-resistance resistance elements and four MISFETs. The DRAM 109 is mainly used as a temporary storage circuit for data that does not require high-speed data transfer with the CPU 100 or the 10102, and that requires a large capacity of memory, mainly for programs being executed or data in the middle of calculations. It will be done. The memory cell of the DRAM 109 of this embodiment is composed of a capacitor section that stores charge and a switch MISFET that controls the capacitor section. In this way, the RAM of the microcomputer of this embodiment is SR.
Composed of AM108 and DRAM109, SRAM108 is used to store data that has a small data capacity but requires high-speed data transfer, and SRAM108 is used to store data that does not need to be transferred at high speed but has a large capacity. is DRA
Use M109. The SRAMIO3 operates as a so-called cache memory.

High-speed data transfer is performed with the CPU 100.

The DRAM 109 in this embodiment is not operated by applying a negative potential lower than the ground potential Vss, for example, O■, which is a reference potential for the electrical operation of the circuit, to the substrate 1. This is because when a negative potential lower than the ground potential Vss is applied to the substrate 1 as described above, the EPROM 105 or EEPROM 107 normally operates without making the substrate 1 a negative potential.
However, the characteristics of the MI 5FET constituting the other components will change.

However, if the region of the substrate 1 where the DRAM 109 is configured is electrically isolated from the region where other MISFETs such as the EPROM 105 and the EEPROM 107 are configured, the negative potential cannot be applied to the substrate 1. It may be operated by applying the voltage. That is, as described later, DRAM109 and other EEPROM2O3,E
The P ROM2O3 and the like may be provided in separate P-type well regions, and the P-type well regions may be electrically isolated.

The refresh operation of the DRAM 109 is performed under the control of the CPU 100. Further, the potential of the word line of the DRAM 109 is set to a higher potential than Vcc, which is a logic voltage, for operation. This voltage is generated by a voltage control circuit 106.

Next, the structure of each MISFET constituting the microcomputer of this embodiment is shown in FIGS. 5a and 5b.
This will be explained using FIG. 5c.

FIG. 5a is a cross-sectional view of the MISFET that constitutes the EPROM 105 included in the microcomputer shown in FIG. 1, and FIG. The cross-sectional view, FIG. 5c, shows the MISFE that constitutes the CPU 100, l10102, etc. included in the microcomputer shown in FIG.
It is a sectional view of T.

In FIG. 5a, Ql is a MISFET that constitutes a memory cell of the EPROM 105, and O2 is a MISFET that constitutes the memory cell of the EPROM 105.
The N-channel MISFET O3 that constitutes peripheral circuits such as the address buffer and decoder of M105 is the EPRO
This is a P-channel MISFET that constitutes peripheral circuits such as the address buffer and decoder of M105. EPROM1
05(7) Memo The MISFET QI constituting the IJ cell is provided in the p-type well region 3 on the main surface of the semiconductor substrate 1 made of p-type single crystal silicon, and has a first gate insulating film 6 made of a thin silicon oxide film. A floating gate electrode 7A made of, for example, a polycrystalline silicon film, a second gate insulating film 8A made of a thin silicon oxide film, and a tungsten silicide film (WSi) formed on, for example, a polycrystalline silicon film.
2), an n-type semiconductor region 11A forming the channel region side portion of the source and drain, and the n-type semiconductor region 11A forming the channel region side portion of the source and drain;
The n° type semiconductor region 13A constitutes a portion other than the n° type semiconductor region 11A. The thickness of the first gate insulating film 6 is, for example, about 500, and the thickness of the second gate insulating film 8A is, for example, about 350. The n-type semiconductor region 11A
This is for increasing the generation of hot carriers and improving the information writing characteristics.

Note that the control gate electrode 9A is also a word line. The side surfaces of the floating gate electrode 7A and the side surfaces and top surface of the control gate electrode 9A are covered with a thin silicon oxide film 10. A side wall 12 made of a silicon oxide film is provided on the sides of the floating gate electrode 7A and the control gate electrode (word line) 9A.

The memory cells Q1 in the direction in which the word line extends are separated by a field insulating film 4 made of a silicon oxide film and a p-type channel stopper region 5 therebelow. A data line 16D is connected to the Go-type semiconductor region 13 that forms part of the drain when reading information. The data line 16D is made of aluminum film, for example.
Aluminum is the main component with additions of silicon, steel, baladium, etc., or silicide films (MoSi, TaS, etc.) are added below or above these films.
i2. T i S i2. It consists of a multilayer film provided with WS i, etc.). 14 is a first layer passivation film, such as a silicon oxide film formed by CVD, a phosphosilicate glass (PSA) film, a boron-doped PSG (BPSG) film, a silicon oxide film formed by plasma CVD, or a laminated film of these. It is formed of. 15 is a connection hole. A second layer passivation film 17 is made of a silicon oxide film formed by a plasma CVD method, a spin-on-glass film formed by a spin coating method, or the like. The N-channel MISFET Q2 constituting the peripheral circuit has a gate insulating film 6, a gate electrode 7B made of, for example, a polycrystalline silicon film, and a source.

n-type semiconductor region 11 forming the channel region side of the drain
B, and an n° type semiconductor region 13B forming a portion other than the source and drain A type semiconductor regions 11B. The type 1 semiconductor region 11B suppresses the generation of hot carriers at the end of the drain, and
This is to prevent the electrical characteristics of the device from changing. The side and top surfaces of the gate electrode 7B are covered with a thin silicon oxide film 10. A contact hole 15 made of an aluminum film is inserted into the n° type semiconductor region 13B on the drain side. 16 are connected. The Go-type semiconductor region 13 is provided at a predetermined distance from the sidewall 12 in order to improve the breakdown voltage of the drain.

P-channel MI 5FETQ3 that constitutes the peripheral circuit
is provided in the rectangular well region 2 on the main surface of the semiconductor substrate 1, and includes a gate insulating film 6, a gate electrode 7B made of, for example, a polycrystalline silicon film, and a source.

p“ type semiconductor region 1 forming the channel side portion of the drain
1C, and the p-type semiconductor regions 11 of the source and drain.
It is composed of a p° type semiconductor region 13C forming a portion other than C. A wiring 19 is connected to the wiring 17 through a connection hole 18 . This distribution! 1A19 is made of the same material as the wiring 17. Although not shown, a final passivation film made of a PSG film, a silicon nitride film formed by plasma CVD, or the like is provided on the wiring 19.

The floating gate electrode 7A of the memory cell Q1, the gate electrode 7B of the N-channel MISFETQ2, and the gate electrode 7B of the P-channel MISFETQ3 are made of the same first-layer conductive film. The gate electrode 9A of the memory cell Q2 is made of a second layer conductive film. Also, memory cell Q1, N-channel MISFET Q2 . P
Each gate insulating film 6 of channel MISFET Q3
The film thicknesses are kept the same.

In FIG. 5b, Q4 is a memory MISFET Q, , □ to Q E in the memory cells of the EEPROM 107.
The N-channel MISFET Q5 constituting E P4 is the switch M in the memory cell of the EEPROM 107.
ISFETQ, □ to Q*4 or EEPR○M10
N-channel MI 5FET, Q6, which constitutes peripheral circuits such as the address buffer and decoder of 7 is EEPRO
P-channel MISFET that constitutes the peripheral circuit of M107
It is.

The N-channel MISFET Q4 has a first gate insulating film 6 made of a silicon oxide film as thin as 500 mm, and a gate insulating film 6 of about 10
An insulating film 21 made of a silicon oxide film with a thickness of about 0.00 to 2,000 people, a tunnel insulating film 22 made of a very thin silicon oxide film of about 100 people, and a floating gate electrode 7C made of, for example, a polycrystalline silicon film. 350
It is composed of a second gate insulating film 8C made of a thin silicon oxide film, a control gate electrode 9C formed integrally with the word line, and an n-type semiconductor region 20 serving as a source and a drain. Side surface of floating gate electrode 7C and control gate electrode vi (word line)
The side and top surfaces of 9G are covered with a thin silicon oxide film 10. The insulating film 21 is for relaxing the electric field at the end of the floating gate electrode 7C and improving the breakdown voltage. The N-channel MISFET Q5 for configuring the switch MISFET of the memory cell or the peripheral circuit is:
It is composed of a gate insulating film 6, an insulating film 21, a gate electrode i7B made of, for example, a polycrystalline silicon film, and an n-type semiconductor region 20 that becomes a source and a drain.

The side and top surfaces of the gate electrode 7B are covered with an insulating film 10. A wiring 1 is inserted through the connection hole 15 into the n-type semiconductor region 20 that becomes the drain of the N-channel MI 5FETQ5.
6D is connected. The wiring 16D is a data line in the memory cell, and is a MISFE line in one peripheral circuit.
This is the signal wiring that connects between T.

The P-channel MISFET Q6 constituting the peripheral circuit includes a gate insulating film 6, a gate electrode 7B, and a p-type semiconductor region 1 forming the source and drain portions on the channel region side.
1C, and the p” type semiconductor regions 11 of the source and drain.
It is composed of a p° type semiconductor region 13C forming a portion other than C. The side and top surfaces of the gate electrode 7B are covered with an insulating film 10.
is covered. A wiring 816 is connected through the connection hole 15 to the p-type semiconductor region 13C forming a part of the source region. The p° type semiconductor region 13C is provided at a predetermined distance from the sidewall 12 in order to improve the breakdown voltage of the source region.

Note that a wiring 19 made of a second layer of aluminum film covers the N-channel MISF'ETQ4 of the memory cell and the N-channel MISFETQ5 forming the switch element. That is, the entire memory cell array area is connected to the wiring 19.
covered with This is when erasing the data stored in the EPROM 105 by irradiating it with ultraviolet light.
This is to prevent the data stored in M107 from being erased by the ultraviolet rays.

In addition, between the floating gate electrode 7C of the memory element Q4 and the MISFET 5. The gate electrode 7B of Q6 is
2. Between floating gate electrode 7A of memory cell Q1 of PROM 105 and MISFET. Gate electrode 7 of Q3
It is formed of the same first layer conductive film as B. EEPR
The control gate electrode 9C of the memory MISFETQ4 of the OM107 is made of the same second-layer conductive film as the control gate electrode 9A of the EPROM105.

In FIG. 5C, Q7 is an N-channel MISFET that configures the CPU 100, and Q8 is an N-channel MISFET that configures the l10102 and SI (serial interface) 103.
Channel MISFET Q9 is a P-channel MISFET for configuring CPU 100. The N-channel MISFET Q7 has a gate insulating film 8D made of a silicon oxide film as thin as 250 mm, a gate electrode 9D, a semiconductor region 11B forming the channel region side of the source and drain, and It is composed of an n° type semiconductor region 13B forming a portion other than the n type semiconductor region 11B. The N-channel MISFET Q8 is
Gate insulating film 8D, gate electrode 9D, and source.

An n-type semiconductor region 11A forming a portion on the channel region side of the drain, and the n-type semiconductor region 11 of the source and drain.
It is composed of an n° type semiconductor region 13B forming a portion other than A. The n-type semiconductor region 11A is for preventing the MISFET gap 8 from being destroyed when an abnormally high voltage is applied to the drain region. Said P channel MI
SFETQ9 has a gate insulating film 8D and a gate electrode 9D.
And the sauce.

It is composed of a P-type semiconductor region 11G forming a portion of the drain on the channel region side, and a p°-type semiconductor region 13C forming a portion of the source and drain other than the p-type semiconductor region 11C.

In addition, MISF, ETQ7. Q8. Each gate electrode 9D of Q9 is made of the same second layer conductive film as the control gate electrode 9A of the EPROM 105 and the control gate electrode 9C of the EEPROM 107.

Furthermore, the N-channel MISFET and P-channel MISF that constitute the memory cell of the SRAM 108 shown in FIG.
ET is an N-channel MISFET Q7 and a P-channel MISFET that constitute the CPU (logic section) 100 shown in FIG. 5C.
It has the same structure as SFETQ9.

Next, the MISFETQI, Q2. Q3. Q4, Q5
．． Q6. Q7. Q8. Each manufacturing method of Q9 is shown in the fifth
This will be explained using FIG. a, FIG. 5b, FIG. 5c to FIG. 22a, FIG. 22b, and FIG. 22c.

Figures 5a, 5b, 5c to 22a, 22
Figures b and 22c show an E P ROM 105. of a microcomputer according to an embodiment of the present invention. E E PROM
FIGS. 5a to 22a are cross-sectional views of the region where the MISFETs forming the memory cells of the EPROM 105 and their peripheral circuits are provided, and FIG.
Figures 22b to 22b are cross-sectional views of the memory cells of the EEPROM 107 and the region where MISFETs constituting their peripheral circuits are provided, and Figures 5c to 22c are CP Uloo
FIG. 11 is a cross-sectional view of a region where MISETs constituting I10102 and I10102 are provided.

Note that the P-channel MISFET and N-channel MISFET that constitute the memory cell of the SRAM shown in FIG. 2 are the same as the N-channel MISFET that constitutes the logic section shown in FIG. 4C.
Since it is formed using the same creation method as FETQ7 and P-channel MISFETQ9, the explanation will be omitted.

EPROM 105 of the microcomputer of this embodiment,
E E P ROM2O3, CP Uloo and l1
The method for manufacturing the MISFET constituting 0102 is described in Section 6a.
As shown in FIGS. 6 to 6c, ion implantation and annealing are performed on each predetermined region of the main surface of a p-type semiconductor substrate (chip) 1 to form a type 1 well region 2 or a p-type well region 3. do. 50 is a thin silicon oxide film used as a buffer film when performing the ion implantation. Next, as shown in FIGS. 7a to 7c, predetermined regions of each of the type 1 well region 2 and p'' type well region 3 are thermally oxidized using a well-known technique to form a field insulating film 4. Then, a p channel stopper region 5 is formed in the p-type well region 3. A silicon nitride film 51 is used as a mask for thermal oxidation when forming the field insulating film 4. Next, a silicon nitride film 51 is formed. is removed, and the silicon oxide film 50 used as the base film is removed to form an n-
After exposing the portions of the type well region 2 and the P-type well region 3 that cannot be covered with the field insulating film 4, the exposed surfaces are thermally oxidized again to form gates as shown in FIGS. 8a to 8c. Next, as a mask for ion implantation when forming the n-type semiconductor region 20 which will become the source and drain of the N-channel MISFET of the memory cell of the EEPROM 107 and its peripheral circuit shown in FIG. 8b, A resist film 52 is formed on the π-type well region 2 and the p-type well region 3. Next, an n-type impurity, such as arsenic (As) ion, is added at 1014 to 10'' atoms/
The n-type semiconductor region 20 is formed by introducing about a#. After this, the resist film 52 is removed. Next, as shown in FIGS. 9a to 9c, the n-type semiconductor region 2 is thermally oxidized.
An insulating film (S i O,) 21 is formed on top of the silicon wafer 0 . Since the insulating film 21 has the heavily doped n-type semiconductor region 20 at the bottom thereof, a thick insulating film can be obtained.

At this time, the thickness of the oxide film is set so that the thickness of the gate insulating film 6 is approximately 500 people. The thickness of the insulating film 21 is about 1000 to 2000A.

Alternatively, after removing the gate insulating film 6, one-time thermal oxidation is performed to form an insulating film of about 500 people and 10oO~2
The insulating films on the upper portions of the n-type semiconductor regions 20 may be formed at the same time. Next, in order to etch the portion of the insulating film 21 where the tunnel insulating film 22 of the memory MISFET Q4 of the EEPROM 107 is provided, a resist film 54 is formed as a mask, as shown in FIGS. 10a to 10c. Next, as shown in Figure 10b,
A portion of the insulating film 21 where the tunnel insulating film 22 is to be formed is etched to expose the surface of the n-type semiconductor region 20.

After this, the resist film 54 is removed. Next, the surface of the n-type semiconductor region 20 exposed by removing the insulating film 21 in the previous step is thermally oxidized to form a tunnel insulating film 22 made of a silicon oxide film. Tunnel insulation film 22
The film thickness is about 100 people. Next, EPROM10
Floating gate electrode 7A of memory cell Q1 of No. 5,
Peripheral circuit MISFETQ2. Gate electrode 7B of Q3 and memory MISFET of memory cell of EPROM 105
Q4 floating gate electrode C9 switch MISFET of the memory cell and MISFET Q of the peripheral circuit
In order to form the gate electrode 7B of No. 5, a polycrystalline silicon film 7 is formed on the n-type well region 2 and the p-type well region 3 by, for example, CVD, as shown in FIGS. 11a to 11c. . An n-type impurity such as phosphorus (P) is introduced into this polycrystalline silicon film 7 by thermal diffusion, ion implantation, etc. to lower the resistance.

Next, as shown in FIGS. 12a to 12c, the polycrystalline silicon film 7 is patterned to form the EPROM 10.
Floating gate electrode 7A of memory cell Q1 of No. 5,
Gate electrode 7B of peripheral circuit, floating gate electrode 7C of memory MISFETQ4 of EEPROM107
, EEPROM107 memory cell switch M
Gate electrodes 7B of ISFET2 (and MISFETQ5, Q6 in the peripheral circuit) are formed respectively.
Since the gate electrode is formed from a second layer conductive film to be formed later, the first Ff1 polycrystalline silicon film 7 is removed and does not remain in the region for forming these MISFETs Q7 to Q9.

Here, the floating gate voltage 1! of the memory cell Q1 of the EPROM 105 shown in FIG. 12a! i7A has a long extending pattern in the direction in which the data line extends without being divided into floating gate electrodes 7A of individual memory cells. However, in the direction in which the word line extends, the floating gate electrodes 7A of adjacent memory cells are separated into patterns. This is because when the control gate electrode (word A11) 9A is later formed thereon, the floating gate electrode 7A, which extends long in the direction in which the data line extends, is patterned a second time. This is to form a predetermined pattern.

On the other hand, the memory MI of the memory cell of the EEPROM 107
The floating gate electrode 7C of SFETQ4 has a pattern separated for each individual memory cell. Next, as shown in FIGS. 13a to 13c, the EP
ROM105 floating '7'-to fiH+i7
A and the surface of the floating gate electrode 7C of the EEPROM 107 are thermally oxidized to disconnect the second gate.
form C. When forming the second gate insulating films 8A and 8C, the surfaces of the other gate/first shields 7B are also thermally oxidized to form a thin silicon oxide film 8. Next, C.P.
After covering the parts other than the U100 area and the l10102 area with the resist film 55, the CPU U100 area and the area 101
The thin silicon oxide film (gate insulating film) 6 formed in the 02 region is removed by etching. Next, the 14th a
As shown in FIGS. 14c to 14c, first the silicon oxide film 6 is
The CPU 100 region and l10102 region exposed by etching are thermally oxidized to form a gate insulating film 8D of MI S FET for forming cpUloo and T10102. When forming this gate insulating film 8D, each floating gate electrode 7A
, 7C and the surfaces of the gate electrode 7B are oxidized, and the thicknesses of the second gate insulating films 8A, 8C and the silicon oxide film 8 are increased.

Here, the film thickness of the second gate insulating films 8A and 8C is set to be approximately 350 people. Further, the film thickness of the gate insulating film 8D is set to be the optimum film thickness for the CPU 100 and the MI S FETs Q7 to Q9 that constitute the device 10102. Note that the gate insulating film 6 of the MISFET that constitutes the memory cells of the EPROM 105 and EEPROM 107 and their peripheral circuits, and the gate insulating film 8D of the MISFET that constitutes cpUloo and l10102 are
In order to set the optimum value for the FET, the gate insulating film 6 may be formed thicker, and the gate insulating film 8D may be formed thicker. Furthermore, the gate insulating film 6 and the gate insulating film 8D may be formed to have the same thickness.

After forming the gate insulating film 8D, a second conductive film 9 is formed over the entire surface of the semiconductor chip 1. This conductive film 9 is composed of a two-layer film in which, for example, a polycrystalline silicon film is formed by CVD, and a silicide film is further laminated thereon by sputtering. N-type impurities such as phosphorus CP) are introduced into the polycrystalline silicon film by ion implantation or thermal diffusion to lower the resistance.

Next, as shown in FIGS. 15a to 15c, the conductive film 9 is patterned using the resist film 72 as a mask, and the EE
Control gate electrode (word line) of memory MISFETQ4 of PROM107 9C1MISFETQ7. Q
8. A gate electrode 9D of Q9 is formed. Next, the 16th a.
As shown in FIGS. 16c to 16c, a resist film 73 is formed. In this state, memory cell Q1 of EPROM 105
control gate electrode 9A, second gate insulating film 8A
, the floating gate electrode 7A is etched to form floating gate electrodes 7A divided into individual memory cells also in the direction in which the data lines extend, as shown in FIGS. 17a to 17c. After that, the resist film 73 is removed. Next, FIGS. 18a to 18c
As shown in the figure, EPROM105 and EEPROM10
7 each control gate electrode (word line) 9
The surfaces of A and 9D are thermally oxidized to form a thin silicon oxide film 10. At this time, other MISFETQ2. Q3. Q
5. Q6, Q7. Q8. The surfaces of gate electrodes 7B and 9D of Q9 are also oxidized to form a silicon oxide film 10.

The area of the memory cell Q1 of the EPROM 105 and the area of the memory cell Q1
A resist film 56 with an opening in the region of MISFET Q8 of 02 is formed, and a p-type well and a p-type well are formed by ion implantation.
By introducing an n-type impurity, for example, arsenic (As) into region 3, the sources of memory cell Q1 and N-channel MISFET Q8,
An n-type semiconductor region 11A that will become a part of the drain is formed. The dose of impurity ions introduced at this time is, for example, 101 satoms/-. Thereafter, the resist film 56 is removed, and as shown in FIGS.
A resist film 57 is formed which has an opening in the region where the N-channel MISFET Q7 for forming the transistor 0 is provided. Then, by ion implantation, an n-type impurity such as phosphorus (P) is added.
is introduced, and the N-channel MISFETQ2. n-type semiconductor region 11B that becomes part of the source and drain of Q7
form. The dose of impurity ions introduced at this time is, for example, 101013ato/aj. After this, the resist film 57 is removed. Next, as shown in FIGS. 20a to 20c, the EPROM 105, EEPR
P-channel MISFETQ3. for configuring each peripheral circuit of OM107. The area where Q6 is provided and C
P-channel MISFETQ for configuring PU100
A resist film 58 is formed which has an opening in the region where 9 is provided. Then, a p-type impurity such as boron (B) is introduced by ion implantation to form the P-channel MISFETQ.
3. Q6. A p-type semiconductor region 11C which becomes part of the source and drain of Q9 is formed. The dose of impurity ions at this time is about 1, for example, 10"3 atoms/d. Thereafter, the resist film 58 is removed. Next, as shown in FIGS. 21a to 21c, each gate electrode 7A is , 9A, 7B, 7C, 9C and 9D (7) sidewalls 12 made of a silicon oxide film are formed using, for example, CVD and reactive ion etching.Next, P channel MISFETs Q3 and Q9 and EEP
A resist film 59 covers a region where an N-channel MI 5FET for forming a memory cell of the ROM 107 and its peripheral circuit is provided. In addition, in order to increase the withstand voltage of the drain of the N-channel MISFET Q2 in the peripheral circuit of the EPROMIO3, in order to separate its high concentration portion from the sidewall 12 and the field insulating film 4 by a predetermined distance,
A resist film 59 is formed. Then, an n-type impurity such as arsenic (As) is introduced into the go-type semiconductor region 1 by ion implantation.
3A and 13B are formed. After this, the resist film 59 is removed. Next, as shown in FIGS. 22a to 22c, each of the N-channel MISFETs Q1. Q2. Q4
, Q5. Q7. Q8 is covered with a resist film 60, and the P channel MI 5F of the peripheral circuit of the EEPROM 107 is covered with a resist film 60.
In order to increase the withstand voltage of the drain of ETQ6, a resist film 60 is formed in an iridescent manner with its high concentration portion separated from the sidewall 12 and field insulating film 4 by a predetermined distance.

Then, a p-type impurity such as boron (B) is introduced by ion implantation to form each p'-type semiconductor region 13. After this, the resist film 60 is removed. After this, 5th a.
As shown in FIGS. 5c to 5c, the passivation film 14
For example, silicon oxide film by CVD, PSA film, BP
A silicon oxide film formed by SG film sputtering or a laminated film of these films is used to form the film. Next, passivation film 1
4 is selectively removed to form a contact hole 15, and then annealing is performed at a temperature of about 1f900° C. to glass flow the passivation film 14 in order to reduce the step difference in the contact hole 15 portion. On the passivation film 14, an aluminum film or an aluminum alloy film containing aluminum as a main component and to which silicon, steel, palladium, or the like is added is formed by, for example, a sputtering method, a CVD method, or a vapor deposition method.

Alternatively, a silicide film (Mo
S i2. TaSi2. TiSi,,
After forming the WS iz), these films are patterned to form the wiring 16. Data 116D is formed. Note that the silicide film is formed on the passivation film 14 before forming the aluminum film or aluminum alloy film,
The aluminum film or the like may be formed thereon. After forming wiring 16.18D.

For example, the passivation film 17 is formed by stacking a silicon oxide film formed by plasma CVD, a spin-on-glass film formed by spin coating, and a silicon oxide film formed by plasma CVD in order from the bottom. Next, the passivation film 17 is selectively removed to form the connection hole 18. The connection hole 18 has a wiring layer 1 formed of a low melting point aluminum film or the like below.
Because of the 8.16D, it is not possible to reduce the level difference by glass flow, so first, the passivation film 17 is removed by isotropic etching such as wet etching.
The film is etched to about half the film thickness, and then the remaining half is etched using anisotropic dry etching.

Next, on the passivation film 17, the wiring 16.
The wiring 19 is formed using the method used to form the LSD. Next 1
Although not shown, a PSG film and a silicon nitride film are formed as the final passivation layer.

In addition, FIGS. 13a to 13c and FIGS. 14a to 1
．． As shown in Figure 4c, MISFETQ7. The gate insulating film 8D of the MISFET Q8 for configuring the MISFET Q9 and 110102 is formed by first forming the second gate insulating film 8A of the EEPROM 2O3 (7) and the second gate insulating film 8G of the EEPROM 107, and then forming the gate insulating film 8D of the MISFET Q7. The thin silicon oxide film 6 previously formed in the regions of Q8 and Q9 was removed by etching, and then formed using a dedicated thermal oxidation process.
MI before forming the second gate insulating film 8C of OM107.
SFETQ7. Q8. The thin silicon oxide film 6 in the region Q9 is etched, and then the E PROM and E
When forming the second gate insulating films 8A and 8C of the EPROM 107, MISFETQ7. The gate insulating film 8D may be formed by oxidizing the Q8 and Q9 regions.

Furthermore, the manufacturing method of this embodiment is applicable to the first gate insulating film 6 of the memory cell Q1 of the EPROM 105 shown in FIGS. 8a to 8c, and the first gate insulating film of the memory MISFET Q4 of the memory cell of the EEPROM 107. 6 are formed at the same time, but they may be formed in separate steps so that their film thicknesses are slightly different.

Next, a method of manufacturing a DRAM memory cell provided in the microcomputer of this embodiment shown in FIG. 1 will be described.

23 to 26 are cross-sectional views of the DRAM memory cell provided in the microcomputer of this embodiment shown in FIG. 1 during the manufacturing process.

First, the cross-sectional structure of the memory cell of the RAM will be explained using FIG. 23.

As shown in FIG. 23, a DRAM memory cell has p-
It is provided in the mold well region 3. Further, Q is a switch MISFET of the memory cell, and C is a capacitive element of the memory cell. The switch MISFETQ has a gate insulating film 8D made of a silicon oxide film and a silicide film (MoSi, TaSi, etc.) on a polycrystalline silicon film, for example.
A gate electrode (word line) 9D consisting of a two-layer film formed by laminating TiSi2°WSi, ), a π-type semiconductor region 11B forming the channel region side portion of the source and drain, and the I-type semiconductor region of the source and drain. A go-type semiconductor region 13B constitutes a portion other than 11B. The capacitive element C includes an n-type semiconductor region 20 serving as one electrode, a dielectric film 22 made of a thin silicon oxide film, and a conductive plate 7E serving as the other electrode made of, for example, a polycrystalline silicon film. It consists of Conductive plate 7
A dielectric film 22 is provided at the end of switch E on the MISFETQ side.
An insulating film 21 made of a thicker silicon oxide film is provided to alleviate the electric field at the end of the conductive plate 7E. An insulating film 23 made of a silicon oxide film is provided on the surface of the conductive plate 7E. 16D is a data line, which is a drain A-type semiconductor region 1 when reading information.
Connected to 3B.

Next, a method for manufacturing the memory cell of the DRAM will be explained with reference to FIGS. 24 to 26.

As shown in FIG. 24, p-
After forming the type well region 3, field insulating film 4, and p-type channel stopper region 5, the EPROM 105 and EEP
In the step of forming the gate insulating film 6 of the memory cells Ql, Q4 and Q5 of the ROM 107 (FIGS. 8a to 8c), D
A silicon oxide film 6 having a thickness of approximately 500 mm is formed in the memory cell area of the RAM. However, this silicon oxide film 6 is not used as a gate insulating film of the switch MISFETQ. At this point, the n-type semiconductor region 20 and the insulating films 21 and 22 shown in FIG. 24 have not been formed.

After this, memory cells Q4 and Q5 of EEPROM 107
In the step of forming the n-type semiconductor region 20 which is the source and drain of the capacitive element C, the n-type semiconductor region 20 which is one electrode of the capacitive element C is formed. Next, the step of forming the insulating film 21 of the memory cell of the EEPROM 107 (FIGS. 9a to 9c)
In the figure), an insulating film 21 is formed in the region where the capacitive element C is provided. At this point, Mi! ! 6. The region where the body membrane 22 is provided is also insulated [21]. M marginal membrane 21) The thickness is
Approximately 1,000 to 2,000 people. Next, EEPROM
In the step of etching the insulating film 21 in the part where the tunnel insulating film 22 of 107 is formed (FIGS. 10a to 10c), the insulating film 21 in the part where the dielectric film 22 of the capacitive element C is to be formed is selectively etched. Remove. Next, EEPROM10
In the step of forming the tunnel insulating film 22 of No. 7, the capacitive element C
Next, the floating gate electrode 7A of the EPROM 105 and the EEPROM 107 is formed.
, 7C and their peripheral circuits MISFETQ2. Q3
．． In the step of forming the gate electrode 7B of Q6 (FIGS. 11a to 12c), as shown in FIG.
A plate electrode 7E is formed. Next, conductive plate 7
The surface of E is thermally oxidized to form a silicon oxide film [2]
form 3. Note that the insulating film 23 may be formed of a silicon oxide film formed by a CVD method, or may be formed by stacking a silicon oxide film formed by thermal oxidation and a silicon oxide film formed by CVD. When forming the insulating film 23, the area where the switch MISFETQ is provided, the CPU 100,
l10102, EPROM105 and EEPROM10
The silicon oxide film 6 in the region where the MISFET constituting the peripheral circuit 7 is provided becomes a thick insulating film 74.

Also, the memory of EPROM105 and EEPROM107
Jf! /LzQ1. A thick insulating film 23 is formed on the surface of the gate electrode 7B of the Q4(7)70-ting gate electrode and its peripheral circuits. Therefore, the conductive plate 7
After forming the insulating film 23 on the surface of E, for example, DRAM1
09 capacitive element C is covered with a resist film, and the area where the switch MISFETQ is provided and the CPU 100 and l1 are covered.
0102, E P ROM2O3 and E P R O
M107 (7) M I SF E that constitutes the peripheral circuit
The thick insulating film 74 in the region where T is provided and the EPROM1
The thick insulating film 23 formed on the surfaces of the floating gate electrodes of the memory cells Ql and Q4 of EEPROM 107 and the gate electrodes 7B of their peripheral circuits is removed by etching. After removing the resist film.

The surfaces of the floating gate electrodes 7A, 7C of the EPROM 105 and EEPROM 107 are thermally oxidized to form second gate insulators 18A, 8C. Next, as shown in FIG. 26, in the step of forming a gate insulating film 8D in the CPtJloo and l10102 regions (FIGS. 14a to 14c), a gate insulating film made of a silicon oxide film is formed in the region where the switch MISFETQ is provided. A film 8D is formed. Note that this gate insulating film 8D is used for the EPROM 105 and the EE
Floating gate electrodes 7A and 7C of PROM107
The second gate insulating films 8A and 8C on the surface of the EPROM 1 may be formed simultaneously with the step of forming them.
In the step of forming the control gate electrodes 9A, 9C of the EEPROM 107 and the control gate electrodes 9D of the CPU 100 and 110102 regions (FIGS. 14a to 17c), the gate electrode VjA9D of the switch MISFETQ is formed. Next, EPROM105 and EEPROM1
07 control gate electrode 9A.

When forming the insulating film 10 on the surface of the switch M
An insulating film 10 is provided on the surface of the gate electrode 9D of ISFETQ.
is formed. Thereafter, a sidewall 12 made of a silicon oxide film is formed. Next, the N-channel MISFET Q2 of the peripheral circuit of the EPROM 105 and the CPU 100
π-type semiconductor region 1 of N-channel MISFET Q7 in the region
In the step of forming 1B (FIGS. 19a to 19c),
The zero-order semiconductor region 11B is formed on the channel side of the source and drain of the switch MESFETQ.
ROM105 and EEPROM107 (7) Memories, It/Ql.

Q4 and their peripheral circuits MISFETQ2, Q5,
N-channel MISF of CPU100 and l10102 area
ETQ7. In the step of forming the n° type semiconductor regions 13A and 13B which are part of the source and drain of Q8 (FIGS. 21a to 21c), the go type semiconductor regions 13B of the source and drain of the switch MISFETQ are formed. After this, passivation film 14, connection hole 15, data, 1i
16D, passivation fi 17, wiring 19, and a final passivation film (not shown) are formed.

As explained above, EPROM105, EEP R
The DRAM 109 can be formed in the process of forming OM2O3.

Next, we will discuss the operational amplifier, analog/digital converter, and digital/digital converter that the microcomputer shown in Figure 1 has.
The structure of the capacitive element and resistive element in the analog converter will be explained. These resistive elements and capacitive elements are used when a microcomputer processes analog quantities.

Figure 27 shows the operational amplifier, analog/digital converter, and digital/digital converter in the microcomputer shown in Figure 1.
FIG. 3 is a cross-sectional view of a capacitive element and a resistive element included in an analog converter.

In FIG. 27, R is a resistive element used when processing analog quantities, and C is a capacitive element used when processing analog quantities.

The resistance element R includes a resistance layer 7G made of a first layer of conductor (polycrystalline silicon film) on the field insulating film 4;
It consists of connection terminals 7H provided at both ends.

Impurities are implanted into the connection terminal 7H at a high concentration so that an ohmic connection can be made with the wiring 16 made of aluminum or the like.

Further, the upper part of the resistance layer 7G has a fixed potential Vcc or Vss.
A wiring 16 to which the voltage is applied is provided. The potential of the n-type well region 2 is fixed at Vcc or Vss. The capacitive element C includes a first electrode 7F made of a first layer of polycrystalline silicon film on the field insulating film 4, and a first electrode 7F.
A dielectric film 8F on the surface of F and a second electrode 9F made of a second layer of conductive film provided overlying the first electrode 7F. The second layer conductive film is, for example, a silicide film (M o S x □) on a polycrystalline silicon film.

TaSi2. TiSi2. It consists of a two-layer film made by laminating WSiz). The first electrode 7F and the second electrode 9F are
Impurities are implanted at a high concentration to lower the resistance.

A wiring 16 is connected to each of the first electrode 7F and the second electrode 9F.

Next, a method for forming the resistive element R and capacitive element C will be explained.

28 to 30 are cross-sectional views of the resistive element and capacitive element shown in FIG. 27 in the manufacturing process.

As shown in FIG. 28, the method for forming the resistive element R and the capacitive element C is to form a first layer polycrystalline silicon film 7 on the field insulating film 4 by, for example, CVD. At this point, no impurity is introduced into the polycrystalline silicon film 7 to lower the resistance. Next, a silicon oxide film 61 is formed by thermally oxidizing the surface of the polycrystalline silicon film 7, for example, as a buffer film when impurities are introduced into the polycrystalline silicon film 7 by ion implantation. Next, the polycrystalline silicon film 7 is filled with phosphorus (P), boron (B), or arsenic (A) by ion implantation.
s), etc., for example, 1012 to 10
The ion implantation is carried out to the extent of "atoms/a!". If this ion implantation is performed by thermal diffusion, the silicon oxide film 61 on the surface of the polycrystalline silicon film 7 is removed.Next, a predetermined region that will become the resistance layer 7G is An impurity implantation mask 62 is formed on the upper part.This impurity implantation mask 62 may be formed of a resist film if the subsequent impurity implantation is performed by ion implantation, or a silicon oxide film formed by CVD if the impurity implantation is performed by thermal diffusion. Then, the polycrystalline silicon film 7
is the memory cell Ql of the EPROM 105 and EEPROM 107.

Floating gate electrode 7A of Q4, 7C5 and MISFET Q2 of their peripheral circuit. Q3. Q5゜Used as the gate electrode 7B of Q6, and the connection terminal 7 of the resistance element R.
Since it is used as the first electrode 7F of the H1 capacitive element C, a second impurity implantation is performed after forming the impurity implantation mask 62 to lower the resistance of the polycrystalline silicon film. Note that when performing the second impurity implantation by thermal diffusion, the portions of the insulating film 61 that are not covered by the impurity implantation mask 62 are removed to expose the polycrystalline silicon film 7, and then thermal diffusion is performed. I do. Next, as shown in FIG. 29, the polycrystalline silicon film 7 is patterned using a resist film 63.
Resistance layer 7G, connection terminal 7H1, first electrode 7F of capacitive element C
form. At this time, EPROM105, EEPRO
Memory cell Ql of M107.

Floating gate electrode 7A, 7C1 of Q4 and MISFET Q2 of their peripheral circuit. Q3. Gate electrodes 7B of Q5°Q6 are also formed. Next, the above-mentioned FIG. 13a,
3b, 13c to 18a, 18b, 1st
8c, the surfaces of the dielectric film 8F, second electrode 9F, resistance element R, and capacitive element C first electrode 7F and second electrode 9F of capacitive element C are covered, as shown in FIG. 30. A thin insulating film 10 is formed.

Note that as a method for making the resistor Q10 have a predetermined resistance value, instead of implanting a predetermined impurity at a low concentration in the first impurity implantation as described above, Alternatively, after the second impurity implantation, an impurity of a conductivity type opposite to that introduced in the second impurity implantation may be implanted, or a predetermined amount of an insulator such as oxygen or nitrogen may be implanted to increase the resistance of the resistance layer 7G. You may try to adjust the. Furthermore, the resistor 17G may be the polycrystalline silicon film 7 without implanting impurities (however, the connection terminal 7H is implanted with impurities to lower the resistance), or the conductive layer 7A other than the resistive layer 7G may be used. , 7B, 7C, 7H, and 7F, high concentration impurities may be introduced.

As explained above, the resistance element R and the capacitance element C are
P R0M105. It can be formed using the process of forming EEP R0M107.

Next, l101 of the microcomputer shown in FIG.
One I10 cell in 02 is shown in FIG.

The I10 cell shown in FIG. 31 is used to drive a fluorescent display tube or the like. For example, a fluorescent display tube is
It is driven in a large voltage range of about 40-OV, and there is a large difference between OV and 5V, which is the normal operating range of a microcomputer. So, for example -40
A voltage of about V is a depletion type P-channel MI
After converting the voltage to the microcomputer's normal operating voltage Vcc level by S FETT, □, P channel MISFET T, , and N channel MISFET T8,
The signal is input to an inverter consisting of the following, and is then subjected to various processing. Note that the N-channel MISF shown in FIG.
ETQ8 corresponds to the N-channel MISFET. On the other hand, the data output from the microcomputer to the fluorescent display tube is
□ and N-channel MISFET T, through an inverter circuit consisting of a depletion type P-channel MIS
FETToz and enhancement type P-channel MI
It is output after voltage conversion by an inverter circuit consisting of SFE T TP3.

Next, the P channel MISF E shown in FIG.
The cross-sectional structure of T.3 is shown in FIG.

As shown in FIG. 32, P-channel MISFET T,
2 is configured in two n-type well regions.

The 2-type well region 2 has a lower impurity concentration than the n-type well region 2, and has a deeper junction depth than the π-type well region 2. The MISFET T3 has a gate insulating film 6 made of a silicon oxide film, a gate electrode 7 made of, for example, a polycrystalline silicon film, a p-type semiconductor region 111 which becomes a part of the source and drain, and a source and drain. p which forms a portion other than the p-type semiconductor region III of
13C. The p-type semiconductor region 111 is provided under the field insulating film 4 without the gate electrode 7e, and is located under the p°-type semiconductor region 13.
It is provided surrounding C. An end of the gate electrode 7H extends above the field insulating film 4.

Under the field insulating film 4 of the two n-type well regions, five n-type channel stopper regions are provided apart from the P-type semiconductor region 111.

Next, a method for manufacturing the P-channel MISFET T, 3 will be explained using FIGS. 33 to 34.

FIGS. 33 to 34 are cross-sectional views in the manufacturing process of P-channel MISFET T, 3 that operates in the range of 0 to +40V.

As shown in FIG. 33, the method for manufacturing the P-channel MISFET T is as follows: First, in order to form two well regions, the surface of the p-type semiconductor substrate 1 is thermally oxidized to form a silicon oxide film 64. do. Next, a silicon nitride film 66 is formed on this as a mask for heat-resistant oxidation, and ions are implanted using this as a mask for ion implantation to form two n-type well regions. Next, the exposed portion of the silicon nitride film 66 on the surface of the semiconductor substrate 1, that is, the n-type well region 2, is thermally oxidized to form a silicon oxide film 65 that is slightly thicker than the silicon oxide film 64. As shown in FIG. 34, the silicon nitride film 66 is removed, a new silicon nitride film is formed, the silicon nitride film in the formation region of the n-type well region 2 is removed, and ions are implanted. After forming the mold well region 2, a silicon oxide film 65 is formed on its surface by thermal oxidation.

Thereafter, the silicon nitride film is removed, and then, as shown in FIG. Then, n-type impurities are implanted into a portion other than the n-type well region 2 to form a p-type well region 3. Next, a silicon nitride film 68 is formed on the silicon oxide films 64 and 65 as a mask for thermal oxidation when forming the field insulating film 4. Next, as a mask for forming the n-type channel stopper region 5, a resist film 6 is placed over the Go-type well region 2I, the 1-type well region 2, and the p-type well region 3.
form 7. Then, on the surface of the type 1 well region 2,
A type impurity is ion-implanted to form an n-type channel stopper region 5. After this, the resist film 68 is removed.

Next, as shown in FIG. 36, a new resist WA69 is formed, and using this resist film 69 and silicon nitride film 68 as masks, ions are implanted into the surface of the A-type well region 2■ to form a P-type semiconductor region. 111 is formed. After that, the resist film 69 is removed. Next, as shown in FIG. 37, using the difference in film thickness between the silicon oxide film 64 and the silicon oxide film 65, n-type impurity ions are implanted into the surface of the P-type well region 3 to form a p-type channel. A stopper region 5 is formed. Thereafter, the field insulating film 4 is formed by thermally oxidizing the portions of the A-type well region 2I, the I-type well region 2, and the p-type well region 3 exposed from the silicon nitride film 68.

After this, E as shown in FIGS. 4a to 4c explained earlier.
Memory cell Q1 of PROM105, MISF of peripheral circuit
ETQ2. Q3, memory MI 5FET Q4 of the memory cell of EPROM 105, switch MISFET in the memory cell or N-channel MISFET Q5 for configuring the peripheral circuit, P-channel MISFE of the peripheral circuit
In the process of forming TQ6, the gate insulating film 6, gate electrode 7e, insulating film 10, and sidewall 1 shown in FIG.
2. P° type semiconductor region 1 forming part of source and drain
Form 3G. Furthermore, a first layer passivation film 14, a connection hole 15, a wiring 16, a second layer passivation film 17, a connection hole 18, a wiring 19, and a final passivation film (not shown) are formed.

Note that the P-channel MISFET shown in FIG. 32 may be constructed using a gate insulating film 70 that is thicker than the gate insulating film 6, as shown in FIG.

Figure 38 shows the P-channel MISFET shown in Figure 32.
P using a gate insulating film 70 thicker than the gate insulating film 6 of
FIG. 3 is a cross-sectional view of a channel MISFET and an N-channel MISFET.

In FIG. 38, a P-channel MISFET is configured in the 1-type well region 2 on the left side. This P channel MI
The gate insulating film 70 of the SFET is made of a silicon oxide film, and has a thickness of about 1000 to 2000 layers.

An N-channel MISFET that operates in the range of 0 to +40V is configured in the p-type well region 3. This N-channel MISFET includes a gate insulating film 70, a gate electrode 7J made of, for example, a polycrystalline silicon film, an n-type semiconductor region 5I forming part of a source and a drain, and a source.

N forming the part other than the n-type semiconductor region 5 of the drain
° type semiconductor region 13B. The gate electrode 7J also extends over the field insulating film 4. Further, the n-type semiconductor region 5 is provided under the field insulating film 4 and surrounding the n-type semiconductor region 13B. In addition, a p-type channel stopper with a higher impurity concentration than the p-type channel stopper region 5 is provided between the n-type semiconductor region 5 and the 1-type well region 2 and between the n-type semiconductor region 5 and the p-type channel stopper region 5. Area 5J is provided.

Next, a method for manufacturing the P-channel MISFET and N-channel MISFET shown in FIG. 38 will be explained using FIG. 39.

Figure 39 shows the P-channel MISFET shown in Figure 38.
FIG. 3 is a cross-sectional view of the manufacturing process of the N-channel MISFET.

The P-channel MISFET and N-channel MISFET shown in FIG. 39 are manufactured by forming the n-type well region 2I (and 2 ) tp-type well region 3. An n-type semiconductor region 5I, a p-type semiconductor region 5J, a P''-type semiconductor region 111, a p-type channel stopper region 5, and a field insulating film 4 are formed.

After this, a silicon nitride film 68 (FIG. 35) which is a mask for thermal oxidation used when forming the field insulating film 4
The silicon oxide films 64 and 65 thereunder are removed to expose the surfaces of the go-type well regions 2I (and 2) and the p--type well regions 3 that are not covered with the field insulating film 4.

Then, the exposed surfaces of the D-type well region 2I (and 2) and the P-type well region 3 are thermally oxidized to form a gate insulating film 7.
form 0.

Thereafter, the gate insulating film 70 in areas other than the regions where the P-channel MISFET and N-channel MISFET shown in FIG. 38 are provided is removed by etching using a resist film. After removing the resist film, the surfaces of the π-type well region 2I (and 2) and the p''-type well region 3 are thermally oxidized again to create a MISFE operating in the range of, for example, O to 5V.
A T gate insulating film 6 is formed. Thereafter, the memory cell Q1 of the EPROM 105 and the MISFET Q2 of the peripheral circuit shown in FIGS. 4a to 4c described above are connected. Q3, EP
Memory MISFET Q4 of the memory cell of ROM105,
N-channel MI 5FETQ5 which is a switch MISFET in the memory cell, P-channel MI in the peripheral circuit
In the process of forming SFETQ6, gate electrodes 7I and 7J
, an insulating film 10, a side wall 12. N-channel MIS
FET source.

n゛-type semiconductor region 13B that is part of the drain, p-type semiconductor region 13G that is part of the source and drain of the P-channel MI S FET, passivation film 14, connection hole 15, wiring 16, passivation film 17, connection Holes 18, wiring 19, and a final passivation film (not shown) are formed.

As mentioned above, the microcomputer of this embodiment has MISFETQ2.
Gate electrode 7B of Q3, MISFET Q5 of the peripheral circuit of EEPROM107. The gate electrode 7B of Q6 is formed using the first layer of polycrystalline silicon film, but as semiconductor integrated circuit devices become smaller, the thickness of the first layer of polycrystalline silicon film becomes thinner. be done. Further, the thickness of the silicon oxide film 10 on the surface of the gate insulating film 6 and the gate electrode 7B is also reduced. Therefore, during ion implantation to form the source and drain, impurity ions may penetrate the silicon oxide film 10, the gate electrode 7, and the gate insulating film 6 and leak into the channel region.
Q3. Q5. The threshold value of Q6 may deviate from a predetermined value. To solve this problem, a thick silicon oxide film is formed on the first layer of polycrystalline silicon film by, for example, CVD, and then the silicon oxide film and the polycrystalline silicon film are patterned to form the gate electrode 7B. If formed, since there is a thick silicon oxide film on the gate electrode 7B, it is possible to prevent impurity ions from leaking into the channel region during the ion implantation. However, as mentioned above, the first layer of polycrystalline silicon film is
Floating gate electrode 7A of memory cell Q1 of 05
and EEPROM107 memory cell memory MISFE
It is used as the floating gate electrode 7C of TQ4, and the second gate insulator @8A, 8C made of a thin silicon oxide film must be formed on it. There is a problem that it is not possible to form a thick silicon oxide film using the above methods.

Therefore, next, in a MISFET in which the gate electrode 7B is made of a first layer polycrystalline silicon film.

source without leaking impurity ions into the channel region.
A method by which a drain can be formed is described.

FIGS. 40 to 45 show the manufacture of a MISFET in which the gate electrode is formed from the first conductive film, such as a polycrystalline silicon film, and the source and drain can be formed without leaking impurity ions into the channel region. FIG. 3 is a diagram for explaining the method.

In FIGS. 40 to 45, the region indicated by Ql is the region where the memory cells of the EPROM 105 are formed, and the region indicated by Q2 is the region where the N-channel MISFET of the peripheral circuit of the EPROM 105 is formed. .

MI5 without leaking impurity ions into the channel region
The method of forming the FET is as shown in FIG.
After forming a second layer of polycrystalline silicon film 7 and implanting a predetermined impurity into it to achieve low resistance, a thick silicon oxide film 71 is formed by, for example, CVD. Next, as shown in FIG. 41, the silicon oxide film 71 in the region where the memory cell Q1 of the EPROM 105 is to be formed is removed by etching using, for example, a resist film as a mask. The resist film is removed after selectively removing the silicon oxide film 71. Next, the polycrystalline silicon film 7 is patterned by etching using a resist film (not shown) as a mask.
As shown in Figure 2, the memory cell Q1 of the EPROM 105
floating gate electrode 7A and MISFETQ2
A gate electrode 7B is formed. The mask made of resist film is removed after patterning<, N-channel MISF
A thick silicon oxide film 71 is placed on the gate electrode 7B of ETQ2. Next, as shown in FIG. 43, the surface of the floating gate electrode 7A is thermally oxidized to form a second gate insulating film 8A. Next, a second layer of conductive film is formed on the semiconductor substrate (chip) 1, and this is patterned to form the control gate electrode (
Word line) 9A is formed.

Next, as shown in FIG. 45, the n-type semiconductor region 11A forming part of the source and drain of memory cell Q1, the n-type semiconductor region 11B forming part of the source and drain of MISFET Q2 of the peripheral circuit, and the memory cell Source of MISFET Q2 of Q1 and peripheral circuit.

n° type semiconductor region 13 forming a portion of the drain other than the above
A, form 13B.

If the source and drain of N-channel MISFET Q2 are formed in this way, the thick silicon oxide film 71 is placed on the gate electrode 7B, which prevents impurities for forming the source and drain from leaking into the channel region. can.

As can be seen from the above description, according to this embodiment, the following effects can be obtained.

(1) In a semiconductor integrated circuit device constituting a microcomputer including a central processing unit and a nonvolatile memory in which program data, dictionary data, etc. of the central processing unit are stored on one semiconductor chip, the nonvolatile The memory is a first non-volatile memory (E P ROM2O3) in which information is written electrically and the written information is erased by irradiation with ultraviolet light; By comprising a second nonvolatile memory (E E P ROM2O3) that is electrically erased, the RO has a large capacity and is rewritable.
M can be obtained, and a ROM that can be electrically rewritten on the system can be obtained.

(2) From (1) above, EPR'0M105 is used to store data that requires a large capacity but is not infrequently rewritten, and is used to store data that requires a small capacity although it is rewritten many times or after the power is turned off. By using the EEPROM 107 to store calculation data that needs to be stored, a degree of freedom is achieved that compensates for the disadvantages of the EPROM 105 that information cannot be rewritten on the system and the disadvantages of the EEPROM 107's small memory capacity. High R
A semi-integrated circuit device consisting of a microcomputer equipped with an OM can be obtained.

That is, program data and dictionary data that require a large storage capacity are stored in the EPROM 105, and even when the content of the data changes over time, such as control data for feedback control, and when the N source is shut off, it can also be stored. Since the control data that needs to be stored can be stored in the EEPROM 107, the functionality of the semiconductor integrated circuit device consisting of a one-chip microcomputer can be improved.

(3) Non-volatile R from EEPROM107 in (1) above
AM can be obtained.

(4) Since the 1-chip microcomputer is equipped with an SRAM as the first RAM, a RAM capable of high-speed data transfer can be obtained.

(5) Since a DRAM is provided as the second RAM of the one-chip microcomputer, a large capacity RAM can be obtained.

(6) From (4) and (5) above, SRA is used to store data that requires small capacity but requires high-speed data transfer.
By using DRAM to store data that does not require high-speed data transfer but requires a large storage capacity, SRAM has the disadvantage that it cannot increase the capacity, and the disadvantage that DRAM has a slow transfer speed. It is possible to obtain a RAM that complements each other.

(7) Form a memory cell Q1 of the EPROM 105 in a first region of the semiconductor substrate 1, form a memory MISFET Q4 in the memory cell of the EEPROM 107 in a second region of the semiconductor substrate 1 different from the first region, and The EEPROM 1 is located in a third region adjacent to the second region of the semiconductor 1.
In the method for manufacturing a semiconductor integrated circuit device constituting a microcomputer, the method includes the step of forming the switch MISFET Q5 in the memory cell No. 07. forming a first gate insulating film 6 on the surfaces of the second and third regions, and forming a source and a drain 20 in predetermined portions under the first gate insulating film 6 in the second and third regions; A floating gate electrode 7A is formed on the first gate insulating film 6 in the first and second regions.
, 7C and the first gate insulating film 6 in the third region.
a step of forming a gate electrode 7B thereon; a step of forming second gate insulating films 8A, 8C on the surfaces of the floating gate electrodes 7A, 7C in the first region and the second region;
A step of forming control gate electrodes 9A and 9C on the second gate insulating films 8A and 8C in the first and second regions, respectively, and forming a source on a predetermined portion under the first gate insulating film 6 in the first region. , drains IIA and 13A, and by performing each of the above steps in the above order, the EEPROM 1
07 sauce.

a step of forming an n-type semiconductor region 20 that will become a drain;
EEPROM 107 can be formed by simply adding the step of forming tunnel insulating film 22 on n-type semiconductor region 20.

(8) The floating gate electrode 7A of the memory cell Q1 of the EPROM 105 and the floating gate electrode 7C of the storage element Q4 in the memory cell of the EEPROM 107 are formed from the first layer of conductive M (polycrystalline silicon film). , the first gate insulating films 6 of the respective elements Ql and Q4 are formed in the same process, and the first gate insulating films 6 of the respective elements Ql and Q4 are formed in the same process.
By forming the second gate insulating films 8A and 8C on the floating gate electrodes 7A and 7C of Q4 in the same process, the EPROM 105 and EE
Each memory cell of PROM 107 can be obtained.

(9) MISF that constitutes the peripheral circuit of EPROM105
ETQ2. MISFETQ5.Q3 and the peripheral circuit of EEPROM107. The gate insulating film 6 of Q6 is connected to the first gate insulating film 6 of the memory cell Q1 of the EPROM 105 and the memory M of the memory cell of the EEPROM 107.
Since it was formed in the same process as the first gate insulating film 6 of ISFETQ4, MISFETQ2. Q3.
Q5. The film thickness of the gate insulating film 6 of Q6 becomes thicker, and the dielectric breakdown voltage can be improved.

(10) Gate insulating film 8 of MISFETQ7 to Q9 for configuring CPU (logic section) 101 and l10102
D is the first gate insulating film 6 of the memory cell Q1 of the EPROM 105 and the EEPROM 107 (7).
Since it is formed in a separate process from the first gate insulating film 6 of the memory MISFET Q4 in the J cell, the film thicknesses of the gate insulating film 8D and the gate insulating film 6 can be set to optimum values independently.

(11) CPU (Logic part) 100 and l10102
Since the gate electrodes 9D of MISFETs Q7 to Q9 for configuring are formed of a second conductive layer, that is, a two-layer film in which a silicide film is laminated on a polycrystalline silicon film, for example, the gate electrodes 9D have low resistance. can be achieved.

(12) From the above (8) to (11), EEPROM2O3 and EEPROMI07 including one peripheral circuit.
The voltage applied to the MISFE, T and the MI 5F for configuring the CPU (logic section) 100 and l10102.
Since the voltage applied to the ET can be set independently, the structure of each element can be set independently.

(13) The DRAM 109 can be formed in the manufacturing process of the EEPROM 107 or in substantially the same process.

(14) From the above (12), the dielectric film 22 of the capacitive element C of the memory cell of the DRAM 109 is
Since it is formed very thinly like the I-channel insulating film 22 of the M2O3 memory cell, the capacitance value of the capacitive element C can be increased.

(15) A DRAM with a large capacity can be obtained from the above (14), and a RAM with a large capacity can also be obtained from this.

(16) EPRO the resistance element R that constitutes the analog circuit.
It can be formed in the same process or almost the same process as the floating gate electrodes 7A and 7C of the memory MISFET Q4 in the memory cell M105 or the memory cell EEPROM107, and the capacitive element C can be formed in the memory cell M105 or the memory cell EEPROM107.
5 or EPROM 105 in the same process.

(17) Since the resistive element R and the capacitive element C are covered with the transparent film 10, stable resistance and capacitance values can be obtained during operation of the circuit.

(18) Since the well region under the resistive element R and the capacitive element C is electrically fixed, stable resistance and capacitance values can be obtained during circuit operation.

(19) Conductive layer 1 with the upper part of resistance element R set at a fixed potential
9, other signal wiring can be extended over the conductive layer 19.

(20) From (16) to (19) above, it is possible to easily obtain stable resistive elements R and capacitive elements C necessary for processing analog quantities in a one-chip microcomputer.

(21) EPROM105, EEPROM107, DR
High-pressure MI is produced in almost the same process as AM109.
SFET can be formed.

(22) By extending the gate electrode 7e of the high-voltage MISFET to the top of the field insulating film 4 so that the end portion rests on the field insulating film 4, the gate electrode 7
The breakdown voltage between I and the semiconductor substrate 1 can be improved.

(23) By surrounding the semiconductor region with high impurity concentration, which is part of the source and drain of the high voltage MISFET, with the semiconductor region with low impurity concentration, the breakdown voltage of the source and drain can be improved.

(24) From the above (21) to (23), it is possible to easily obtain a high voltage MISFET for use in the 110102 of a one-chip microcomputer.

The present invention has been specifically explained above using examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

For example, the microcomputer shown in FIG.
Although M is provided with an SRAM 108 and a DRAM 109, it is also possible to use only one of the SRAM 108 and the DRAM 109.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects of typical ones are briefly explained below.

EPROM is used to store data that is rewritten many times but requires a large capacity, and is used to store data that is rewritten many times but has a small data capacity, or for calculation data that needs to be stored even after the power is turned off. In my memory, E E P
By using ROM, EPROM has the disadvantage that information cannot be rewritten on the system, and EEPR
It is possible to obtain a one-chip microcomputer equipped with a ROM with a high degree of freedom, which mutually compensates for the shortcoming of the OM's small memory capacity.

In other words, program data and dictionary data that require a large storage capacity can be stored in EPROM, and the content of the data changes over time, such as control data for feedback control, and can be stored even when the power is cut off. Since necessary control data is stored in the EEPROM, it is possible to improve the functionality of a semiconductor integrated circuit device consisting of a one-chip microcomputer.

In addition, in the step of forming the EPROM, there are a step of forming an n-type semiconductor region 20 which becomes the source and drain of the EEPROM, a step of forming a thick insulating film 21 on the n-type semiconductor region 20, and a step of forming the n-type semiconductor region 20. An EEPROM can be formed by simply adding the step of forming a tunnel insulating film 22 on top of the tunnel insulating film 20.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microcomputer of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a memory of an SRAM 108 included in the microcomputer of an embodiment of the present invention shown in FIG. Figure 3 is an equivalent circuit diagram showing the schematic configuration of the circuit of the EPROM 105 installed in the microcomputer of this embodiment, and Figure 4 is the equivalent circuit diagram of the circuit of the EPROM 105 installed in the microcomputer of this embodiment. 2 is an equivalent circuit diagram showing a schematic configuration of a circuit of an EPROM 105. FIG. Figures 5a, 5b, 5C, 6a, 6b,
Fig. 6c, . . . Fig. 21a, Fig. 21b. Figures 21c, 22a, 22b, and 22c are
Microcomputer (7) EPR of one embodiment of the present invention
M that constitutes the logic part of OM, EEPROM, CPU, etc.
23 to 26 are cross-sectional views in the manufacturing process of the ISFET. FIGS. 23 to 26 are cross-sectional views in the manufacturing process of the DRAM memory cell provided in the microcomputer of this embodiment shown in FIG. The operational amplifier included in the microcomputer shown in FIG.
28 to 30 are cross-sectional views of the capacitive element and the resistive element in the analog/digital converter and the digital/analog converter. Fig. 31 is an equivalent circuit diagram showing the - cell in Ilo of the microcomputer shown in Fig. 1, and Fig. 32 is an equivalent circuit diagram of the P-channel MISFET shown in Fig. 31.
33 to 37 are cross-sectional views of the P-channel MISFET shown in FIG. 32, and FIG. 38 is a cross-sectional view of the P-channel MISFET shown in FIG. 32.
P using a gate insulating film 70 thicker than the gate insulating film 6 of
FIG. 3 is a cross-sectional view of a channel MISFET and an N-channel MISFET. Figure 39 shows the P-channel MISFET shown in Figure 38.
40 to 45, cross-sectional views of the manufacturing process of N-channel MISFET, show that the gate electrode is formed with the first layer of polycrystalline silicon film, and the source and drain are further formed without leaking impurity ions into the channel region. FIG. 3 is a diagram for explaining a method for manufacturing a MISFET that can be formed. In the figure, 1... semiconductor chip (microcomputer)
, 100...CPU, 101...○5C110
2...■／○, 103・S I, 104...T
IM E R1105・E P ROM, 106...
・Voltage control circuit, 107...EEPROM, 108・
...S RAM, 109...DRAM, 110...
l10BUS, Ql...EPROM memory cell, Q
2. Q3...MISFET of peripheral circuit, Q4...E
Storage element in an EPROM memory cell, Q5. Q6・
・・MISFET of EEPROM peripheral circuit, Q7. Q
9...CPU MISFET, Q8...MISFE
T, 6...first gate insulating film, 7A, 7B, 7C...
・Gate electrodes made of first layer conductive film, 8A, 8C・
...Second gate insulating film on floating gate electrode, 8D...First gate insulating film in CPU and I10 area, 9A, 9C, 9D... Gate electrode made of second layer conductive film, 10 ...thin silicon oxide film, IIA, I
IB, 11C...Low concentration layer of source and drain, 12
...Side wall, 13A, 13B, 13C...
High concentration layer of source and drain, 20...EEPROM
n-type source and drain, 21...thick gate insulating film, 22... tunnel insulating film.

Claims (1)

[Claims] 1. A semiconductor integrated circuit device constituting a microcomputer that includes a central processing unit and a nonvolatile memory in which program data, dictionary data, etc. of the central processing unit are stored on one semiconductor chip. In the above, the nonvolatile memory electrically writes information and erases the written information by irradiation with ultraviolet light, and the first nonvolatile memory electrically writes information and erases the written information. A semiconductor integrated circuit device comprising a second nonvolatile memory that is electrically erased. 2. A memory cell of an EPROM is formed in a first region of the semiconductor substrate, and a memory MISFET in the memory cell of the EEPROM is formed in a second region of the semiconductor substrate different from the first region.
and forming a switch MISFET in a memory cell of the EEPROM in a third region adjacent to the second region of the semiconductor substrate. forming a first gate insulating film on the surfaces of the first, second and third regions of the semiconductor substrate, and forming a first gate insulating film on a predetermined portion under the first gate insulating film in the second and third regions; forming a source and a drain, forming a floating gate electrode on a first gate insulating film in the first and second regions, and forming a gate electrode on the first gate insulating film in the third region; forming a second gate insulating film on the surfaces of the floating gate electrodes in the first and second regions; and forming a control gate electrode on the second gate insulating films in the first and second regions, respectively. and a step of forming a source and a drain in a predetermined portion under a first gate insulating film in the first region, and each of the steps is performed in the above order. manufacturing method. 3. The step of forming a source and drain in predetermined portions of the second and third regions is performed before the step of forming a first gate insulating film on the surfaces of the first, second and third regions, respectively. A method for manufacturing a semiconductor integrated circuit device according to claim 2, characterized in that: