JPH01295516A - Malfunction preventing circuit - Google Patents

Abstract

PURPOSE:To eliminate noise without causing the reduction in fan-out, reduction in the mount density and any cost-up by providing a delay circuit outputting plural delay signals and a logic circuit taking majority decision logic of plural delay signals and giving an output. CONSTITUTION:A delay circuit 10 gives delays of '0', t and t2 to a digital input signal to generate three delay signals. A logic circuit 12 takes majority decision logic of the three signals. For example, suppose that noise is superimposed on, e.g., a digital signal and the signal level is changed momentarily to a high level, then the high level is given to the logic circuit 12 as it is and delayed by t and t2 the result is given to the logic circuit 12. As a result, when one of inputs to the logic circuit 12 is at a high level, the other two inputs are at a low level without fail. Thus, the majority decision logic results in a low level. The noise is eliminated from the input signal as the output of the logic circuit 12.

Description

[Detailed Description of the Invention] [Summary] Regarding a malfunction prevention circuit that prevents malfunction by removing noise generated in a digital circuit, by adding a simple circuit to the digital circuit,
The aim is to eliminate noise without reducing fan-out, reducing packaging density, or increasing costs.Delay circuits that output multiple delayed signals with different times from digital input signals The device is configured to include a logic circuit that takes majority logic and outputs it.

FIELD OF THE INVENTION The present invention relates to a malfunction prevention circuit that prevents malfunctions by removing noise generated in digital circuits.

In digital circuits, it is desirable that digital input signals be stably supplied to internal logic circuits.

Traditionally, manufacturers have designed, manufactured, inspected, and shipped I
When C is delivered to a user and an implementation test is performed, it may not work as expected. This is caused by the difference between the manufacturer's shipping test and the user's environment. Although there are various causes of malfunctions and cannot be generalized, it can be said that noise on the signal line to the internal logic circuit is one of the causes. If the logic of the digital input signal becomes incorrect due to noise on the signal line (“0” becomes “1” or “1” becomes “0”), the logic of the internal logic circuit becomes completely incorrect. It malfunctions.

Therefore, it is necessary to prevent malfunctions caused by such noise.

[Conventional technology]

Conventionally, measures to prevent this type of noise have been to make the output drive transistor inside the IC insensitive or to add a bypass capacitor outside the IC between the power supply (Vcc and GND) to minimize the generation of noise. ing. Both of these methods are radical! *Variations in VAN voltage due to changes are suppressed to prevent noise from being transmitted to the elements within the IC.

[Problem to be solved by the invention]

However, if the output drive transistor within the IC is made insensitive, fan-out decreases, and if a capacitor is added outside the IC, the packaging density decreases and costs increase.

Therefore, the present invention solves these problems and adds a simple circuit to the digital circuit to remove the M sound without reducing fan-out, reducing packaging density, or increasing cost. The purpose is to

[Means to solve the problem]

1- is a delay circuit 1 which is a block diagram of the principle of the present invention.
0 inputs a digital input signal and outputs a plurality of delayed signals with different delay times.

The logic circuit 12 takes the majority logic of the plurality of delayed signals output from the delay circuit 10 and outputs the result as an output signal.

[Effect]

The delay circuit 10 generates three delayed signals by applying delay amounts 0, Δ, and Δ2t to the digital human input signal. The logic circuit 12 takes majority logic of these three signals. for example,
Suppose that noise is superimposed on a digital input signal and the signal level momentarily changes to a high level. This high level is given as is to the logic circuit 12, and Δ and Δ
The signal is delayed by 2t and applied to the logic circuit 12. As a result, when one of the inputs of logic circuit 12 is at a high level, the other two inputs are always at a low level. Therefore, the result of this majority logic is a low level. Therefore, theory I
I! The output of circuit 12 is the input signal with noise removed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

2(A) and 2(B) are circuit diagrams of one embodiment of the present invention, in which FIG. 2(A) shows the delay circuit 10 of FIG. 1, and FIG.
) indicates the logic circuit 12 of FIG.

The delay circuit 10 is constructed by connecting delay circuits 10a and 10b in series. Each of the delay circuits 10a and 10b is composed of, for example, a two-stage CMOS inverter. Each delay circuit 10a and 10b provides a delay time of Δt.

The input signal (2) and output signal (@) of the delay circuit 10a and the output signal (C) of the delay circuit 10b are input (1) to the logic circuit 12 shown in FIG. 2(B), respectively.

The logic circuit 12 includes three two-man power AND circuits 12a.

12b and 12G, and an OR circuit 12d which inputs the output signals of these AND circuits. The AND circuit 12a performs AND logic of the signals O and @,
The AND circuit 12b takes an AND logic between the signals O and ■, and the AND circuit 12G takes an AND logic between ω and ■. In this way, the AND circuits 12a to 12c generate the three signals ■, ■, ■
The AND logic of all combinations of two of them is taken.

Next, the operation of this embodiment will be explained with reference to the operation timing diagrams shown in FIGS. 3A and 3B.

First, when a high-level pulse is generated due to noise when the input signal is at a low level (Figure 3 (A))
I will explain about it. As shown in FIG. 3(A), it is assumed that the input signal ■ enters a low level, and at this time, it becomes a high level (sufficiently shorter than the duration of a normal logic level) due to the N sound. The signal @ generates a high level pulse with a delay of Δt with respect to the input signal O, and the signal ■ generates a high level pulse with a delay of Δt with respect to the signal O. Therefore, two-man powered AND circuits 12a to 12c
All outputs are at low level and never go to high level. As a result, the output signal of the OR circuit 12d is
is also held at O-level, and high-level noise superimposed on the input signal is not propagated.

Next, in the opposite case, that is, when a low-level pulse is generated due to noise during a high-level input signal, Figure 3 (
As shown in B), the signal @ becomes low level with a delay of Δt from the input signal, and the signal O becomes low level with a delay of Δt from the signal @. In this case, the AND circuit 12a,
As shown in FIG. 3(B), a low level pulse is generated twice at each output of the signals 12b and 12c, that is, the AND output of the signals ■ and @, the signal @, and the AND output of the signals ■ and ■. However, all the AND outputs do not become low level at the same time. Therefore, the low level pulse of the input signal (2) is not propagated to the output signal O of the OR circuit.

The present invention can be applied to, for example, a cover sofa for a digital IC. FIG. 4 is a 70 block diagram when the present invention is applied to a digital IC. The digital IC includes an input buffer 14a, an internal logic circuit 14b, and an output buffer 14c. Input buffer 14a receives a digital input signal via input bin 14d and outputs a digital input signal via output bin 14e.
Outputs a digital output signal via. The malfunction prevention circuit of the present invention is provided within the input buffer 14a.

FIG. 5 is a detailed circuit diagram of the input buffer 14a. In the illustrated circuit, the input bin 14d is a chip select bin (hereinafter referred to as the C8 input terminal), and the input buffer 14
This is the case where a is a depth select buffer. Fifth
In the figure, the same reference numerals are given to the same components as those shown in FIGS. 2(A) and 2(B). The C8 input terminal is applied to the delay circuit 10a via a two-stage CMOS inverter. Delay circuits 10a and 10b each have 2
It consists of CMOS inverters in stages.

The two-man powered AND circuits 12a, 12b and 12G are each composed of six MOS transistors. The three-man powered off circuit 12d is composed of eight MOS transistors. The output signal (2) of the OR circuit 12d is applied to the input of the internal logic circuit 14b in FIG.

By using the present invention in the preceding stage of the input buffer 14a, the internal logic circuit 14a of the digital IC 14 can operate normally without being affected by noise. In addition, it can be applied to various parts such as the input bin, σE, WE address, and data-in of the memory IC.

FIG. 6 is a circuit diagram of a logic circuit 12 according to another embodiment of the present invention. This is similar to the delay circuit 10 shown in FIG. 2(A). The logic circuit 12 of this embodiment is an OR circuit 16a, 1 operated by two people.
6b and 16G, and a three-man powered AND circuit 16d. The OR circuit 16a performs an OR operation between the signals ω and @, the OR circuit 16b performs an OR operation between the signals @ and 2, and the OR circuit 16G performs an OR operation between the signals 2 and 0. Each output of OR circuits 16a, 16b and 16C is given to AND circuit 16d.

7 is an operation timing diagram of the embodiment shown in FIG. 6. FIG. 7 (A) is an operation timing diagram when the digital input signal ■ momentarily changes from high level to low level due to noise, and FIG. 7 (B) is an operation timing diagram of the embodiment shown in FIG. is an operation timing diagram when the digital input signal ω momentarily changes from low level to high level due to noise. It can be seen that noise is removed in both cases.

【Effect of the invention〕

As explained above, according to the present invention, when a low level becomes a high level due to a noise, or conversely, when a high level becomes a low level due to noise, in either case, these unnecessary reverse effects are avoided. Since the signal component is completely removed and is not propagated to subsequent stages, by adding a simple circuit to the digital circuit, it is possible to eliminate M sound without reducing fan-out, packaging density, or increasing cost. Can be removed.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a circuit diagram of an embodiment of the present invention, Fig. 3 is an operation timing diagram of the embodiment of Fig. 2, and Fig. 4 is an application example of the present invention. 5 is a detailed circuit diagram of the input buffer 714a shown in FIG. 4, FIG. 6 is a circuit diagram of another embodiment of the present invention, and FIG. 7 is an operational timing diagram of the embodiment of FIG. 6. It is a diagram. In the figure, 10 is a delay circuit, 10a, 10b are delay circuits, 12 is a logic circuit, 12a, 12b, 12c are AND circuits, 12d is an OR circuit, 14 is a digital IC1, 14a is an input buffer, 14b is an internal logic circuit, 14c is an output buffer, 14d is an input bin, 14e is an output bin, 16a, 16b, 16c are OR circuits, and 16d is an 'AND circuit. Agent Patent attorney Tadahiko Ito 1''. ・J'Nereshi's sword R craft fi'0,7 Figure g1 Figure (A) (B) 1. At times ■ 4 pieces 2 figures (A) Book IN Chaos Ya 1 hard work shell 22゛ country 3 figures? 'January 4 diversion tase showing boots 2 figures Fig. 4 (B)

Claims (1)

[Claims] It is characterized by comprising a delay circuit (10) that outputs a plurality of delayed signals having different delay times from a digital input signal, and a logic circuit (12) that takes majority logic of the plurality of delayed signals and outputs the result. Malfunction prevention circuit.