JPH01273346A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a latch up phenomenon from occurring in a parasitic bipolar between a pMOS and an nMOS, by equipping an electrode on the rear of a high-concentration substrate and a high-concentration layer reaching the substrate from the surface of an epitaxial growing layer on the borders of said pMOS and said nMOS in the epitaxial growth layer. CONSTITUTION:A high-concentration substrate 1 and a high-concentration layer 15 reaching said substrate 1 increase the amplification factor of the parasitic bipolar formed between the pMOS transistor 9 and the nMOS transistor 14 of a low-concentration epitaxial growing layer 3 to decrease the amplification factor of the parasitic bipolar and the frequency of operations. The high- concentration layer 15 reaching the high-concentration substrate 1 is formed in the epitaxial growing layer 3 on the borders of the pMOS and the nMOS. This makes the high-concentration substrate 1 and the high-concentration layer 15 of extremely low substrate resistance constitute the base of a parasitic pnp transistor to produce no potential difference between the base and the source even if a large current is passed through the pMOS transistor, therefore, the parasitic bipolar is not be operated.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a CMO3 semiconductor device.

[Prior Art] A CMO3 semiconductor device, for example, as shown in FIG.
A P well 101 is provided on an N-type substrate 100, and a source (P''') 102 and a drain (P'') are provided on the N-type substrate 100.
) 103 and a gate 105 formed through a gate oxide film 104.

It is composed of an S transistor 106, an nMOS transistor 111 consisting of a source (N") 107 and a drain (N'") 108 formed in a P well 101, and a gate 110 formed through a gate oxide film 109. Things are common. In this CMO8 semiconductor device, for example, the source 102 . Parasitic p-n- formed in N-type substrate 100° P well lot
p bipolar transistor δ1 and source 102 of nMOS transistor 111. Inside P-well 101.

The parasitic npn bipolar transistors δ formed on the N-type substrate 100 are respectively configured, and the two parasitic bipolar transistors δ1 . It is believed that δ2 constitutes a thyristor 112 as shown by a broken line.

[Invention tries to solve &ll! Title] CMO3 above
In a semiconductor device, for example, the parasitic bipolar transistor δ is triggered by a noise current that enters from the power supply.
1. The thyristor 112 composed of δ2 operates and the electric current f
A latch-up phenomenon in which the i (yoD) terminal and the ground (V ss) terminal become conductive easily occurs (, thyristor 112
Once activated, current will continue to flow unless the power supply voltage ■IID is completely reduced to zero.

Therefore, attempts have been made to prevent this launch-up phenomenon by various means as shown below, but none of them have been sufficient preventive measures.

First, as shown in FIG. 2, the parasitic bipolar transistor δ7. The purpose is to increase the execution base length, ,b, corresponding to the base area of δ2. This causes the parasitic bipolar transistor δ1
．． Since the amplification factor (ho), which is the performance of δ□, decreases, the thyristor 112 becomes difficult to function, but there is a problem that the semiconductor chip inevitably becomes larger.

As a second means, the parasitic bipolar transistor δ1
The aim is to increase the base concentration of As shown in FIG. 3, this uses a highly concentrated N-type substrate 113, and
3, low concentration epitaxial growth layer (N”) 114
and pMOsM is formed on the epitaxial growth layer 114.
OS transistor 106O3) transistor 111 is formed. As a result, the base concentration of the parasitic bipolar transistor δ1 increases, so the amplification factor hFE of the parasitic bipolar transistor δ decreases, making it difficult for the parasitic bipolar transistor δ1 to operate, but this is still a sufficient measure to prevent the latch amplifier phenomenon. It's not.

[Means for Solving the Problems] In order to solve the above problems, the semiconductor device of the present invention has the following features:
A semiconductor device in which a low concentration epitaxial growth layer is formed on a high concentration substrate, and a CMOS transistor is formed in the epitaxial growth layer, in which an electrode is provided on the back surface of the high concentration substrate, and a high concentration The present invention is characterized in that a high concentration layer reaching the substrate is provided at a position separating the 9MOS transistor and the nMOS transistor in the epitaxial growth layer.

[Function] In the semiconductor device having the above configuration, the high concentration substrate and the high concentration layer reaching the high concentration substrate are used to form the 1) MOS transistor and n of the low concentration epitaxial growth layer formed on the substrate.
Since the base concentration of the parasitic bipolar transistor formed between the MOS transistors can be increased, the amplification factor of the parasitic bipolar transistor decreases and it becomes difficult to operate, and the high concentration layer reaching the high concentration substrate is replaced with a pMOS.
By forming the epitaxial growth layer that separates the transistor and the nMO3 transistor, the highly doped substrate with extremely low substrate resistance and the highly doped layer serve as the base of the parasitic pnp) transistor, allowing a large current to flow into the 9MOS transistor. Even if the current flows, it is possible to prevent a potential difference between the base and the source of the 9MOS transistor from occurring.
The parasitic bipolar transistors described above almost no longer operate, and a CMO3 semiconductor device in which measures are taken to prevent the launch amplifier phenomenon can be realized. Furthermore, the high concentration substrate is ■3. Therefore, the t-edge provided on the back side of the high concentration substrate is
By using the D electrode, the CMO3 semiconductor device can be significantly downsized. .

〔Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, and in FIG. An electrode 2 made of aluminum or the like is formed on the back surface. Further, a low concentration epitaxial growth layer (N-) 3 having an internal resistance of about several Ω1 is formed above, and a P well 4 is formed in the epitaxial growth N3. Furthermore, this epitaxial growth layer 3 has a source (Po
) 5, a drain (P") 6, and a gate 8 formed through a gate oxide film 7. In addition, in the P well 4, a source (N"") is formed. 10, a drain (N'') 11, and a gate 13 formed through a gate oxide film 12.
A transistor 14 is formed and the drain 6.
A CMO3 semiconductor device is constructed in which 11 serves as an output. Further, at a position of the epitaxial growth layer 3 that separates the pMO3) transistor 9 and the nMOS transistor 14, a highly doped layer (N''
) 15 are formed.

In the CMO3 semiconductor device described above, a parasitic bipolar transistor (see FIG. 2) is formed by the pMO3I-transistor 9 and the nMOS transistor 14. Since it is formed at a position separating the transistor 9 and the nMOS transistor 14, the base concentration of the parasitic npn transistor becomes sufficiently high due to the highly doped substrate 1 and the heavily doped layer 15, so that the parasitic bipolar transistor formed The amplification factor hFE is significantly lowered,
The parasitic bipolar transistor hardly operates. Also, the substrate resistance of the high concentration substrate 1 and the high concentration layer 1
Since the resistance of the transistor (N”) is extremely low, even if current begins to flow through the parasitic bipolar transistor, the current will flow through the highly doped substrate 1 and the heavily doped layer 1.5, which have low resistance, and this parasitic The bipolar transistor stops operating. Also, the high concentration substrate l and the high concentration layer 15 are connected to the base (V
, ), so the base (Voe) and pM.

It becomes possible to significantly lower the bias voltage between the source 5 of the S transistor 9, and therefore, a CMOS semiconductor device can be realized in which measures are taken against the latch-up phenomenon that can prevent the operation of the parasitic bipolar transistor that is formed.

Furthermore, in a conventional CMO3 semiconductor device, a circuit is formed by a combination of pMOS transistors and nMOS transistors, so the wiring for the power supply V□ of each pMO3) transistor and the wiring for the ground VSS of each nMOS transistor are different from each other. Electrodes are formed over a wide area of the chip surface so that they are connected by the same wiring. However, the commercial of the present invention
In the O3 semiconductor device, the high concentration layer 15 and the high concentration substrate 1 are connected and the resistance is low, so that the voltage BvllD of the pMOS transistor 9 can be taken from the electrode 2 formed on the back surface of the substrate 1. Therefore, since this electrode 2 can be used as the electrode for the power supply Vllll of each pMO transistor, there is no need to form an electrode for the power supply VIID on the chip surface, and compared to the conventional CMO3 semiconductor device shown in FIG. It will be possible to significantly reduce the size of the chip by cutting the chip area in half. Furthermore, C
Since the MO3 semiconductor device has a large number of pins (for example, 24 pins), by using the power supply Vllll+ of the PMOS transistor as the back electrode 2, the number of pads can be reduced by one, and the number of wire bonding operations can be reduced.

In addition, the source 5 of the pMO3l-transistor and the high concentration layer 15
It is only necessary to form an electrode made of aluminum or the like on the short-circuit part 16 of the chip, and the size of the chip itself is not affected.Also, although the high concentration substrate 1 is a N゛ substrate, a P゛ substrate is used. Of course, it is also possible to use a CMO3 semiconductor device.

[Effects of the Invention] The CMO3 semiconductor device of the present invention is a CMO3 semiconductor device in which measures are taken to prevent the launch amplifier phenomenon caused by the parasitic bipolar transistor formed between the pMOS transistor and the nMO5 transistor. Furthermore, CMO3 with the electrode provided on the back surface of the high concentration substrate as the base electrode
Since it is a semiconductor device, it has an extremely effective effect of being able to significantly reduce the size of the chip.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIGS. 2 and 3 are sectional views of conventional semiconductor devices. DESCRIPTION OF SYMBOLS 1... High concentration substrate, 2... Electrode, 3... Epitaxial growth layer, 9... 9MO5) transistor, 14... nMO5) transistor, 15... High concentration layer. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] (1) A semiconductor device in which a low concentration epitaxial growth layer is formed on a high concentration substrate, and a CMOS transistor is formed in the epitaxial growth layer, in which an electrode is provided on the back surface of the high concentration substrate, and the surface of the epitaxial growth layer is A semiconductor device comprising: a highly doped layer extending from the top to the highly doped substrate at a position separating a pMOS transistor and an nMOS transistor in the epitaxial growth layer.