JPH01270414A - Phase synchronous oscillating circuit - Google Patents

Abstract

PURPOSE:To reduce the occurrence of disorder accompanied with the switching operation by switching a time constant of phase synchronization to form a gentle slope at the time of switching from the quick lead-in state to the normal synchronous state. CONSTITUTION:When switching from the quick lead-in state to the normal state is indicated, the output voltage of a voltage comparator IC 2 of a time constant switching controller 4 falls and the voltage of a time constant switching signal S6 falls while describing a gentle slope. Consequently, the circuit between the drain terminal and the source terminal a field effect transistor Q1 of a filter 2 is turned off, and the resistance value between them is raised. Then, the time constant of the filter 2 is changed to the value by which the eliminating integral capability of high frequency components is increased, and the normal synchronous characteristic is realized as the whole of a phase synchronizing circuit.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a phase synchronized oscillation circuit, and particularly to a read clock synchronized with a read data pulse signal read from a storage medium in a magnetic disk storage device. The present invention relates to a phase-locked oscillation circuit suitable for time constant switching phase-locked oscillation that generates a signal.

[Conventional technology]

Conventionally, this type of phase synchronized oscillator circuit synchronizes the phase of a read clock signal output from the circuit with a read data pulse signal read from a storage medium of a magnetic disk storage device. In this operation, the time constant of the phase synchronization circuit is switched in steps in order to perform faster operation when pulling in to the read data pulse signal compared to normal synchronization to the read data pulse signal. .

That is, switching between the time constant during normal synchronization and the time constant during high-speed operation is instantaneously performed.

[Problem to be solved by the invention]

As described above, in the conventional phase-locked oscillation circuit, the time constant of the phase-locked circuit is switched in steps, so in the operation of switching the time constant of the phase-locked circuit from the high-speed pull-in state to the normal synchronization state There is an inconvenience that disturbance occurs due to switching.

The present invention has been made in view of the above, and its purpose is to provide a means for reducing disturbances that occur when switching the time constant of a phase-locked circuit from a high-speed pull-in state to a normal synchronization state. .

[Means to solve the problem]

The present invention provides a phase comparator that detects a phase difference between a read data pulse signal read from a storage medium of a magnetic storage device and a read clock signal, and generates a phase difference signal corresponding to the phase difference; filter means for removing and integrating a high frequency component of the phase difference signal with a time constant switched based on a time constant switching signal and outputting an oscillation frequency control signal;
and oscillation means for controlling the frequency based on the oscillation frequency control signal and oscillating and outputting the read clock signal. Based on a high-speed pull-in switching signal that instructs the speed and speed of pull-in of the read clock signal with respect to the read data pulse signal, a time constant having a gentler slope when switching from the high-speed pull-in state to the normal state than in the reverse case is set. A configuration is adopted in which a time constant switching control means capable of outputting a switching signal is provided. This aims to achieve the above-mentioned purpose.

[For production]

In the present invention, when switching from the high-speed retraction state to the normal state, the time constant switching signal is input to the filter means so as to draw a gentle slope compared to when switching from the normal state to the high-speed retraction state. .

Therefore, the time constant for the removal integration of the high frequency component of the phase difference signal in the filter means changes so as to draw a gentle slope, and does not change stepwise.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, in FIG. 1, read data pulse non-signal S1 read from a storage medium (not shown) of a magnetic storage device.
The phase difference signal S2, which is the output signal of the phase comparator l, is input to the phase comparator 1, and the output signal of the filter 2 is input to the filter 2. The oscillation frequency control signal S3, which is 0-order, is input to the voltage-controlled oscillator 3.The read clock signal S4, which is the output signal of the voltage-controlled oscillator 3, is input to the phase comparator 1 on the one hand. On the other hand, it is connected as an output of the oscillation circuit.

Next, the high-speed pull-in switching signal S5 output from an external device (not shown) is input to the time constant switching controller 4. A time constant switching signal S6, which is an output signal of the time constant switching controller 4, is connected to be input to the filter 2 described above.

Among the above parts, phase comparator 1. and the voltage controlled oscillator 3 have the same configuration as that normally used.

Next, the filter 2 has a configuration as shown in FIG. 2, for example. In the figure, a phase difference signal S2, which is an output signal of a phase comparator 1, is input to a negative input terminal of an operational amplifier ICI via a resistor R1. The negative input terminal of this operational amplifier ICI is further connected to a resistor R2.
is connected to the output terminal of the operational amplifier ICI via a series connection circuit including a resistor R3 and a capacitor C1. The positive input terminal of operational amplifier ICI is grounded.

Next, the time constant switching signal S6, which is the output signal of the time constant switching controller 4, is input to the gate terminal of the field effect transistor Ql, and the drain terminal of the field effect transistor Q1 is connected to the resistor. The phase difference signal S2 is inputted via R4, and the source terminal of the field effect transistor Q1 is connected to the connection point between the resistor R2 and the resistor R3. The output of the operational amplifier ICI becomes the oscillation frequency control signal S3, which is the output signal of the filter 2.

To explain the function of the filter 2 as described above, the time constant as a filter is determined by the resistors R1°R2, R3, R
4, the capacitance value of the capacitor C1, and the resistance value between the drain terminal and the source terminal of the field effect transistor Ql. Therefore, if the resistance value between the drain terminal and the source terminal of the field effect transistor Q1 changes, the time constant also changes.

In this embodiment, the field effect transistor Q1 operates as a variable resistor, and the resistance value between its drain terminal and source terminal is the same as that at its gate terminal, that is, the time constant switching signal S
When the voltage of 6 increases, the resistance value changes to a low value, and in the opposite case, the resistance value changes to a high value.

The filter 2 as described above has the function of removing and integrating the high frequency component of the phase difference signal S2 based on the time constant determined by the time constant switching signal S6, and outputting the oscillation frequency control signal S3.

Next, the time constant switching controller 4 has a configuration as shown in FIG. 3, for example.

In the figure, first, the high-speed pull-in switching signal S5 in FIG.
8. Positive electrode high-speed retraction switching signal S7
is input to the positive input terminal of the voltage comparator IC2 via the resistor R5, and the negative electrode high-speed pull-in switching signal S8 is input to the negative input terminal of the voltage comparator IC2 via the resistor R6. A resistor R is connected to the output side of the voltage comparator IC2.
7 and a diode D1 are connected, and a time constant switching signal S6 is output.

Furthermore, in the series circuit of resistor R7 and diode D1,
A resistor R8 is connected in parallel, and a capacitor C2 is connected between the output side of the series circuit and ground.

To explain the function of the time constant switching controller 4 as described above, in the transition operation to the high-speed pull-in state,
The voltage at the output terminal of the voltage comparator IC2 increases, and the current flowing through the capacitor C2 and the resistor R8 as well as the diode D1 turns on, causing the resistor R7 to rise.
The voltage of the time constant switching signal S6 also increases due to the current flowing through the voltage comparator, and the voltage between the drain terminal and the source terminal of the field effect transistor Q1 turns on. ■The voltage at the output terminal of C2 falls and the diode D1 turns off, causing the voltage of the time constant switching signal S6 to fall only due to the change in the current flowing through the resistor R8. The terminal-source terminal is turned off.

That is, the switching from the high-speed retraction state to the normal state is performed with a gentle slope, and the reverse switching from the normal state to the high-speed retraction state is performed quickly.

Next, the operation of the embodiment configured as above will be explained. First, the phase difference signal S2, which is the output signal of the phase comparator 1, is integrated in the filter 2 to remove its high frequency components, and the oscillation frequency control signal S3 is input to the voltage controlled oscillator 3.

In this case, when the high-speed pull-in switching signal S5 instructs switching from the normal state to the high-speed pull-in state, the output voltage of the voltage comparator IC2 of the time constant switching controller 4 increases, and the time constant switching signal S6 increases. The voltage increases quickly as described above.

Therefore, the drain terminal and source terminal of the field effect transistor Q1 of the filter 2 are in an on state, and the resistance value therebetween is low. Then, the time constant of the filter 2 changes to a value that reduces the high-frequency component removal and integration ability, and the phase-locked circuit as a whole realizes a high-speed pull-in characteristic.

On the other hand, when switching from the high-speed pull-in state to the normal state is instructed, the output voltage of the voltage comparator IC2 of the time constant switching controller 4 decreases, and the time constant switching signal S6
The voltage decreases with a gentle slope as described above.

Therefore, the drain terminal and source terminal of the field effect transistor Q1 of the filter 2 are turned off, and the resistance value therebetween becomes high. Then, the time constant of the filter 2 changes to a value that increases the high-frequency component removal and integration capability, and the phase synchronization circuit as a whole achieves normal synchronization characteristics.

As described above, in the case of switching from the high-speed pull-in state to the normal state, the time constant switching signal S6 having a gentle slope compared to the reverse case is inputted from the time constant switching controller 4 to the filter 2. Therefore, the occurrence of disturbances in the switching operation is reduced.

Note that the present invention is not limited to the above-mentioned embodiments; for example, circuits other than those shown in FIGS. 2 and 3 may be used as long as they have the same effect.

〔Effect of the invention〕

As explained above, according to the present invention, the time constant switching of phase synchronization in the switching operation from the high-speed pull-in state to the normal synchronization state is performed with a gentle slope. This has the effect of reducing the occurrence of disturbances.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a time constant switching phase synchronized oscillator circuit for a magnetic disk storage device according to the present invention;
2 is a circuit diagram showing a specific example of the configuration of the filter shown in FIG. 1, and FIG. 3 is a circuit diagram showing a specific example of the configuration of the time constant switching controller shown in FIG. 1... Phase comparator, 2... Filter,
3... Voltage controlled oscillator, 4... Time constant switching controller, IC1... Operational amplifier, IC
2... Voltage comparator, Ql... Field effect transistor. Patent applicant Nippon Electric Co., Ltd. Agent Patent attorney Isamu Takahashi Figure 1, 54 2nd cause b Figure 3

Claims (1)

[Claims] (1) a phase comparator that detects a phase difference between a read data pulse signal read from a storage medium of a magnetic storage device and a read clock signal and generates a phase difference signal corresponding to the phase difference; a filter means for removing and integrating a high frequency component of the phase difference signal with a time constant switched based on a time constant switching signal and outputting an oscillation frequency control signal; In a phase-locked oscillator circuit having an oscillation means for oscillating and outputting a read clock signal, the circuit changes from a high-speed pull-in state to a normal state based on a high-speed pull-in switching signal that instructs slow or fast pull-in of the read clock signal with respect to the read data pulse signal. 1. A phase synchronized oscillator circuit comprising time constant switching control means for outputting a time constant switching signal having a gentler slope when switching to a state than in the opposite case.