JPH01258152A - Memory controller - Google Patents

Abstract

PURPOSE:To comparatively simplify the circuit constitution of a memory controller and to accelerate access to information even when mis-hit is generated by making access start simultaneously to both a cache memory and a main memory device. CONSTITUTION:At the time of making access to data by a central processing unit 21 which performs the storage of the data on the cache memory 23 as a memory device accessible at high speed and the main memory device 24 with an access time less than that of the cache memory, the access to a cache memory control means 25 and the main memory device 24 is started simultaneously. In other words, by making access even to the main memory device at a timing making access to the cache memory, no delay time is generated in the access to the main memory device 24 even when no targeted data exists in the cache memory 23. In such a way, it is possible to make access to the targeted data even when the mis-hit is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control device equipped with a cache memory. The present invention relates to a memory control device that has devised control when obtaining data from a computer.

"Prior Art" Cache memories are widely used in conjunction with large-capacity main storage devices from the perspective of improving the speed of data processing devices. In other words, if a cache memory is placed between the CPU (central processing unit) and the main memory as a storage device that has a small capacity and can operate at high speed, the main memory obtained when the CPU accesses the main memory Some of the information on the device can be stored in this cache memory. In this way, when the CPU accesses information again, it is possible to read the information at high speed by using the cache memory without accessing the main storage device.

"Problem to be Solved by the Invention" As described above, the cache memory itself has the character of copying a part of the data stored in the main memory, but
Nor does it always match the data stored in main storage. This is because there are usually multiple devices that can access the main memory, and the CP
When a device other than U rewrites the contents of the main memory, the contents will no longer match the contents of the cache memory.

For this reason, even if the CPU accesses the information, the corresponding information may not exist in the cache memory. Such a case will be referred to as a mishit in this specification. In conventional memory control devices, the main memory is accessed after it is determined that there is a mishit.

FIG. 4 shows how data is accessed in a conventional memory control device. First, as shown in FIG.
) can be sent to the controller.

Based on this, the DRAM controller changes the memory request signal 12 from H level to L level (
Figure b). In response to this memory request signal 12, tag data 13 as address data of data stored in the cache memory is output from a cache tag memory (not shown) (C in the same figure). Address valid signal 1
The time from when 1 is output to when tag data 13 is output is called tag access time T1.

The tag data 13 is compared with the address data output by the CPU by a comparator (not shown), and the comparison result 14 (d
) determines whether it is a mishit or not. The time required from the output of the address valid signal 11 until the mishit is determined is indicated by T2 in this figure.

Once a mishit is detected, the DRAM controller described above now activates the RAS (Row Address Strobe) signal 15.
(e) in the figure to start an access cycle to the DRAM. The delay up to this point is T
It is expressed as 3. FIG. 3f shows the CAS (column address strobe) signal 16.

As explained above, conventional memory control devices have a problem in that when there is no corresponding data in the cache memory, it takes a considerable amount of time to access the data.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory control device that can quickly access target data even in the event of a mishit.

"Means for Solving the Problems" The present invention provides (i) a cache memory as a memory element that can be accessed at high speed, (11) cache memory control means for controlling this cache memory, and (iii) (iv) a central processing unit that stores data in this main storage device and the cache memory; and (v) a main storage device that has a slower access time than a cache memory; (v) a central processing unit that stores data in the main storage device and the cache memory; A memory control device is provided with a cache memory control means and an access start control means for simultaneously starting access to a main storage device.

That is, in the present invention, by accessing the main memory at the same time as accessing the cache memory, there is no delay time in accessing the main memory even when the cache memory does not contain the target data. do not have.

"Example" The present invention will be described in detail below with reference to Examples.

FIG. 1 shows the system configuration of a data processing device in which this memory control device is used. CPU21
is connected by a data bus 22 to a cache memory 23 and a DRAM 24 serving as a main storage device.

The cache tag memory 25 is connected to the cache memory 23 by a tag address bus 26 that outputs the address of information stored in the cache memory 23. The address bus 27 of the CPLI 21 is connected to the DRAM 2
In addition to being connected to the tag address bus 26, a pass line 27U for transmitting the upper address information is also connected to a comparator 28, and is compared with the address information output from the tag address bus 26. The comparison result 14 of the comparator 28 is supplied to the output enable terminal of the cache memory 23 and the sequence control circuit 31. DRAM24 is
It is controlled by various control signals output from the sequence control circuit 31 and the DRAM controller 32.

FIG. 2 shows the memory control timing at the time of reading by the memory control device of this embodiment, and corresponds to the previous FIG. 4. This FIG. 2 will be explained together with FIG. 1.

When the address valid signal 11 is output from the CPU 21 as shown in FIG.
(b in the same figure) and RAS signal 15 (e in the same figure) are output simultaneously. In this way, the access cycle to the cache memory 23 and the access cycle to the DRAM 24 start simultaneously.

Incidentally, the cache memory 23 is accessed faster than the DRAM 24. Therefore, even after the tag data 13 (FIG. 2C) is output from the cache tag memory 25 and the comparison result 14 (FIG. 2D) of the comparator 28 appears, the DR
Access to AM24 will continue. If no action is taken then, after the necessary data is sent from the cache memory 23 to the data bus 22, the DR
Similar data will be output from AM24 to data bus 22 as unnecessary data.

In order to prevent the above-described disadvantages other than when a mishit occurs, the sequence control circuit 31 of this embodiment is configured to perform control to prevent the above-mentioned unnecessary data from being transmitted.

FIG. 3 shows the circuit configuration of the sequence control circuit. As shown in FIG. 1, the sequence control circuit 31 receives the memory request signal 12, CAS signal 16 right, and clear signal 41 from the DRAM controller 32. The comparison result 14 output from the comparator 28 is also input to the sequence control circuit 31.

Of these, the CAS signal 16 is supplied to the clock input terminal CLK of the first flip-flop circuit 42 in a logically inverted state. Also memo IJ IJ quest signal 12
is manually inputted to the clock input terminal CLK of the second flip-flop circuit 43 with its logic similarly inverted. The comparison result 14 and the clear signal 41 are input to the logic gate 44, and the logic determination result 45 is input to the clear input terminal CLR of the second flip-flop circuit 43 with its logic inverted. The second flip-flop circuit 43 outputs a Q-bit mask/memory request signal 46, which is supplied to the cache memory 23 and DRAM 24 as well as to the first flip-flop circuit 42. The logic is inverted and input to the clear terminal CLR. The mask/CAS signal 4 is output from the output terminal d of the first flip-flop circuit 42.
7 is now output, which is supplied to the DRAM 24 shown in FIG.

The operation of the memory control device having the above configuration will be explained with reference to FIG. 2 above.

After the address valid signal 11 shown in FIG. 2a changes to L level, the memory request signal 12 (FIG. 2b) and RAS
At the same time, signal 15 (e in the figure) changes to L level. When the memory request signal 12 changes to L level, the second
The flip-flop circuit 43 is set, and the mask memory request signal 46 becomes H level. As a result, an access request to the cache memory 23 and DRAM 24 is made.

When the tag data 13 (FIG. 2C) is output from the cache tag memory 25 as a result of the access by the mask memory request signal 46, the comparator 28 outputs the pass line 27.
This is compared with the upper address information appearing in 0. When there is a hit, the comparison result 14 is changed from the H level to the L level (solid line d in FIG. 2), and when there is a miss, it is held at the H level (broken line d in the same figure).

That is, in the event of a mishit, the logical determination result 45 remains at the H level, and the mask memory request signal 46 also remains at the H level. Therefore, when the reset power is not supplied to the first flip-flop circuit 42 and the CAS signal 16 as shown in FIG. A waveform mask/CAS signal 47 is output. As a result, desired data is outputted from the DRAM 24 onto the data bus 22 at the address determined by the RAS signal 15 and the mask/CAS signal 47 shown in FIG.

On the other hand, when the signal is hit, the comparison result 14 shown in FIG. 2d changes from the H level to the L level. As a result, the logic determination result 45 changes to L level, and the second flip-flop circuit 43 is reset.

As a result, the mask memory request signal 46 changes to L level, and the first flip-flop circuit 42 enters the reset state. In this state, even if the CAS signal 16 is supplied to the first flip-flop circuit 42, it is masked, and from its output terminal d! (The mask/CAS signal 47 held at the level is output. As a result, when the signal is hit, the sequence of the DRAM 24 is
This becomes an S-only refresh cycle. That is,
D after data is read from the cache memory 23
The access cycle of RAM24 causes data bus 2 to
2, unnecessary data is prevented from being output.

In the embodiments described above, a memory control device including a cache memory and a DRAM has been described. It goes without saying that the present invention can also be applied to a memory control device that is provided with a physical cache containing .

"Effects of the Invention" As described above, according to the present invention, since access to both the cache memory and the main storage device is started at the same time, the circuit configuration of the memory control device is relatively simple, and moreover, when there is a mishit, This also has the advantage of speeding up information access.

[Brief explanation of the drawing]

1 to 3 are for explaining one embodiment of the present invention, of which FIG. 1 is a system configuration diagram showing the configuration of a data processing device in which a memory control device is used, and FIG. 3 is a timing diagram showing the state of memory read control, FIG. 3 is a block diagram showing the circuit configuration of the sequence control circuit, and FIG. 4 shows the state of memory read control in the event of a miss in a conventional memory control device. FIG. 12...Memory request signal, 14...
...Comparison result, 21...cpu. 23...Cache memory, 24...DRAM. 31...Sequence control circuit, 47...
・Mask/CAS signal. Applicant Fuji Xerox Co., Ltd. Agent
Patent Attorney Umeo Yamauchi Figure 3

Claims (1)

[Claims] A cache memory, a cache memory control means for controlling this cache memory, a main storage device, a central processing unit that stores data in this main storage device and the above-mentioned cache memory, and this central processing unit. A memory control device comprising access start control means for simultaneously starting access to the cache memory control means and a main storage device when the device accesses data.