JPH01233970A - Controller for digital signal processing circuit - Google Patents

Abstract

PURPOSE:To prevent the disturbance of screen in the case of changeover to the special display by providing the 2nd transfer buffer holding a control data from the 1st transfer buffer in the timing of a vertical synchronizing signal and transferring the data to each supply destination of a digital signal processing circuit. CONSTITUTION:In case of updating of a control data or supply of a new data, a preparation is required. The preparation is implemented by applying processing to set a control data and an address data to a prescribed register of a microcomputer 21. When the preparation is finished, the microcomputer 21 monitors the incoming of the vertical synchronizing signal and fetches it by the detection. Thus, the microcomputer 21 recognizes the position of the vertical synchronizing signal. When the timing of the vertical synchronizing signal is recognized, the microcomputer 21 transfers the circuit data and address data set in the register in the timing of the vertical synchronizing signal to a decoder 22 respectively as serial data. Thus, the control data is stored respectively to D flip-flops 23, 24 and 25.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a control device that uses a central processing method to control a digital signal processing circuit that digitally processes a video signal. changes (supplies) various control data given to the digital signal processing circuit in synchronization with the vertical synchronization signal.
In this way, digital signal processing can be performed smoothly.

(Prior Art) Conventionally, a digital video signal processing circuit has been controlled by a central processing method using a microcomputer. FIG. 4 shows a block diagram of the configuration. In FIG. 4, 11 is a microcomputer, 12 is a decoder, and 16 is a digital video signal processing circuit. Microcomputer 11 is connected to decoder 12 via bus 17. The decoder 12 includes transfer D flip-flops 13, 14, 15, . . .
A common data line 18 connects the decoder 12 and the D flip-flop 13, 20A and 20.
B, 20C are D flip-flops 13.14.15
... and the digital video signal processing circuit 16. Also, 19A, 19B, 19
C is a signal line that guides a transfer destination selection signal from the decoder 12. Note that the following explanation will be based on a configuration that transfers three types of data.

In the operation of this configuration, first, the micro combi coater 11 sends necessary control data (for example, comparison reference values, coefficient data, etc.) to the digital video signal processing circuit 16 and an address to which this control data is to be transferred in a packet. The data is sequentially supplied to the decoder 12 in the format. The decoder 12 transfers the input control data to one of the D flip-flops 13, 14, 15, generates a selection signal by decoding the address signal, and transfers this signal to the D flip-flops 13, 14, 15. is applied as an output operation control signal.

Since the control data is transferred first to the D flip-flops 13, 14, and 15, they perform an output operation at the timing when the selection signal is input. As a result, the digital video signal processing circuit 16 performs deflection processing and first-speed signal processing.

Various control data necessary for predetermined circuits such as A/D and D/conversion processing are given, and the video signal is digitally processed.

By the way, digital video signal processing circuits can be used to perform normal processing such as digitally processing a video signal, converting it back to an analog signal, and outputting it for display, and to perform special processing such as freezing the screen, enlarging, reducing, strobe, etc. There is. When performing the latter special processing, since the normal processing screen is switched to the special processing screen, it is desirable that the timing of changing or supplying the control data be the same. If each control data is changed or newly supplied at inconsistent timing, the image quality will deteriorate at the moment of screen switching.

Therefore, the change or supply of control data must be completed within the vertical synchronization signal period or within a very short time even if it is outside of that period.

Considering the circuit of FIG. 4 from this point of view, the time from the start of special processing until the digital video signal processing circuit 16 completely enters the special processing state, that is, the time required for the microcomputer 11 to process multiple control data and addresses. The data are registered and sent to the decoder 12 sequentially using the bus 17.
Since the time for supplying the signal to the digital video signal sufficiently exceeds the vertical synchronization signal period, the digital video signal processing circuit 16 does not perform normal special processing even when the special image display period begins, causing disturbances in the image. I'll let you go.

(Problem to be Solved by the Invention) In a system in which a digital video signal processing circuit is controlled by a microcomputer, when a special display is performed, a data transfer period during which various control data necessary for special display processing is supplied to the digital video signal processing circuit. and the time required for its preprocessing sufficiently exceeds the vertical synchronization signal period,
There is a problem in that the image display period begins before the digital video signal processing circuit receives control data for special display, and the screen becomes distorted. Note that when returning from the special display to the normal display image, the problem of screen disturbance does not occur by displaying the special display screen stored in the memory until the control data for the normal display is complete.

SUMMARY OF THE INVENTION An object of the present invention is to provide a control device for a digital signal processing circuit that eliminates the above-mentioned problems and prevents screen disturbances when switching to a special display.

[Structure of the Invention] (Means for Solving the Problems) The present invention controls digital signal processing by transferring various control data necessary for digital signal processing of a video signal to a predetermined supply destination of a digital signal processing circuit. In the control device, the control data generated by the microcomputer is transferred to a first transfer buffer provided corresponding to each supply destination via a decoder at the timing of a vertical synchronization signal,
A second transfer buffer is provided that transfers the control data from the first transfer buffer to a predetermined supply destination at the timing of the vertical synchronization signal.

(Function) According to such a configuration, the first transfer buffer transfers the control data supplied via the microcomputer and the decoder to the second transfer buffer by applying the vertical synchronization signal.
It is held by Moe. Therefore, the second transfer buffer can transfer the control data all at once at the timing of the vertical synchronization signal, and the reference value data and coefficient data required for digital signal processing are changed all at once, causing screen holes. It is something to be avoided.

(Example) This invention will be explained below with reference to Examples.

FIG. 1 is a block diagram showing an embodiment of a digital signal processing circuit according to the present invention. In the figure, 21 is a microcomputer, 22 is a decoder, 26 is a digital video signal processing circuit, 23, 24, and 25 are transfer D flip-flops, and the microcomputer 21 and decoder 22 are connected by a bus 30. and D flip-flop 2
3.24.25 is the data line 31 and signal line 32A,
328, connected by 32C.

Therefore, in this embodiment, the D flip-flops 23°24,
Each D flip-flop 23 does not directly supply the data output from the D flip-flop 25 to the digital video signal processing circuit 26.
．． D flip 70 tubes 27, 28, 29 are provided between 24, 25 and the digital video signal processing circuit 26.

A vertical synchronizing signal generated by the digital video signal processing circuit 26 is introduced to these D flip-flops 27, 28, and 29 as an output operation control signal. However, this vertical synchronization signal
1 is also supplied.

The operation of such a configuration will be explained with reference to FIG. FIG. 2 is a flowchart showing the operation of the microcomputer 21.

When changing control data or supplying new data, preparation work is performed in step S11.

This operation is a process of setting control data and address data in a predetermined register of the microcomputer 21. When the preparation work is completed, the microcomputer 2
1 performs steps 812 and 813.

Step S12. S13 is a process of monitoring the input of a vertical synchronization signal and capturing it by detection. Thereby, the microcomputer 21 knows the order of the vertical synchronizing signal.

When the timing of the vertical synchronization signal is known, the microphone [cocomputer 21] performs step S14. S15. S
16 are executed in sequence, and the control data and address data hit in the register at the timing of the vertical synchronization signal are each converted into serial data and transferred to the decoder 22. The operation of the microcomputer 21 is now complete.

Note that when decoding each data created by the microcomputer 21, decoding start timing information is required, but the configuration of the signal path for such timing signals is omitted because it is not an invention related to the signal format. do.

In this way, control data is stored in the D-flip 70 tabs 23, 24, and 25, respectively. Here, the control data to be transferred to the D flip-flop 23 together with the address data to the address is a, the control data to be transferred to the D flip-flop 24 together with the data indicated by the address is to be the address C.
The control data to be transferred to the D flip-flop 25 at the same time is C. Figure 3 shows the above data A, a1B, b and C,
3 is a time chart showing the transfer operation of c.

In FIG. 3, (a) shows the vertical synchronization signal,
A vertical synchronizing signal period and one vertical scanning period are shown. (b
) indicates the operation of the microcomputer 21, and (C)
, (d), (e) show the operation of D flip-flop 23, 24, 25, respectively, and (f), IJ)
.

(h) are D flip-flops 27, 28, and 29, respectively.
shows the operation.

A period 41 shown in FIG. 3(b) is a processing period of step 311 explained in FIG. 2, and 42 is a processing period of step 812.
813 period. In this way, the microcomputer 21 monitors the preparatory work and the vertical synchronization signal at a certain timing, and updates the data A, a, and B at the timing of the vertical synchronization signal.
, b, C, and c are transferred in this order.

Since A and a are data whose transfer destination is the D flip 70 knob 23, as shown in (C), the control data a is transferred to the D flip 70 knob 23.
It is held in a flip-flop 23. The holding timing is when the selection signal obtained by decoding the address Δ is D.
It is determined by the voltage applied to the flip-flop 23.

After holding the data in this way, the D flip-flop 23
can supply data to the next stage D flip-flop 27. Similarly, the D flip-flop 24 holds control data b based on the address B (select signal), and the D flip-flop 25 holds control data C based on the selection signal based on the address C.

Therefore, even if the D flip-flops 23, 24, and 25 in the preceding stage hold data, the D flip-flops 27, 28, and 29 do not take in the output, that is, do not perform an output operation. The output operation is performed at the timing of the vertical synchronization signal. Therefore, at the timing of the next vertical synchronizing signal after the vertical synchronizing signal that the microcomputer 21 started transferring, the D flip-flop 27, 28° 29
Holds control data from 4.24.25 respectively.

This situation is shown in (f) and (g).

It becomes as shown in (h). Each of the control data a, b, and c is taken into each D flip-flop 27.28°29 all at once. When the D-flip 70 knob 27.28°29 holds the data, the digital video signal processing circuit 2
6, the digital video signal processing circuit 26 is changed or supplied with each control data at the same time. Moreover, since the timing of the data change (supply) is synchronized with the vertical synchronization signal, the data change (supply) is performed within the vertical synchronization signal period, and the special processing screen can be changed from the normal screen to the special processing screen without causing any screen disturbance. It is possible to switch to

In addition, in the above embodiment, the microcomputer 21 is
- Transfer of all data must be completed within the vertical scanning period, but if there is a large amount of data and it takes time, the D flip-flop 27.
28 and 29 may be driven.

[Effects of the Invention] As explained above, according to the present invention, it is possible to change (supply) control data within the first vertical signal period or even outside it, and to avoid image blurring. Enables screen switching without any screen switching.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a digital video signal according to the present invention (a block diagram showing one embodiment of a control device for a processing circuit, and FIGS. 12 and 3 provide detailed explanations of the present invention). FIG. 4 is a configuration diagram showing a conventional circuit. 21... Microcomputer, 22... Decoder; 24, 25... First D flip-flop, 26
...Digital video signal processing circuit, 27.28.29.
...Second D flip-flop. Agent Patent Attorney Shinji Ito Samurai No. 23゜Tough Illusion Figure 2 Figure 4

Claims (1)

[Scope of Claims] A control device for a digital signal processing circuit that supports digital signal processing by transferring various control data necessary for digital signal processing of a video signal to a predetermined supply destination of the digital signal processing circuit, comprising the steps of: and address data indicating the supply destination of the control data to a microcomputer that is generated in synchronization with the vertical synchronization signal from the digital signal processing circuit. Each data from this microcomputer is decoded, and the control data is common. a decoder which sequentially derives the address data to the data lines and derives the address data to separate signal lines as a selection signal instructing the supply destination, and a decoder which is provided corresponding to the supply destination at the timing of the selection signal from each signal line. a first transfer buffer that holds the control data; and a second transfer buffer that holds the control data from the first transfer buffer at the timing of a vertical synchronization signal and transfers it to each supply destination of the digital signal processing circuit. 1. A control device for a digital signal processing circuit, comprising a transfer buffer.