JPH01232755A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to process finely a semiconductor integrated circuit by a method wherein a device is formed into a constitution having a SOI structure consisting of semiconductor pillars, which are selectively shaped and erected from a semiconductor substrate, and an element isolation insulating film, which is formed at the bottom parts of the semiconductor pillars. CONSTITUTION:First, second and third films 22, 23 and 24, which are an insulating film, are laminated in order on a semiconductor substrate 21 and are selectively removed by an anisotropic etching technique of an RIE method and so on using a resist film as a mask to form semiconductor pillars 211. Then, insulative fourth and fifth films 25 and 26 are formed on the sidewalls of the pillars 211 by a CVD method or the like and are heat-treated to form an element isolation insulating film 27 between the substrate 21 and the pillars 211. Moreover, the first to fifth films 22-26 are removed from the entire surface at need or parts of the films are remained to form a semiconductor device on the pillars 211. Accordingly, a SOI structure having the pillars 211 of a good crystallizability can be easily formed and it becomes possible to process finely a semiconductor integrated circuit, to improve an integration degree and to contrive the improvement of the operating efficiency of a transistor.

Description

[Detailed Description of the Invention] [Summary] SO for separating elements of semiconductor devices, especially semiconductor integrated circuits
Regarding the I structure and the structure of the transistor element, we have eliminated parasitic capacitance and latch-up caused by the LOCO3 method and crystal defects caused by the SO3 method, recrystallization method, etc. The present invention includes an S01 structure consisting of a semiconductor pillar selectively etched from a semiconductor substrate and an element isolation insulating film at the bottom of the semiconductor pillar. The first device includes a semiconductor pillar having a multilayer conductive region cut into an element isolation insulating film on a semiconductor substrate, and a pair of lead electrodes and a gate electrode. The structure includes providing an emitter lead electrode, a base lead electrode, and a collector lead electrode on a semiconductor column having a multilayer conductive region cut out at an edge of element isolation vA on a semiconductor substrate.

[Industrial application field]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, the present invention relates to an S01 structure for separating elements of a semiconductor integrated circuit, and a structure and element number of a transistor element.
The present invention relates to a method for forming fine transistor elements in a semiconductor layer on a film.

[Conventional technology]

FIG. 7.8 is an explanatory diagram of a conventional example.

FIG. 7 is a configuration diagram of a semiconductor device according to a conventional semiconductor manufacturing method.

In the figure, bipolar and M
The OS transistor is a p-type or n-type Si substrate 1, 5i (n on 5ili3 on the h film 2) provided by So+ technology.
M OS jil area4. pMO3sII region 5. A bipolar transistor region 6 is formed and a source S is formed.

It is manufactured by forming a drain D, gate G, base B, emitter E, and collector C.

In addition, p-type or n-type Si substrate! , SiO□ film 2 and S
ij! ! No. 3 has an SOI structure formed by a method such as bonding two semiconductor wafers together or a recrystallization method.

FIG. 8 is an explanatory diagram of problems in a conventional semiconductor device and its manufacturing method, and shows a method (device isolation method) for defining a region for forming a transistor element or the like.

FIG. 5A shows the selective LOCO3 method, in which field insulating films 7a and 7b are formed by selectively oxidizing the Si substrate 1 using LOCO3. Note that 8 indicates a heat oxidation-resistant Si:IN4 film, and 9 indicates a channel cant.

This method has problems such as the generation of parasitic capacitance and a launch amplifier, which makes it difficult to increase the speed of transistor operation or miniaturize the transistor.

Figure (b) shows the SO8 method. In the figure, this device isolation method is to form a CVDI crystal S-crystal Si layer 1 by growing single crystal Si on a sapphire substrate 70 by selective CVD.

However, according to this method, there are problems that physical distortion occurs due to the difference in thermal properties between the CVD single crystal Si layer 11 and the sapphire substrate 70, and that the sapphire substrate 1o itself is expensive.

Figure (c) shows the recrystallization method, and in the figure,
The poly-Si film 12 selectively formed on the 5i02 film 2 on the Si substrate 1 is heat-treated with a laser or electron beam 13 through the oxide film 15 to recrystallize it to form a recrystallized Si layer 14. is forming.

Note that this method produces poor quality Si crystals due to recrystallization.
Unable to form large crystals.

FIG. 3(d) shows a process diagram related to the bonding method.

In the figure, first, a 5i02 film 2 is formed on one Si substrate 1, and then a 5i02 film 2 is formed on the other Si substrate 3 via a bonding agent 16.
Glue.

Next, the Si substrate 3 is patterned to isolate elements. Note that this method has a problem in that the processing accuracy is not good because the Si substrate 3 is formed into a fi film by polishing or etching.

Figure (e) shows a process diagram related to the SIMOX method,
In the figure, first, oxygen ions 17 are implanted into a Si substrate 1 by an ion implantation method to form an oxygen implanted layer 18, and then
The i-substrate 1 is separated into regions through an oxygen-implanted layer of 5iN.
form la.

Next, an epitaxial layer 19 is formed on the Si layer la,
It is then activated to form s;otjFI 18 a.

Furthermore, 5iJWIa and epitaxial I'l19 are patterned to isolate elements. Note that this method has problems in that the Si layer has poor crystallinity, is expensive, and has low throughput.

[Problem to be solved by the invention]

By the way, according to element isolation of conventional semiconductor integrated circuits and semiconductor devices constituting the same, transistor elements and the like are formed using an SOI structure related to SOI technology such as the selective LOCO8 method or the SO8 method.

For this reason, as shown in FIGS. 8(a) to 8(d), for example, in the selective LOCO3 method, parasitic capacitance and launch amplifiers adversely affect the transistor operating characteristics. It may lead to a decrease in belief n degree. Further, in the 301 structure of the SOS method, etc., there is a problem that thermal crystal distortion occurs and crystal defects are generated thereby, making it impossible to easily form 5ilq with good crystallinity at a low cost.

The present invention was created in view of the problems of the conventional examples, and prevents the occurrence of parasitic capacitance and launch amplifiers caused by the LOCO3 method and crystal defects caused by the SO3 method, recrystallization method, etc., and can be used from a single semiconductor substrate. The object of the present invention is to provide a semiconductor device and a manufacturing method thereof that make it possible to construct a vertical transistor element in a columnar semiconductor region that is element-isolated.

[Means to solve the problem]

The principle diagram of the semiconductor device and manufacturing method of the present invention is shown in FIG.
As shown in Fig. 2 and an example thereof shown in Figs. 3 to 6,
The first device is characterized in that it has a 5-ort structure consisting of a semiconductor pillar 211 selectively cut out from a semiconductor substrate 21 and an element isolation insulating film 27 at the bottom of the semiconductor pillar 211. Element isolation insulating film 3 on 31
Semiconductor pillar 211 with a multilayer conductive region cut into 9
The second device is provided with a pair of extraction electrodes S, D and a gate electrode G, and the second device is connected to the semiconductor substrate 61.
It is characterized in that a semiconductor column 211 having a multilayer conductive region placed in front of an upper element isolation insulator 71 is provided with an emitter extraction electrode ridge, a heat extraction electrode B, and a collector extraction electrode C. 1.2 of the manufacturing method on the semiconductor substrate 21
and 3. selectively removing the 1.2 and 3. films 22, 23.24 and the semiconductor substrate 21 to form semiconductor pillars on the semiconductor substrate 21; 211, forming fourth and fifth insulating films 25 and 26 on the side walls of the semiconductor pillar 211, and heat-treating the semiconductor substrate 21 to separate the semiconductor substrate 21 and the semiconductor pillar 211. a step of forming an iF1 insulating film 27 for the element between the steps;
5.26, and the method for manufacturing the first device is performed by forming a semiconductor layer 32 of one conductivity type and a semiconductor layer 33 of the opposite conductivity type on a semiconductor substrate 31. ,
One conductivity type semiconductor layer 34 and an insulating first and second film 35
．． 36 to form a multilayer semiconductor substrate 30; a step of selectively removing the multilayer semiconductor substrate 30 to form semiconductor pillars 211 on the semiconductor substrate 31; forming an insulating third film 38 on the entire surface; selectively removing the third film 38 to form the semiconductor pillar 2;
forming a sidewall insulating film 38a on the sidewall of the semiconductor substrate 11; and heat-treating the semiconductor substrate 31 to
forming an element-sized insulating film 39 between the semiconductor substrate 31 and the semiconductor pillar 211; and removing the 1.2 and 3 films 35, 36, and 38 on the entire surface; a step of selectively removing the first conductor film 40 and then forming an insulating fourth groove 42 on the entire surface of the semiconductor substrate 31; The fourth film 42 and the first conductor film 40 are selectively removed to expose the semiconductor pillar 211, and at the same time, the first extraction electrode 40a is formed, and then the exposed portion of the semiconductor pillar 211 is removed. forming a second conductive film 45 on the entire surface of the semiconductor substrate 31; selectively removing the second conductive film 45, and then forming a completely transparent sixth film 47 on the entire surface of the semiconductor substrate 31; selectively removing the sixth film 47 and the second conductive film 45; a step of exposing the fifth film 44 and also forming a second extraction electrode 45a; a step of forming a wA edge-type seventh film 49 on the entire surface of the semiconductor substrate 31; 49 and then forming a third conductor 11'251 on the entire surface of the semiconductor substrate 31; and selectively removing the third conductor film 51 to form a third conductor 11'251. The second device manufacturing method is characterized by forming an extraction electrode 51a and then forming an insulating eighth hole 53 on the entire surface of the semiconductor substrate 31. The first and second semiconductor layers 62 and 63 of one conductivity type, the semiconductor layer 64 of the opposite conductivity type, and the third and fourth conductors J!65 of one conductivity type
．． 66 and first and second insulating films 67 and 68 to form a multilayer semiconductor substrate 60; selectively removing the multilayer semiconductor substrate 60 and depositing a layer on the semiconductor substrate 61; a step of forming a semiconductor pillar 211; a step of forming an insulating third film 70 on the entire surface of the semiconductor substrate 61; and a step of selectively removing the third 11!70 to form the semiconductor pillar 211. forming a sidewall insulating film 70a on the sidewall; heat-treating the semiconductor substrate 61;
and the semiconductor pillar 211, the element portion i! iI insulating film 71
A first polycrystalline semiconductor film 72 is formed on the entire surface of the semiconductor substrate 6I.
and selectively removing the first polycrystalline semiconductor +1'272 to form a pseudo film 72a for the first extraction electrode, and then depositing an insulating film on the entire surface of the semiconductor substrate 61. Fourth membrane 74
selectively removing the fourth film 74 to form the first drawer T! , a step of forming a control sidewall insulating film 74a for the electrode, and completely removing the pseudo film 72a for the first extraction electrode to form a second opening 75; removing the film 67, 68, 70 by jl<1 dimension to expose the fourth semiconductor layer 66; and forming a first conductor film 76 on the entire surface of the semiconductor substrate 61. a step of selectively removing the first 5jL electric film 76;
The semiconductor layer 66 of the semiconductor layer 66 is exposed, and the first extraction electrode 7
6a, selectively removing the control sidewall insulating film 74a for the first extraction electrode, and then forming an insulating fifth film 78 on the entire surface of the semiconductor substrate 61; The fourth film 78 is selectively removed. forming an isolation insulating film 78a between
After that, a step of forming a second polycrystalline semiconductor film 80 on the entire surface of the semiconductor substrate 61, and a step of selectively removing the polycrystalline semiconductor film 80 to form a second lead-out electrode (l! film 80a) are performed. and then forming an insulating sixth film 82 on the entire surface of the semiconductor substrate 61, and selectively removing the sixth film 82 to form a control sidewall insulator for the second extraction electrode. A film 82a is formed, and then the second film 82a is formed.
A step of completely removing the pseudo film 80a for an extraction electrode and forming a second opening 84, forming a second conductor film 85 on the entire surface of the semiconductor substrate 61, and then removing an insulating seventh IC.
186 and further heat treatment to form an impurity diffusion layer 87 of the opposite conductivity type in a self-aligned manner;
The seventh film 86 is completely removed, and then the second conductor film 85 is selectively removed to form the control insulation If! for the second extraction electrode. 2B2a; and the second! The I electric body 1I985 is selectively removed to form a second extraction electrode 85a, and then the control insulation film 82a for the extraction electrode of the cylinder 2 is selectively removed, and then the entire surface of the semiconductor substrate 61 is formed. , forming an insulating eighth film 88; selectively removing the eighth film 88 to form an opening 89 exposing the fourth semiconductor layer 66; Third conductor film 9 electrically coupled to fourth semiconductor layer 66
The method is characterized by comprising a step of forming 0, thereby achieving the above object.

[Effect]

According to the SOI structure of the semiconductor device of the present invention, the semiconductor pillars 211 are provided in the element isolation insulating film 27''.

Therefore, a semiconductor element can be formed three-dimensionally on the semiconductor pillar 211.

Compared to conventional planar semiconductor elements, this makes it possible to finely process transistor elements, reduce parasitic capacitance, latch amplifiers, etc. as much as possible, speed up transistor operation, and It becomes possible to achieve high integration of devices.

Further, according to the manufacturing method of the present invention, one semiconductor substrate 21
The element isolation insulator 11927 is formed by heat-treating the bottom of the semiconductor pillar 211 cut out from the substrate.

Therefore, it is possible to eliminate the need for an expensive sapphire substrate as in the conventional example, form a semiconductor layer with better crystallinity than a silicon layer by recrystallization method or SIMOX method, and easily form an SO1 structure. becomes possible.

〔Example〕

Next, embodiments of the present invention will be explained with reference to the drawings. Figs. 1 to 6 show a semiconductor device according to an embodiment of the present invention and its device! ! FIG. 1 shows a principle diagram of an SOI structure related to a semiconductor device according to an embodiment of the present invention.

In the figure, 2I is a semiconductor substrate, and 27 is an element isolation insulating film, which is formed by heat-treating the semiconductor substrate 21 and the bottom of the semiconductor pillar 211. Reference numeral 211 denotes a semiconductor pillar, which is selectively carved out from the semiconductor substrate 21. Note that semiconductor devices such as transistor elements and storage capacitors C are formed on the semiconductor pillar 211.

This makes it possible to increase the degree of integration and density of semiconductor integrated circuits.

FIG. 2 is a process diagram showing the principle of forming the S01 structure of the semiconductor device according to the embodiment of the present invention.

In the figure, first insulating films 22, 23, and 24 are sequentially laminated on a semiconductor substrate 21. Note that the first film 2
2 is a 5in2 film etc. which is naturally oxidized on the semiconductor substrate 21, and may not be used in the embodiment of the present invention. That is, this means that the step of removing the naturally oxidized 5iOz film is omitted.

Further, the second film is a Si3N4 film or the like having thermal oxidation resistance, and has a function of protecting the semiconductor pillars 211 when forming the element isolation insulating film 27 together with the third film 24 (
Figure (a)).

Next, the first. The films 22, 23, and 24 of Nos. 2 and 3 and the semiconductor substrate 21 are subjected to RI using a resist film (not shown) as a mask.
selectively removed by anisotropic etching technology such as E method,
A semiconductor pillar 211 is formed (FIG. 2(b)).

Next, the fourth and fifth insulating films 25 and 26 are formed on the side walls of the semiconductor pillars 211 by CVD or the like. Note that the fifth film is a heat oxidation-resistant Si, N4 film, etc. (FIG. 3(C)).

Next, the semiconductor substrate 21 is heat-treated to form an element isolation insulating film 27 between the semiconductor substrate 21 and the semiconductor pillars 211 (FIG. 2(d)).

In addition, in the post-process of the formation process shown in FIG. 2(d), the first to fifth films 22 to 26 may be completely removed as necessary, or in some cases, a portion may be left to form a semiconductor device on the semiconductor pillar 211. do.

This makes it possible to increase the degree of integration and density of semiconductor integrated circuits.

FIG. 3 shows a structural diagram of a MOS transistor according to the first embodiment of the present invention.

In the figure, for example, in the case of an n-channel MOS transistor, 31 is a P-type or n-type Si substrate, and 39 is an element i! 1! It is an insulating film. Further, 211 is a semiconductor pillar, which has a pair of n° type epitaxial layers (32, 33) and an n° type epitaxial layer (32, 33).
It is formed by a type epitaxial layer (33).

Note that S or D is a source or drain lead electrode of a MOS transistor, and is an n-type poly-Si film (40, 51).
It is formed by patterning.

G is a gate electrode, which is formed by patterning an n-type poly-Si film (45).

As a result, a vertical n-channel MOS transistor can be three-dimensionally formed on the semiconductor pillar 21t.

Therefore, it is possible to achieve higher integration and higher density of the semiconductor ii and integrated circuit, and higher speed of transistor operation.

FIG. 4 shows a process diagram for forming a MOS transistor according to the first embodiment of the present invention.

In the figure, when forming, for example, an n-channel type MOS transistor, first an n° type epitaxial layer 32 with a thickness of about 0.5 [μm] is formed on an n-type or n-type Si substrate 31 by a CVD method or the like. p-type epitaxial jlii33.
The n” type epitaxial layer 34 is formed with a 5iJ4/SiO2 film having a thickness of about 0.2 (μm) and a film thickness of 5.3 (μm).
) about 5i(h[36) are sequentially grown and stacked to form a multilayer semiconductor substrate 30.

Thereafter, the resist film 37 is patterned to form a mask pattern with a predetermined width, for example, about 1 [μm] (FIG. 2(a)).

Next, using the resist film 37 as a mask, the multilayer semiconductor substrate 3
0 is selectively removed by anisotropic etching processing such as RIE method, and semiconductor pillars 211 with a width of l [μm] and a height of about 2 [μm] are formed on the Si substrate 31 (see FIG. b)).

Next, a 5i film containing a heat-resistant oxidation insulating film is formed using a CVD method or the like.
A J4 film/5iO1 film 38 is formed on the entire surface of the Si substrate 31 (FIG. 3(C)).

Thereafter, 5i3N grown on the -F part of the semiconductor pillar 211 and on the Si substrate 31 by anisotropic etching such as RIE method.
A sidewall insulating film 38a having an IF2 thickness of approximately 0.2 [μm] is left on the sidewalls of the a/SiO□Si substrate 31 and the semiconductor pillar 211 (see 117(d)).

Next, the SiO□ film 36 is removed by isotropic etching using an aqueous solution of HF (hydrofluoric acid), and then the Si substrate 31
is heat-treated to form three elementary M insulating films. Depending on the heat treatment conditions at this time, an SiO□ film having a thickness of about 7000 to 8000 cm can be formed on the Si substrate 31. Note that the bottom of the semiconductor pillar 211 is electrically and physically bonded to the Si substrate 21 by thermal oxidation treatment (see (e) in the same figure).
).

Next, by isotropic etching with an aqueous solution of phosphoric acid, etc., the side wall insulation 11! U'38a is completely removed.

Note that the 5in2 film is removed using an IIF aqueous solution or the like to expose the semiconductor pillars 211. After that, 5i7s,
The entire surface of the plate 31 is coated with n-poly 5il1 by low-pressure CVD or the like.
240 is grown, and the resist film 41 is further patterned (FIG. 2(r)).

Next, using the resist film 41 as a mask, the n1 type poly-Si film 40 is removed by anisotropic etching such as RIE, and then a Si film 42 is formed on the entire surface of the Si substrate 31 by CVD or the like. Furthermore, the resist film 43 is patterned (FIG. 4(g)).

Next, using the resist film 43 as a mask, the SiO□ film 42 and the n° poly 5il 1940 are removed by anisotropic etching such as RIE to expose the semiconductor pillars 211.

Note that the etching gas contains CF, 70% for the SiO□ film.
! , cce and 7o□ are used for the poly-Si film.

In addition, by selectively removing the n-poly Si film 40, the first lead electrode 4 connected to the n-epitaxial layer 32 is formed.
0a is formed, and the first extraction electrode 40a forms, for example, a source S of an n-channel MOS transistor. After that, a film thickness of 700 to 200 [included] is obtained by low-pressure CVD method, etc., and sto, P! 44 is formed and patterned. Note that the Sin film 44 becomes a gate oxide film ((h) in the same figure).

Furthermore, an N3 polySi film 45 is coated on the entire surface of the Sii plate 31
It is formed by a VD method or the like, and then a resist film 40 is formed as a gate resist pattern (FIG. 4(i)).

Next, using the resist film 46 as a mask,
Film 45 is selectively removed. Thereafter, a 5i (h film 47) is formed on the entire surface of the Si substrate 31. Furthermore, the resist film 48 is patterned (FIG. 4(j)).

Next, using the resist film 48 as a mask, a 5iOz film 4 is formed.
7 and n poly-Si film 45 are selectively removed using a predetermined etching gas using RIE or the like to expose semiconductor pillars 211. Then, as shown in FIG. By selectively removing the poly-Si film 45, a second extraction electrode 45a is formed which is capacitively coupled to the p-type epitaxial layer 33 via the gate oxide film 44, and the extraction electrode 45a is an n-channel MOS. Gates T, and poles G of the transistor are formed ((h) in the same figure).

Thereafter, a SiO□ film 49 is formed 9 on the entire surface of the temporary 5iyS by CVD or the like, and a resist film 50 is further formed (FIG. 4(i)).

Next, using the resist film 50 as a mask, the SiO□ film 49 is removed in a film pattern 9 to expose the upper part of the n′ epitaxial layer 34 of the semiconductor pillar 211. After that, an n° type poly-Si film 51 is formed on the entire surface of the substrate 31 by a low pressure CVD method,
Furthermore, a resist film 52 is formed (FIG. 3(m)).

Next, using the resist film 52 as a mask, an n9 type poly S
The i-film 51 is selectively removed to form the third extraction electrode 51a. In addition, the withdrawal power J? j51a forms, for example, the drain D of an n-channel MOS transistor. After that, a SiO□ film 53 is formed on the entire surface of the Si substrate 31.
The drain D is insulated ((n) in the same figure).

In this way, a vertical n-channel MO3) transistor can be manufactured. This makes it possible to increase the degree of integration and density of semiconductor integrated circuits.

FIG. 5 shows a structural diagram of a bipolar transistor according to a second embodiment of the invention.

In the figure, for example, in the case of an npn-type bipolar transistor, 61 is a ρ-type or n-type Si substrate, and 71 is an N insulating film. In addition, 211 is a semiconductor pillar, n° type epitaxial Ji62, 66, p type Si/p” type S+
Diffusion layer 87 and n-type epitaxial! It is formed from 63.65. In addition, C is n0 type epitaxial l'!
1162, and the n° type poly-Si film 7
This is an extraction electrode patterned by 6. Also, B
is the pace at which the P-type si/p'-type diffusion layer 87 is drawn out,
Drawer N patterned by P° type poly-Si film 85
jTr. E is an emitter for drawing out the n° type epitaxial layer 66, and is a drawing electrode patterned by n° type poly 5ilp390.

As a result, a vertical npn type bipolar transistor can be three-dimensionally formed on the semiconductor pillar 211. For this reason, semiconductor integrated circuits have become highly integrated.

It becomes possible to achieve higher density and faster transistor operation.

FIG. 6 shows a process for forming a bipolar transistor according to a second embodiment of the present invention.

In the figure, for example, in the case of an npn-type bipolar transistor, first, p-type or n-type 5i7s: plate 6! CV above
N° type epitaxial N62 with a film thickness of about 0.5 [μm] by D method etc., n type epitaxial M63 with a film thickness of about 0.3 (μm), ρ type epitaxial N64 with a film thickness of about 5000 (μm), 0.4 (μm) N-type epitaxial 165 of about [μm], n”X bitaxial N66 of about 0.3 (μm), Si3N4/5 of about 0.1 (μm)
totH67 and SiO□ film 6 of about 0.3 [μm]
8 are sequentially grown to form a multilayer semiconductor substrate 60. Thereafter, the resist film 69 is patterned to form a mask pattern having a predetermined width, for example, about 1 to 2 [μm] (FIG. 2(a)).

Next, using the resist film 69 as a mask, the multilayer semiconductor substrate 6
0 is selectively removed by an anisotropic etching process such as the RIE method to form a semiconductor pillar 211 having a width of 1 to 2 [μm] and a height of about 2 [μm] on the Si substrate 61.

Next, 5iJ containing a heat-resistant oxidation insulating film is formed using a CVD method or the like.
4/Sin, a film 70 is formed on the entire surface of the Si-based layer 61 (FIG. 6(C)).

Thereafter, 5tJa was grown on the top of the semiconductor pillar 211 and on the s+73 plate 61 by anisotropic etching such as RIE.
The /5Iot film 70 is removed and the sidewall insulating film 70a with a thickness of about 0.2 (um) is left on the sidewall of the semiconductor pillar 211 (
Figure (d)).

Thereafter, the Si substrate 61 is heat-treated to form an element isolation film 71. Depending on the heat treatment conditions at this time, the film thickness is 7,000 to 80 mm.
A SiO□ film of about 0.00 (in) can be formed on the Si substrate 61.The bottom of the semiconductor pillar 211 is electrically and physically insulated from the Si substrate 61 by thermal oxidation treatment (as shown in the figure). (e)).

Next, poly 5i 1272 is formed on the entire surface of the Si substrate 61 by low-pressure CVD or the like, and then the resist film 73 is patterned (FIG. 6(f)).

Next, using the resist film 73 as a mask, the poly-Si film 7 is
2 is selectively removed by an anisotropic etching process such as RIE to form a collector lead electrode dummy film 72a. After that, SiO is deposited on the entire surface of the Sii plate 61 by CVD method or the like.
□11i74 is formed ((g) in the same figure).

Next, the entire surface of the Si substrate 61 is anisotropically etched by RIE method or the like, and the extraction electrode control sidewall insulating film 74a is formed on the sidewall of the semiconductor pillar 211 in a self-aligned manner (
Figure (h)).

Thereafter, the entire surface of the collector lead electrode dummy film 72a is removed by isotropic etching using a predetermined etching solution, thereby forming an opening 75. Furthermore, Si3N4/5i (h
The film 67 and the sidewall insulating film 70a are selectively removed, and an n-type epitaxial I! 162.6
6 is exposed ((i) in the same figure).

Next, an n° type poly-Si film 76 is formed on the entire surface of the Si substrate 61 by low pressure CVD or the like, and the opening 75 is filled. Thereafter, the resist film 77 is patterned (FIG. 6(j)).

゛Next, using the resist film 77 as a mask, r? The n' type poly S1 film 76 is selectively removed by an anisotropic etching process such as the IE method, and the n' type epitaxial layer 66 is exposed (FIG. 4(k)).

Furthermore, using a resist film (not shown) as a mask, an n-type polyS
By patterning the i-film 76, the first drawer 1
A pole (collector C) 76a is formed.

After that, the collector extraction electrode control side wall insulating film 74a is heated with HF.
The SiO□ film 78 is removed by wet etching with an aqueous solution such as
The film shape 8 is formed, and then the resist film 79 is patterned (
Same figure (1)).

Next, using resist M79 as a mask, 5i02n'J
78 is patterned to form a collector/base isolation insulating film 78a. After that, low pressure C is applied to the entire surface of the Si substrate 61.
A poly-Si film 80 is formed by a VD method or the like, and a resist film 81 is further patterned (FIG. 4(m)).

Next, using the resist film 8I as a mask, the poly-Si film 80
By patterning, a base extraction electrode dummy film 80a is formed. After that, CVD was applied to the entire surface of the 31 substrate 61.
5i02119B2 is formed by a method or the like, and the resist film 83 is further patterned ((n) in the same figure).

Next, using the resist film 83 as a mask, the SiO□ film 82 is
By patterning, base extraction electrode control insulation JIQ82a is formed. Then the base extraction electrode gummy
Wl 80a was completely removed using a specified etching solution,
Opening 8 forming the active region of the bipolar transistor
form 4. Furthermore, the sidewall insulating film 70a exposed in the opening 84 is removed using an aqueous solution such as phosphoric acid/HF, and the n-type epitaxial layer 63, 65 and the p-type epitaxial layer 64 are removed.
((O) in the same figure).

Next, p is deposited on the entire surface of the Si substrate 61 by a low pressure CVD method or the like.
A type poly 5illff is formed and the opening 84 is filled. After that, 5iO is applied to the entire surface of the Si substrate 61 by CVD method or the like.
1 film 86 is formed, and the Si substrate 61 is further heat-treated to form a p-type Si/ρ''Si diffusion layer 87 in a self-aligned manner ((P) in the same figure).

Furthermore, the SiO□ film 86 is completely removed, and the p-type poly-Si film 85 is selectively removed using a resist film (not shown).
The base extraction electrode control insulating film 82a is exposed (see figure (Q)
)).

Next, using a resist film (not shown) as a mask, p' type poly 5
The third extraction electrode (base B) 85a is formed by patterning the ilp 185. Thereafter, the base extraction electrode control insulating film 82a is removed, and a SiO□ film 88 is formed on the entire surface of the Si substrate 61 by CVD or the like.
)).

Next, using a resist film (not shown) as a mask, 5iOtW
By patterning J, 88, the semiconductor pillar 211
An opening 8 exposing the pitaxial layer 66 at the top of the
9 is formed, and then the n-type poly-Si film 90 is patterned to form a third extraction electrode (emitter E) ((S) in the same figure).

This makes the vertical npn bipolar transistor +
! ! can be built. Therefore, it becomes possible to achieve higher integration and higher density of semiconductor integrated circuits.

In this way, the semiconductor pillars 21 are placed on the element isolation insulating film 27.
1 is provided. Therefore, a three-dimensional vertical n-channel MO3) transistor or an npn-type bipolar transistor can be manufactured on the semiconductor pillar 211.

As a result, compared to conventional planar semiconductor elements, for example, it is possible to microfabricate transistor elements, reduce parasitic capacitance and launch-up, etc., increase the speed of transistor operation, and It becomes possible to achieve high integration of semiconductor devices.

Further, according to the manufacturing method of the present invention, one S'r substrate 31
The element isolation insulating films 39 and 71 are formed by heat-treating the bottoms of the semiconductor pillars 211 cut out from the semiconductor pillars 211 and 61.

This eliminates the need for an expensive sapphire substrate as in conventional examples, and multilayer semiconductor substrates with better crystallinity than silicon layers made by recrystallization or SI'MOX methods.
It becomes possible to form an SOI structure easily.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to easily form a 5OItll structure having semiconductor pillars with good crystallinity, and also to form a three-dimensional vertical semiconductor element in the semiconductor layer.

Therefore, compared to the conventional example, it becomes possible to finely process the semiconductor integrated circuit, improve the degree of integration, and improve the performance of transistor operation.

This makes it possible to manufacture compact and high-performance semiconductor devices.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a principle diagram of an SOI structure of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a process diagram of the formation principle of an SOI structure according to a semiconductor device of an embodiment of the present invention. , FIG. 3 is a structural diagram of a MOS transistor according to the first embodiment of the present invention, FIG. 4 is a formation process diagram of a MOS transistor according to the first embodiment of the present invention, and FIG. FIG. 6 is a structural diagram of a bipolar transistor according to a second embodiment of the invention; FIG. 6 is a formation process diagram of a bipolar transistor according to a second embodiment of the invention; FIG. 7 is a diagram of a conventional semiconductor manufacturing method. Structural diagram of semiconductor device FIG. 8 is an explanatory diagram of problems of a conventional semiconductor device and its manufacturing method. (Explanation of symbols) ! , 21.31.61...Si substrate (semiconductor substrate),
22.35.67...1st (D'ffJ (Sia
N4 or Signnri), 23... second film (Si, N, /SiO□ film), 2
4.36.68...Third film (SiO□ film), 25.
...Fourth film (SiJa or SiO□ film), 26.38
．． 70-...Fifth film (SiJ4/5tozlff)
, 27.39.71... element isolation insulating film, 211...
・Semiconductor layer, 2.7a, 15, 42, 44, 47, 49°53.6B
, 74.78, 82, 86.88... SiO□ film (oxide film), 3... Si layer, 4... nMO3 region, 5... pMOS Sl region, 6... bipolar Region, 7b...Field insulating film, 8...5iJ4 film (thermal oxidation resistant insulating film), 9...Channel cant, 70...Sapphire substrate, 11.CVD single crystal 5iliJ, 12.72.80 ...Po'JSiv (Chapter 1.2 (7)
Polycrystalline semiconductor III), 13... Laser or electron beam, 14... Recrystallized Si layer, ! 6... Bonding agent, 30.60... Multilayer semiconductor substrate, 32.34, 62.66... n9 epitaxial N (
1st or 5th one conductivity type semiconductor IFi), 33.64・
...p-type epitaxial layer (second or third semiconductor layer of opposite conductivity type), 37.4+, 43.4G, 4B, 50.52°69.7
3.7? , 79.81.83... Resist film, 38a, 70a... Side wall insulating film, 40.45, 51, 76.90-n' type poly 5ilI9
(polycrystalline semiconductor Wi containing impurities of one conductivity type), 40a...source S (extracting electrode or first extracting electrode S
), 45a...G)G (gate electrode or second extraction electrode G), 51a...Drain D (extraction electrode or third extraction electrode), 63.65...n-type epitaxial layer (gate electrode or second extraction electrode G), 63.65...n-type epitaxial layer (gate electrode or second extraction electrode G), 2 or 4), 72a...Collector extraction electrode dummy film (pseudo-image film for the first extraction electrode), 74a...Collector extraction electrode control side wall insulating film (first extraction electrode Control side wall insulating film for electrode), 75.84.89...opening, 78a...collector/base isolation insulating film (interelectrode isolation insulating film), 80a...base extraction electrode dummy F! (i-pseudo film for second lead-out bridge), 82a...Base lead-out electrode control insulating film (control insulating film for second lead-out), 85...p type poly-Si film (opposite conductivity type) (polycrystalline semiconductor film containing impurities), 87... p-type Si/p'Si diffusion layer (opposite conductivity type impurity diffusion layer), 85a... second drawer 'yJ, pole (base B) ,7
6a... first extraction electrode (collector C), 90...
Third extraction electrode (emitter E). Fig. 1 (a) is a principle diagram of an SOI structure related to half-mounting according to an embodiment of the present invention; Fig. 2 is a diagram showing the SOI structure O formation principle related to a semiconductor device according to an embodiment of the present invention (see C111). (b) (c) Present invention 0 implementation 1 ``O semiconductor device: ζ related SCI + beak O formation principle process diagram jI 2 v! J (Part 2) (d) Regarding the semiconductor device according to the embodiment of the present invention; Figure 2 (Part 3) Part 1 of the present invention: Information on the λ40S transistor according to the embodiment Fig. 3 (a) (b) (C) Formation process diagram of the subject S transistor according to the first embodiment of the present invention t! Ii4 Figure (Part 1) (d) (e) (f) National policy for the formation process of MOS (Rannostar) according to the first embodiment of the present invention Figure (Part 2) (i) (j) (h) CL) Book National policy for the formation process of the MOS transistor according to the embodiment of Ml of the invention Figure 4 (Part 4) (m) (n) National policy 4 for the formation process of the MOS transistor according to the first embodiment of the invention Figure (Part 5) (b ) (c) (d) Regarding the second implementation θ of the present invention, the formation process of the bipolar trannosta Figure 6 (Part 2) of the national policy Fig. 6 of the process of forming a pipolar tranbesta Fig. 6 (Part 3) (h) (i) (j) Fig. 6 of the process of forming the pipolar tranvester according to the second embodiment of the invention (Part 4) (m) Forming step of the no-quipolar transistor according to the second embodiment of the present invention 6 Figure (No. 5) (n) Step of the forming process of the no-quipolar transistor according to the second embodiment of the present invention Cylinder 6 Figure (Part 6) (Q) (S) Kun2C embodiment of the present invention: Formation process of a piebola transnostar according to national policy Figure 6 (Part 7) Horizontal I of a semiconductor device according to a conventional semiconductor manufacturing method Figure 7 (a) Selection LOCO8 method/'lI CVDjlla+aSil (b) SOS method (c) Recrystallization method Semiconductor devices and their manufacturing method related to conventional examples ) Explanation of the amount of semiconductor components and their manufacturing method related to conventional examples 0 issues National policy Figure 8 (Part 2)

Claims (6)

[Claims] (1) It is characterized by having an SOI structure consisting of a semiconductor pillar (211) selectively carved out of a semiconductor substrate (21) and an element isolation insulating film (27) at the bottom of the semiconductor pillar (211). Semiconductor equipment. (2) Insulating first, second and third on the semiconductor substrate (21)
the first, second and third films (22, 23, 24) and the semiconductor substrate (21) are selectively removed; 2
1) forming a semiconductor pillar (211) on the semiconductor substrate (21); forming fourth and fifth insulating films (25, 26) on the side walls of the semiconductor pillar (211); The semiconductor substrate (
An element isolation insulating film (
27), and forming the first, second, third, fourth and fifth films (22, 23, 24,
25, 26) selectively removing. 25, 26). (3) Element isolation insulating film (39) on semiconductor substrate (31)
A semiconductor pillar (211
), a pair of extraction electrodes (S, D) and a gate electrode (G
). (4) On the semiconductor substrate (31), a semiconductor layer of one conductivity type (
32), a semiconductor layer (33) of opposite conductivity type, a semiconductor layer (34) of one conductivity type, and first and second insulating films (35,
36) to form a multilayer semiconductor substrate (30), and selectively removing the multilayer semiconductor substrate (30) to form semiconductor pillars (211) on the semiconductor substrate (31). a third insulating film (3) on the entire surface of the semiconductor substrate (31);
8); selectively removing the third film (38) to form a sidewall insulating film (38a) on the sidewall of the semiconductor pillar (211); 31) to form an element isolation insulating film (39) between the semiconductor substrate (31) and the semiconductor pillar (211), and the first, second and third films (35, 36, 38), and then forming a first conductive film (40) on the entire surface of the semiconductor substrate (31); selectively removing the first conductive film (40); After that, an insulating fourth film (4) is applied over the entire surface of the semiconductor substrate (31).
2), selectively removing the fourth film (42) and the first conductor film (40) to expose the semiconductor pillar (211); forming an extraction electrode (40a) and then forming an insulating fifth film (44) on the exposed portion of the semiconductor pillar (211); and forming a second conductor on the entire surface of the semiconductor substrate (31). Membrane (45
), selectively removing the second conductive film (45), and then forming an insulating sixth film (45) on the entire surface of the semiconductor substrate (31).
7), and selectively removing the sixth film (47) and the second conductor film (45) to form a fifth film (44) of the semiconductor pillar (211).
) and forming a second extraction electrode (45a) at the same time, and forming an insulating seventh film (45a) on the entire surface of the semiconductor substrate (31).
9), selectively removing the seventh film (49), and then forming a third conductive film (51) on the entire surface of the semiconductor substrate (31); The third conductor film (51) is selectively removed, and the third conductor film (51) is selectively removed.
A method for manufacturing a semiconductor device, comprising the steps of: forming an extraction electrode (51a), and then forming an insulating eighth film (53) on the entire surface of the semiconductor substrate (31). (5) Semiconductor pillar (211) having a multilayer conductive region carved into the element isolation insulation (71) on the semiconductor substrate (61)
, the emitter extraction electrode (E) and the base extraction electrode (
A semiconductor device characterized in that it is provided with a collector extraction electrode (C) and a collector extraction electrode (C). (6) On a semiconductor substrate (61), first and second semiconductor layers (62, 63) of one conductivity type and a semiconductor layer (62, 63) of an opposite conductivity type are provided.
4) and third and fourth conductive layers (65, 66) of one conductivity type.
and first and second insulating films (67, 68) to form a multilayer semiconductor substrate (60); selectively removing the multilayer semiconductor substrate (60); A step of forming a semiconductor pillar (211) on a semiconductor substrate (61), and a step of forming an insulating third film (7) on the entire surface of the semiconductor substrate (61).
0); selectively removing the third film (70) to form a sidewall insulating film (70a) on the sidewall of the semiconductor pillar (211); 61) to form an element isolation insulating film (71) between the semiconductor substrate (61) and the semiconductor pillar (211); forming a crystalline semiconductor film (72); selectively removing the first polycrystalline semiconductor film (72) to form a pseudo film (72a) for a first extraction electrode; A step of forming an insulating fourth film (74) on the entire surface of the substrate (61), and selectively removing the fourth film (74) to form a control sidewall insulator for the first extraction electrode. forming a film (74a); and removing the entire surface of the pseudo film (72a) for the first extraction electrode to form a second opening (75);
, 2 and 3 (67, 68, 70) to expose the fourth semiconductor layer (66); Body membrane (7
6) and selectively removing the first conductor film (76) to form a fourth conductor film (76).
A step of exposing the semiconductor layer (66) and forming a first extraction electrode (76a), selectively removing the control sidewall insulating film (74a) for the first extraction electrode, and then An insulating fifth film (78) is formed on the entire surface of the semiconductor substrate (61).
), selectively removing the fifth film (78) to form an interelectrode isolation insulating film (78a), and then forming the semiconductor substrate (
61) forming a second polycrystalline semiconductor film (80) on the entire surface, and selectively removing the polycrystalline semiconductor film (80) to form a pseudo film (80a) for a second extraction electrode. Then, an insulating sixth film (82) is formed on the entire surface of the semiconductor substrate (61).
selectively removing the sixth film (82) to form a control sidewall insulating film (82a) for the second extraction electrode, and then forming a pseudo-layer for the second extraction electrode. A step of removing the entire surface of the film (80a) and forming a second opening (84), and forming a second conductor film (85) on the entire surface of the semiconductor substrate (61).
) and then an insulating seventh film (86) are successively formed, followed by heat treatment to form an impurity diffusion layer (86) of the opposite conductivity type.
7) in a self-aligned manner, and removing the seventh film (86) entirely and then selectively removing the second conductor film (85) to form the second extraction electrode. a step of exposing a control insulating film (82a) for the first conductor; and selectively removing the second conductive film (85) to
After that, the control insulating film (82a) for the second lead-out electrode is selectively removed, and an eighth insulating film (85a) is formed on the entire surface of the semiconductor substrate (61). 88), selectively removing the eighth film (88) to form an opening (89) exposing the fourth semiconductor layer (66);
A method for manufacturing a semiconductor device, comprising the step of: thereafter forming a third conductor film (90) electrically coupled to the fourth semiconductor layer (66).