JPH01238174A - Vertical mosfet - Google Patents
Vertical mosfetInfo
- Publication number
- JPH01238174A JPH01238174A JP63066328A JP6632888A JPH01238174A JP H01238174 A JPH01238174 A JP H01238174A JP 63066328 A JP63066328 A JP 63066328A JP 6632888 A JP6632888 A JP 6632888A JP H01238174 A JPH01238174 A JP H01238174A
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- gate electrode
- diffusion region
- electrode
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009792 diffusion process Methods 0.000 claims description 43
- 239000000758 substrate Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 21
- 230000015556 catabolic process Effects 0.000 description 10
- 239000012535 impurity Substances 0.000 description 8
- 230000005684 electric field Effects 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 241000772415 Neovison vison Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は縦型ＭＯＳＦＥＴの耐圧向上とオン抵抗低減に
関するものである。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to improving the breakdown voltage and reducing the on-resistance of a vertical MOSFET.
（ロ）従来の技術
縦型Ｄ Ｓ Ａ （Ｄｉｆｆｕｓｉｏｎ ５ｅｌｆ Ａ
ｌｉｇｎｍｅｎｔ ）構造の縦型ＭＯ５ＦＥＴは一平面
上に多数の素子（セル）を等間隔に並べることにより高
耐圧化と大電流化が図られ、高電圧高速スイッチング用
として使用されている（特開昭６１−８０８５９、Ｈｏ
ｔＬ ２９／７８）。(b) Conventional technology Vertical DSA (Diffusion 5elf A)
A vertical MO5FET with a lignment) structure has a high breakdown voltage and a large current by arranging a large number of elements (cells) at regular intervals on one plane, and is used for high-voltage, high-speed switching (Japanese Patent Application Laid-Open No. 61-80859, Ho
tL 29/78).
断る構造の縦型ＭＯ３ＦＥＴは、第５図及び第６図に示
す如く、底部に高濃度Ｎ＋型層（１）を有するＮ−型シ
リコン基体（２）をドレインとして、その表面上に所定
の間隔でゲート電極（ポリＳｉゲート） （３）が配置
され、このゲート電極（３）の下にチャンネル部を作る
ように基体（２）表面にＰ型拡散領域（４）とＮ１型ソ
ース領域（５）を形成したもので、ゲートへの電圧印加
によってゲート下のＰ型拡散領域（４）（チャンネル部
）を通るドレイン電流１゜、を制御するようにＭＯＳ
Ｆ ＥＴを動作させるものである。As shown in FIGS. 5 and 6, a vertical MO3FET with a vertical structure has an N- type silicon substrate (2) having a high concentration N+ type layer (1) at the bottom as a drain, and a layer formed at a predetermined interval on the surface thereof. A gate electrode (poly-Si gate) (3) is arranged, and a P-type diffusion region (4) and an N1-type source region (5) are formed on the surface of the substrate (2) to form a channel section under this gate electrode (3). ), and the drain current (1°) passing through the P-type diffusion region (4) (channel part) under the gate is controlled by applying voltage to the gate.
This is what operates the FET.
従来の縦型ＭＯ３ＦＥＴの各セル（β）の形状は、第６
図に示すように四角形となって等間隔で縦横方向に配列
され、四角形の中心からソース電極を取出し、ゲート電
極（３）からはその上の絶縁膜のスルーホールを通して
共通のゲート電極を取出すようになっている。The shape of each cell (β) of a conventional vertical MO3FET is
As shown in the figure, they are arranged in a rectangular shape at equal intervals in the vertical and horizontal directions, and the source electrode is taken out from the center of the rectangle, and the common gate electrode is taken out from the gate electrode (3) through a through hole in the insulating film above it. It has become.
そして、各セル（６）のチャンネル部形成にあたっては
、ゲート電極（３）を利用したセルファライン技術によ
りＰ型拡散領域（４）とソース領域（５）を形成するが
、ゲート電極（３）によるセル（６）形状が四角形を成
すことにより、セル印）のコーナー部（７）への不純物
拡散が他の部分（辺部）への不純物拡散に比べて少なく
、従ってコーナ一部（７）のチャンネル部は凸型の球面
形状のＰＮ接合を形成し、逆バイアス時の電界強度が他
よりも大きくなる。その為、セル（ρ）のコーナ一部（
７）で電界集中を発生し、この部分における耐圧が縦型
ＭＯ３ＦＥＴの耐圧を決定していた。尚、（８）はチャ
ンネル部の輪郭を示す、そのうえ、不純物濃度が薄くな
るので、コーナ一部（７〉が他の辺部より早くオンし、
リークが発生したり、動作上電流分布が不均一となる為
低Ｖａｓ（ｏｆｆ）化の妨げになっていた。Then, in forming the channel part of each cell (6), a P-type diffusion region (4) and a source region (5) are formed by self-line technology using the gate electrode (3). Since the cell (6) has a rectangular shape, the impurity diffusion into the corner part (7) of the cell mark is smaller than the impurity diffusion into other parts (side part). The channel portion forms a convex spherical PN junction, and the electric field strength at the time of reverse bias is larger than that of other parts. Therefore, part of the corner of the cell (ρ) (
7) causes electric field concentration, and the withstand voltage at this portion determines the withstand voltage of the vertical MO3FET. In addition, (8) shows the outline of the channel part, and since the impurity concentration is thinner, the corner part (7>) turns on earlier than the other side parts.
Leakage occurs and current distribution becomes non-uniform during operation, which hinders lowering Vas(off).
（ハ）発明が解決しようとする課題
このように、従来の縦型ＭＯＳ Ｆ ＥＴはセル（りの
コーナ一部（７）で耐圧が決定されてしまう欠点があっ
た。また、コーナ一部（７）のＰＮ接合の曲率を緩和す
る為チャンネル部を浅くすることができず、従ってセル
（りの微細化が難しい欠点があった。更には微細化が困
難である為、ＭＯＳＦＥＴのチャンネル幅ＧＷ（セルの
周囲長の総和）を増大してオン抵抗Ｒｎ５（ｏｎ）を減
少することも困難である欠点があった。(c) Problems to be Solved by the Invention As described above, the conventional vertical MOSFET has the disadvantage that the withstand voltage is determined by a part (7) of the corner (7) of the cell. 7) In order to alleviate the curvature of the PN junction, the channel part cannot be made shallow, which has the disadvantage that it is difficult to miniaturize the cell.Furthermore, since miniaturization is difficult, the channel width GW of MOSFET It is also difficult to reduce the on-resistance Rn5(on) by increasing the total circumferential length of the cells.
（ニ）課題を解決するための手段
本発明は斯上した欠点に鑑み、チャンネル部のコーナ一
部（２３）が形成するＰＮ接合が凹型の曲面を形成する
ようにＰ型拡散領域（１３）を格子状に形成し、ゲート
電極（１５）は夫々が独立するようアイランド状に形成
することにより、コーナ一部り２３）での耐圧劣化を防
止した縦型ＭＯ３ＦＥＴを提供するものである。(d) Means for Solving the Problems In view of the above-mentioned drawbacks, the present invention provides a P-type diffusion region (13) such that the PN junction formed by the corner part (23) of the channel portion forms a concave curved surface. By forming the gate electrodes (15) in a lattice shape and forming the gate electrodes (15) in an island shape so that each gate electrode (15) is independent, a vertical MO3FET is provided in which breakdown voltage deterioration at corner portions (23) is prevented.
（ホ）作用
本発明によれば、コーナ一部（２３）のＰＮ接合が凹型
の曲面形状を成すので、電界が分散され、集中は起らな
い。また、チャンネルのコーナ一部（７）は他の部分よ
り不純物濃度が高くなる為、リーク電流源にはならず、
低ｖａｓ（ｏｆｆ）化が容易である。(E) Function According to the present invention, the PN junction at the corner portion (23) has a concave curved shape, so the electric field is dispersed and no concentration occurs. In addition, since the impurity concentration in the corner part (7) of the channel is higher than in other parts, it does not become a leakage current source.
It is easy to lower the vas (off).
（へ）実施例
以下、本発明の一実施例を図面を参照しながら詳細に説
明する。(F) Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図及び第２図は本発明の縦型ＭＯＳ Ｆ ＥＴを示
す平面図及びＡＡ線断面図を示す。（１１）は裏面にド
レイン電極が設けられる比較的低比抵抗のＮ１型シリコ
ン半導体基板、（１２）は基板（１１）表面に設けられ
共通のドレイン領域となる比較的高比抵抗のＮ型エピタ
キシャル層、（１３）はＰ型拡散領域、（１４〉はＮ＋
型拡散領域（ソース領域）、（１５）はポリシリコンか
ら成るゲート電極、（１６）はＣＶＤ酸化膜、（１７）
は共通ゲート電極、（１８）は共通ソース電極、（１９
）はＰ型拡散領域（１３）とＮ＋型拡散領域（１４）と
でゲート電極（１５）下に形成きれるチャンネル部を示
す。1 and 2 show a plan view and a sectional view taken along the line AA of the vertical MOS FET of the present invention. (11) is a relatively low specific resistance N1 type silicon semiconductor substrate with a drain electrode provided on the back surface, and (12) is a relatively high specific resistance N type epitaxial substrate provided on the surface of the substrate (11) and serves as a common drain region. layer, (13) is P-type diffusion region, (14> is N+
Type diffusion region (source region), (15) is a gate electrode made of polysilicon, (16) is a CVD oxide film, (17)
is a common gate electrode, (18) is a common source electrode, (19)
) indicates a channel portion that can be formed under the gate electrode (15) by the P type diffusion region (13) and the N+ type diffusion region (14).
Ｐ型拡散領域（１３）は、本願の特徴とする如く格子状
に形成され、残るエピタキシャル層（１２）表面上を覆
うようにゲート酸化膜（２０）を介してゲート電極（１
５）が配設される。ゲート１極（１５）の形状は一例と
して四角形状を成し、夫々がエピタキシャル層（１２）
上に単独で独立して配置される。その為、本願のＭＯＳ
ＦＥＴはアイランド状のゲート電極（１５）が所望の大
きさと間隔で縦横方向に配列されたパターンとなり、前
記四角形の外側にＰ型拡散領域（１３）とＮ＋型拡散領
域（１４）の両方にオーミンクコンタクトする共通ソー
ス電極（１８）が配設される。ゲート電極（１５）はそ
のままでは電気的に独立してしまう為、ゲート電極（１
５〉上の酸化膜（１６）を開孔したコンタクトホール（
２１）を介してソース電極（１８）と平行に延在する共
通ゲート電極（１５）が各ゲート電極（１５）とコンタ
クトすることにより、全てのゲート電極（１５）を電気
的に同電位にする。尚、共通ゲートを極（１７）と共通
ソース電極（１８）とは同層の配線層で形成される為、
両者は図示せぬ外部接続用電極パッドから櫛歯状に形成
され、且つ交互に相対向して延在するようにパターニン
グされる。The P-type diffusion region (13) is formed in a lattice shape as a feature of the present application, and the gate electrode (13) is formed through the gate oxide film (20) so as to cover the surface of the remaining epitaxial layer (12).
5) is provided. The shape of one gate pole (15) is, for example, a rectangular shape, and each gate pole (15) has an epitaxial layer (12).
placed alone and independently on the top. Therefore, the MOS of the present application
The FET has a pattern in which island-shaped gate electrodes (15) are arranged in the vertical and horizontal directions with a desired size and spacing, and an open circuit is formed outside the square to both the P-type diffusion region (13) and the N+-type diffusion region (14). A common source electrode (18) with mink contact is provided. Since the gate electrode (15) is electrically independent as it is, the gate electrode (15)
5> Contact hole (
A common gate electrode (15) extending parallel to the source electrode (18) is in contact with each gate electrode (15) via the electrode 21), thereby making all the gate electrodes (15) electrically at the same potential. . In addition, since the common gate electrode (17) and the common source electrode (18) are formed in the same wiring layer,
Both are formed into a comb-teeth shape from external connection electrode pads (not shown), and are patterned so as to extend alternately facing each other.
ゲート電極（１５）下のチャンネル部（１９）形成にあ
たっては、先ずエピタキシャル層（１２）表面にＰ型拡
散領域（１３）のうちの深い領域を形成する為のＰ型不
純物（ボロン等）を選択的にデポジットした後、エピタ
キシャル層〈１２）表面に膜厚１０００人程度０ゲート
酸化膜（２０）と膜厚５０００乃至８０００人のポリシ
リコン層を生成し、このポリシリコン層をアイランド状
にパターニングすることでゲート電極（１５）を形成し
、ゲートを極（１５）をマスクとしたセルファライン技
術により全面にＰ型不純物（ボロン等）をイオン注入し
、先に導入したＰ型不純物と共にこのＰ型不純物を熱拡
散してＰ型拡散領域（１３）を形成し、今度はゲート電
極（１５）とパターニングしたホトレジスト膜をマスク
としたセルファライン技術によりＮ型不純物（リン等）
をイオン注入してソースとなるＮ＋型拡散領域（１４）
を形成し、その結果Ｐ型拡散領域（１３）とＮ＋型拡散
領域（１４）が規定するゲート電極（１５）下のＰ型拡
散領域（１３）がチャンネル部（１９）となる、そして
、ゲート電極（１５）を覆う様にＣＶＤ酸化膜（１６）
を生成し、ゲート電極（１５〉上とＰ型拡散領域（１３
）上に夫々コンタクトホール（２１）（２２）を形成し
た後全面に電極配線層を形成し、この電極配線層をパタ
ーニングして共通ベース電極（１７）と共通ソース電極
（１８）を形成することにより本願のＭＯＳ Ｆ ＥＴ
を得る。尚、電極配−線層材料としてはアルミニウム（
ＡＩ）、アルミニウム・シリコン（Ａｔ−５ｉ）、タン
グステン（Ｗ＞等が選択される。To form the channel portion (19) under the gate electrode (15), first select a P-type impurity (such as boron) to form a deep region of the P-type diffusion region (13) on the surface of the epitaxial layer (12). After depositing the epitaxial layer (12), a zero gate oxide film (20) with a thickness of about 1000 layers and a polysilicon layer with a thickness of 5000 to 8000 layers are generated on the surface of the epitaxial layer (12), and this polysilicon layer is patterned into an island shape. By this, a gate electrode (15) is formed, and a P-type impurity (such as boron) is ion-implanted over the entire surface using self-line technology using the gate electrode (15) as a mask. The impurity is thermally diffused to form a P-type diffusion region (13), and then an N-type impurity (such as phosphorus) is added using self-line technology using the gate electrode (15) and the patterned photoresist film as a mask.
N+ type diffusion region (14) that becomes a source by ion-implanting
As a result, the P-type diffusion region (13) under the gate electrode (15) defined by the P-type diffusion region (13) and the N+ type diffusion region (14) becomes a channel part (19), and the gate CVD oxide film (16) to cover the electrode (15)
on the gate electrode (15) and on the P-type diffusion region (13
) After forming contact holes (21) and (22) on the respective surfaces, an electrode wiring layer is formed on the entire surface, and this electrode wiring layer is patterned to form a common base electrode (17) and a common source electrode (18). Accordingly, the MOS FET of the present application
get. Note that aluminum (
AI), aluminum silicon (At-5i), tungsten (W>, etc.) are selected.
斯る構成によれば、チャンネル部（１９）がアイランド
状に形成されたゲート電極（１５〉の内側へ形成される
為、四角形状のコーナ一部（２３）のＰＮ接合は内側へ
折れ曲った形状を成し、従って第１図に示す如く、前記
ＰＮ接合からエピタキシャル層（１２）側へ形成される
空乏層（２４）も前記ＰＮ接合の形状に沿ったものとな
る。この様な形状では、エピタキシャル層（１２）から
Ｐ型拡散領域り１３）への電界は集中せず、前記空乏層
（２４）の凹曲面状に沿って分散することになる。その
為、本願のＭＯＳＦＥＴの耐圧は純粋に側辺のチャンネ
ル部（１９）でのバンチスルー又はツェナー降伏電圧で
決まり、コーナ一部（２３）での耐圧劣化は無い。According to this configuration, since the channel portion (19) is formed inside the gate electrode (15) formed in an island shape, the PN junction at a part of the square corner (23) is bent inward. Therefore, as shown in FIG. 1, the depletion layer (24) formed from the PN junction to the epitaxial layer (12) side also follows the shape of the PN junction. The electric field from the epitaxial layer (12) to the P-type diffusion region 13) is not concentrated, but is dispersed along the concave curved shape of the depletion layer (24). Therefore, the breakdown voltage of the MOSFET of the present invention is determined purely by the bunch-through or Zener breakdown voltage at the side channel portions (19), and there is no breakdown voltage deterioration at the corner portion (23).
尚、本実施例はゲート電極（１５）も含めて２層電極構
造を採る為、共通ゲート電極（１７〉下のチャンネル部
（１９）へのソース電流供給はＮ＋型拡散領域（１４）
を介して行なわれる。その為、共通ゲート電極（１７）
の下部はチャンネル部（１９）を除いたＰ型拡散領域（
１３）の全面にＮ１型拡散領域（１４）を設けても良く
、この場合は共通ソース電極（１８）からの電流供給が
よりスムーズに行なわれる。Note that since this embodiment adopts a two-layer electrode structure including the gate electrode (15), the source current is supplied to the channel part (19) under the common gate electrode (17) through the N+ type diffusion region (14).
It is done through. Therefore, the common gate electrode (17)
The lower part of is a P-type diffusion region (excluding the channel part (19)).
The N1 type diffusion region (14) may be provided on the entire surface of the electrode 13), and in this case, the current supply from the common source electrode (18) is performed more smoothly.
第３図及び第４図は夫々本願の第２の実施例を示す平面
図及びＢＢ線断面図である。先の実施例としては共通ソ
ース電極（１８）の取出し方法が異なる。即ち、Ｐ型拡
散領域（１３）の表面にその形状に対応した格子状のソ
ース電極（３０）を配設し、再度ＳｉＮ 、ポリイミド
系絶縁膜等の層間絶縁膜（３１）で覆った後、櫛歯状の
共通ゲート電極（１７）と共通ソース電極（１８）を配
設したものである。ソース電極（３０）材料としては、
タングステン（Ｗ）等の高融点金属やアルミニウム・シ
リコン（Ａｌ−５ｉ）が選択される。本実施例によれば
、Ｐ型拡散領域（１３）の全部に格子状のソース電極（
３０）が延在するので、共通ソース電極（１８）からチ
ャンネル部（１９）への電流供給がより一層スムーズに
且つ平均的に行なわれる。また各チャンネル領域までの
チャンネル抵抗が低減し、寄生バイポーラトランジスタ
動作を防ぎ破壊耐畳の増大が図れる。3 and 4 are a plan view and a cross-sectional view taken along the line BB, respectively, showing a second embodiment of the present application. The method for taking out the common source electrode (18) is different from the previous embodiment. That is, a lattice-shaped source electrode (30) corresponding to the shape of the P-type diffusion region (13) is provided on the surface of the P-type diffusion region (13), and then covered again with an interlayer insulating film (31) such as SiN or polyimide-based insulating film. A comb-shaped common gate electrode (17) and a common source electrode (18) are provided. As the source electrode (30) material,
A high melting point metal such as tungsten (W) or aluminum silicon (Al-5i) is selected. According to this embodiment, a lattice-shaped source electrode (
30) is extended, current is supplied from the common source electrode (18) to the channel portion (19) more smoothly and evenly. Furthermore, the channel resistance up to each channel region is reduced, preventing parasitic bipolar transistor operation and increasing breakdown resistance.
（ト）発明の詳細
な説明した如く、本発明によれば電界集中による耐圧劣
化を防止したので、耐圧を向上した縦型ＭＯ３ＦＥＴが
得られる利点を有する。また、耐圧劣化が無いので、チ
ャンネル部（１９）の拡散深さを浅くしてパターンの微
細化が図れる利点を有する。さらに微細化することでＭ
ＯＳＦＥＴのチャンネル幅ＧＷを増大し、オン抵抗Ｒ□
（ｏｎ）を低減できる利点をも有する。また低Ｖａｓ（
ｏｆｆ）化、高ｇｍ化した場合にもコーナ一部でのショ
ートチャンネル効果等を抑えることができる。(g) As described in detail, the present invention prevents breakdown voltage deterioration due to electric field concentration, and therefore has the advantage of providing a vertical MO3FET with improved breakdown voltage. Further, since there is no breakdown voltage deterioration, there is an advantage that the diffusion depth of the channel portion (19) can be made shallow and the pattern can be made finer. With further miniaturization, M
Increase the channel width GW of OSFET and reduce the on-resistance R□
It also has the advantage of being able to reduce (on). Also, low Vas (
OFF) and high GM, it is possible to suppress the short channel effect in a part of the corner.
第１図及び第２図は夫々本発明の一実施例を説明する為
の平面図及びＡＡ線断面図、第３図及び第４図は夫々本
発明の第２の実施例を説明する為の平面図及びＢＢ線断
面図、第５図及び第６図は従来例を説明する為の平面図
及び断面図である。
（１１）はＮ＋型半導体基板、 （１３）はＰ型拡散領
域、 （１４）はＮ＋型拡散領域、 （１５）はゲート
電極、 （１７）は共通ゲート電極、 （１８）は共通
ソース電極、 （１９）はチャンネル部、（２３）は四
角形状のコーナ一部、（２４）は空乏層である。
第１図
第２図
第３図1 and 2 are a plan view and a sectional view taken along line AA, respectively, for explaining one embodiment of the present invention, and FIGS. 3 and 4 are diagrams, respectively, for explaining a second embodiment of the present invention. A plan view and a BB line sectional view, and FIGS. 5 and 6 are a plan view and a sectional view for explaining a conventional example. (11) is an N+ type semiconductor substrate, (13) is a P type diffusion region, (14) is an N+ type diffusion region, (15) is a gate electrode, (17) is a common gate electrode, (18) is a common source electrode, (19) is a channel portion, (23) is a part of a rectangular corner, and (24) is a depletion layer. Figure 1 Figure 2 Figure 3
Claims (4)
主表面の一部に第２導電型の拡散領域が形成され、この
拡散領域の表面の一部に第１導電型のソース領域が形成
され、前記第２導電型拡散領域周辺部上に絶縁膜を介し
てゲート電極が形成され、前記ゲート電極への電圧印加
によってソース・ドレイン間電流を制御する縦型ＭＯＳ
ＦＥＴにおいて、前記第２導電型拡散領域を格子状に形
成し、前記ゲート電極は夫々が独立するようにアイラン
ド状に縦横に配列したことを特徴とする縦型ＭＯＳＦＥ
Ｔ。(1) A first conductivity type semiconductor substrate is used as a drain, a second conductivity type diffusion region is formed in a part of one main surface thereof, and a first conductivity type source region is formed in a part of the surface of this diffusion region. A vertical MOS, in which a gate electrode is formed on the periphery of the second conductivity type diffusion region via an insulating film, and a source-drain current is controlled by applying a voltage to the gate electrode.
A vertical MOSFE in an FET, characterized in that the second conductivity type diffusion regions are formed in a lattice shape, and the gate electrodes are arranged vertically and horizontally in an island shape so that each gate electrode is independent from the other.
T.
一主表面に格子状に形成した第２導電型の拡散領域と、
この拡散領域の表面に選択的に形成した第１導電型のソ
ース領域と、前記第２導電型拡散領域で囲まれた領域上
に絶縁膜を介してアイランド状に配設したゲート電極と
、縦横に配列された前記ゲート電極の夫々を共通接続す
るストライプ状の共通ゲート電極と、この共通ゲート電
極と平行に延在し前記第２導電型拡散領域と前記ソース
領域の両方にオーミックコンタクトするソース電極とを
具備することを特徴とする縦型ＭＯＳＦＥＴ。(2) a first conductivity type semiconductor substrate serving as a drain; a second conductivity type diffusion region formed in a lattice shape on one main surface thereof;
A source region of a first conductivity type selectively formed on the surface of the diffusion region, and a gate electrode arranged in an island shape on a region surrounded by the diffusion region of the second conductivity type with an insulating film interposed therebetween. a striped common gate electrode that commonly connects each of the gate electrodes arranged in a stripe, and a source electrode that extends parallel to the common gate electrode and makes ohmic contact with both the second conductivity type diffusion region and the source region. A vertical MOSFET characterized by comprising:
一主表面に格子状に形成した第２導電型の拡散領域と、
この拡散領域の表面に選択的に形成した第１導電型のソ
ース領域と、前記第２導電型拡散領域で囲まれた領域上
に絶縁膜を介してアイランド状に配設したゲート電極と
、前記第２導電型拡散領域と前記ソース領域の両方にオ
ーミックコンタクトし前記第２導電型拡散領域の表面に
沿って格子状に配設した下層のソース電極と、縦横に配
列された前記ゲート電極の夫々を共通接続するストライ
プ状の共通ゲート電極と、この共通ゲート電極と平行に
延在し前記下層のソース電極とコンタクトするソース電
極とを具備することを特徴とする縦型ＭＯＳＦＥＴ。(3) a semiconductor substrate of a first conductivity type serving as a drain; a diffusion region of a second conductivity type formed in a lattice shape on one main surface thereof;
a source region of a first conductivity type selectively formed on the surface of the diffusion region; a gate electrode disposed in an island shape on a region surrounded by the diffusion region of the second conductivity type with an insulating film interposed therebetween; a lower source electrode that is in ohmic contact with both the second conductivity type diffusion region and the source region and arranged in a lattice shape along the surface of the second conductivity type diffusion region; and the gate electrodes that are arranged vertically and horizontally, respectively. 1. A vertical MOSFET comprising: a striped common gate electrode commonly connected to the common gate electrode; and a source electrode extending parallel to the common gate electrode and making contact with the source electrode in the lower layer.
状を有し、且つ交互に延在することを特徴とする請求項
第２項又は第３項に記載の縦型ＭＯＳＦＥＴ。(4) The vertical MOSFET according to claim 2 or 3, wherein the common gate electrode and the source electrode have a comb-like shape and extend alternately.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63066328A JPH07120798B2 (en) | 1988-03-18 | 1988-03-18 | Vertical MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63066328A JPH07120798B2 (en) | 1988-03-18 | 1988-03-18 | Vertical MOSFET |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01238174A true JPH01238174A (en) | 1989-09-22 |
| JPH07120798B2 JPH07120798B2 (en) | 1995-12-20 |
Family
ID=13312665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63066328A Expired - Lifetime JPH07120798B2 (en) | 1988-03-18 | 1988-03-18 | Vertical MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07120798B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08255911A (en) * | 1994-12-30 | 1996-10-01 | Siliconix Inc | Longitudinal power mosfet with thick metallic layer for reducing distributed resistance, and its manufacture |
| JPH08264785A (en) * | 1994-12-30 | 1996-10-11 | Siliconix Inc | Integrated circuit die and its manufacture |
| JP2016534581A (en) * | 2013-09-20 | 2016-11-04 | モノリス セミコンダクター インコーポレイテッド | High voltage MOSFET device and method of manufacturing the device |
| JP2017163122A (en) * | 2016-03-11 | 2017-09-14 | 株式会社東芝 | Semiconductor device |
| WO2018003064A1 (en) * | 2016-06-30 | 2018-01-04 | 株式会社日立製作所 | Semiconductor device |
| US10692999B2 (en) | 2013-09-20 | 2020-06-23 | Monolith Semiconductor Inc. | High voltage MOSFET devices and methods of making the devices |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107636835B (en) * | 2015-12-11 | 2021-03-19 | 富士电机株式会社 | Semiconductor device and method of manufacturing the same |
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| JPS57153468A (en) * | 1981-03-18 | 1982-09-22 | Toshiba Corp | Insulated gate type field effect transistor |
| JPS5889864A (en) * | 1981-11-24 | 1983-05-28 | Hitachi Ltd | Insulated gate type semiconductor device |
| JPS59149058A (en) * | 1983-02-15 | 1984-08-25 | Matsushita Electric Works Ltd | Metal oxide semiconductor type transistor |
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1988
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57153468A (en) * | 1981-03-18 | 1982-09-22 | Toshiba Corp | Insulated gate type field effect transistor |
| JPS5889864A (en) * | 1981-11-24 | 1983-05-28 | Hitachi Ltd | Insulated gate type semiconductor device |
| JPS59149058A (en) * | 1983-02-15 | 1984-08-25 | Matsushita Electric Works Ltd | Metal oxide semiconductor type transistor |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08255911A (en) * | 1994-12-30 | 1996-10-01 | Siliconix Inc | Longitudinal power mosfet with thick metallic layer for reducing distributed resistance, and its manufacture |
| JPH08264785A (en) * | 1994-12-30 | 1996-10-11 | Siliconix Inc | Integrated circuit die and its manufacture |
| JP2008124516A (en) * | 1994-12-30 | 2008-05-29 | Siliconix Inc | Integrated circuit die and manufacturing method therefor |
| JP2016534581A (en) * | 2013-09-20 | 2016-11-04 | モノリス セミコンダクター インコーポレイテッド | High voltage MOSFET device and method of manufacturing the device |
| US10361302B2 (en) * | 2013-09-20 | 2019-07-23 | Monolith Semiconductor Inc. | High voltage MOSFET devices and methods of making the devices |
| US10692999B2 (en) | 2013-09-20 | 2020-06-23 | Monolith Semiconductor Inc. | High voltage MOSFET devices and methods of making the devices |
| JP2021108380A (en) * | 2013-09-20 | 2021-07-29 | モノリス セミコンダクター インコーポレイテッド | High-voltage mosfet device and manufacturing method thereof |
| JP2017163122A (en) * | 2016-03-11 | 2017-09-14 | 株式会社東芝 | Semiconductor device |
| US10236377B2 (en) | 2016-03-11 | 2019-03-19 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US10763359B2 (en) | 2016-03-11 | 2020-09-01 | Kabushiki Kaisha Toshiba | Semiconductor device |
| WO2018003064A1 (en) * | 2016-06-30 | 2018-01-04 | 株式会社日立製作所 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07120798B2 (en) | 1995-12-20 |
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