JPH01191965A - Serial bus access system - Google Patents

Abstract

PURPOSE:To omit the transmission of address to serial buses against the accesses to the continuous address by providing the address storing registers at the transmission and reception sides and storing the addresses added with the number of transfer bytes into both registers. CONSTITUTION:A transmission register 4 holds the address following the final one for transfer of data in response to an input/output device. While a reception register 8 holds the received next address. When data are transferred, a comparator 5 compares the head address with the corresponding contents held by the register 4. Then the register 4 is updated. In case no coincidence is obtained from said comparison, the register 8 is updated based on the contents held by the updated register 4. While the register 8 is used with no update if the coincidence is obtained from said comparison.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a serial bus access method.

[Conventional technology]

Conventional serial path access methods send control commands and addresses to the serial bus each time an access is made.

[The gap that the invention attempts to solve]

In the conventional serial bus access method described above, an address is sent every time an access is made, so as the address space expands, the access time increases unless the transfer speed of the serial bus is increased.

In contrast, the present invention has a difference in that depending on the address output by the processor, access can be made without sending the address to the serial bus.

[Means for solving problems]

The serial path access method of the present invention has a transmitting side register for holding the next address of the final address of data transfer corresponding to the input/output device, a receiving side register for holding the received next address, and a receiving side register for holding the next address after the final address of data transfer. When attempting to do so, K is provided with a comparison circuit that compares the starting address with the contents held in the corresponding transmitter side register, updates the transmitter side register after this comparison, and if the comparison result does not match, then The present invention is characterized in that the receiving register is updated and used with the contents held in the updated transmitting register, and if the result of the comparison is a match, the receiving register is used without being updated.

FIG. 1 is a block diagram showing one embodiment of the present invention, in which a processor 1, an adder circuit 2, a transmission control circuit 3, a register 4
and a transmitter side consisting of a comparison circuit 5, a reception control circuit 6,
A receiving side consisting of a switching circuit 7, a register 8 and an adder circuit 9 is connected via a serial bus 10.

When the processor 1 attempts to transfer data via the serial bus 10, K outputs the start address t□ and the transfer pi)Utt. The adder circuit 2 receives the start address t
1 and the number of transferred bytes t! This addition result t is written into the register 4 using the write control signal Δt from the transmission control circuit 3.

It is easy to understand that the addition result 1s is the address next to the final address at which the above-described data transfer was performed, that is, the first address in the case of continuous data transfer.

The comparison circuit 5 compares 81+ held in the register 4 with the start address t1 and outputs a result t. When the start address t1 and the number of transfer bytes 1 are input, the transmission control circuit 3 performs different control depending on the contents of the comparison result t6.

That is, if the content of the comparison result t6 indicates that the content held in the register 4 and the start address t match, the transmission control circuit 3 includes the number of transferred bytes and an address generation request. A command is generated and sent to the serial bus 10, and a write control signal 1. The addition result t3 is written into the register 4.

Furthermore, if the contents of the comparison result t indicate that the contents held in the register 4 and the start address t1 do not match, the transmission control circuit 3 sends a command containing the number of transfer bytes t and an address reception request. , converts the start address t1 into serial, and sequentially converts the serial bus IOK.
Send. In this case as well, the addition result t is obtained from the write control signal t and IIC.

is written to register 4.

When the reception control circuit 6 receives the above-mentioned 2!11 type commands and addresses via the serial bus 10,
It analyzes commands and performs the following controls.

That is, when the command is an address generation request, the switching circuit 7 selects the contents t, held in the register 8.

It generates a switching signal t- (logic @0'') with contents such as to accept or enter , and writes the addition result t1! in the adder circuit 9 to the register 8 using the write control signal t0.

Further, if the command is an address reception request, the first address 1 . is converted into parallel and outputted as a received address t, and the switching circuit 7 generates a switching signal t (logic @1") with contents to accept or accept this received address t, and also writes. The addition result 1. is written into the register 8 by the control signal t11.

The switching circuit 7 outputs the contents t1゜ held in the register 8 or the received address t to the internal address bus ``14'' when the switching signals t and o are @0'' or @1'', and the adder circuit 9 adds the address on the internal address bus t14 and the number of transfer bytes tts received by the reception control circuit 6, and outputs the addition result 211.

Next, the operation of this embodiment will be explained.

At the beginning of data transfer, the comparison result t6 will indicate a mismatch. In this case, the addition result t1
is written into the register 4, and an address reception request is transmitted to the reception control circuit 6.

Therefore, since the switching signal RI becomes logic 11'', the switching circuit 7 receives the reception address tm (starting address t).

) is output to the internal address bus t,4, so
The adder circuit 9 receives the received address t and the number of transferred bytes t*SC.
Add the number of transferred bytes t, which is equal to K).

As a result, the addition result t is the addition result Ls on the sending side
K, and the address of this same value is written into the register 8. Incidentally, on the receiving side, data transfer is performed using the address on the internal address bus /-14 as the starting address.

As described above, when the data transfer of the number of transfer bytes t set by the processor 1 is completed, the processor 1 newly transfers the start address t1 and the number of transfer bytes t! , and then try to perform the next data transfer. In this case, the desired data transfer is often performed from an address consecutive from the previous data transfer.

In such a case, the new starting address t1 is the same value as that held in register 4 and then register t. Register 4 is used to detect data transfers to such consecutive addresses, and register 8 is
To eliminate the need to send the start address of a new data transfer via a serial bus IO.

That is, the comparator circuit 5 compares the content held in the register 4, that is, the address next to the final address in the previous data transfer, with the new start address t, and obtains the comparison result t.
If it indicates -, the transmission control circuit 3 only sends the number of transfer bytes 11 and a command, but does not send the new start address t1. In this case, the starting address used for new data transfer on the receiving side is given from the register 8 to the internal address t by the switching circuit 7.

Note that when a new data transfer is performed from an address that is not consecutive from the previous monitor transfer, the same operation as described at the beginning of the operation description is performed.

In the embodiment described above, in order to simplify the explanation, only one input/output device is assumed, but as is usually the case, there are N (N≧2) input/output devices. In the case of data transfer, eight registers similar to register 4 may be provided for transmission filIK, and the registers may be selectively used according to instructions from processor 1.

〔Effect of the invention〕

As explained above, the present invention provides registers for storing addresses on the transmitting side and the receiving side, and by storing the address including the number of transferred bytes together, the serial bus is used for continuous address access. Since it is possible to omit sending addresses, access time can be shortened, and bus usage efficiency can be improved in multiprocessor systems where serial buses are often used.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example #1 of the present invention. 1... Processor, 2.9-... Addition circuit, 3... Transmission control circuit, 4.8...
Register, 5... Comparison circuit, 6... Reception control circuit, ? ------・Switching circuit, 10...
・Serial bus, t14 ”” ”・Internal address no. Agent: Susumu Uchihara, patent attorney

Claims (1)

[Scope of Claims] A transmitting side register for holding the next address of the final address of data transfer corresponding to the input/output device, and a receiving side register for holding the received next address; When doing so, a comparison circuit is provided that compares the start address and the contents held in the corresponding transmitting side register, and after the comparison, the transmitting side register is updated, and if the result of the comparison is a mismatch, the updated contents are The serial device is characterized in that the receiving side register is updated and used with the content held in the sending side register, and when the result of the comparison is a match, the receiving side register is used without being updated. Bus access method.