JPH01183851A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To lower the resistance of a source and a drain and reduce p-n junction leakage in a MOS FET utilizing silicide structure by forming silicon layers on both sides of a gate electrode, applying a metal onto the silicon layers, metal silicide is formed on the silicon layer and removing the metal not formed into silicide. CONSTITUTION:A gate electrode 14 coated with an insulating film 21 is shaped onto a semiconductor substrate 11, silicon layers 22 are formed on both sides of the gate electrode 14, and an impurity is diffused to the silicon layers 22 to shape a source and a drain. A metal 23 is applied onto the silicon layers 22, the silicon layers 22 are formed into silicide through heat treatment, and the metal 23 not formed into silicide is gotten rid of. Consequently, since polysilicon is stacked previously in source and drain regions and the stacked sections and the metal 23 are reacted, a reaction with the metal 23 of substrate silicon 11 is reduced, and the substrate 11 is shaped in silicide structure having sections formed into silicide on the substrate 11 under the state in which there is no flaw. Accordingly, the resistance of the source and the drain is lowered and junction leakage is reduced in a MOS FET.

Description

[Detailed Description of the Invention] (Summary) A method for manufacturing a semiconductor device, in particular, forming source and drain regions by growing a single crystal or polycrystalline silicon (polysilicon) film in a self-aligned manner with respect to a gate electrode; MOS that utilizes a salicide structure, which has been recently developed, is a method of growing metal and turning a single crystal or polysilicon film into silicide through heat treatment.
In FET, low resistance of source and drain and p-n
The purpose of the present invention is to provide a method for manufacturing a semiconductor device that realizes reduction of junction leakage. forming a silicon layer in a self-aligned manner, and then diffusing impurities of a conductivity type opposite to that of the substrate into the silicon layer to form a source and a drain;
and a method for manufacturing a semiconductor device, comprising the steps of depositing a metal on a silicon layer, siliciding the silicon layer by heat treatment, and removing metal that does not become silicide.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, in particular, forming source and drain regions in a self-aligned manner with respect to a gate electrode by growing a single crystal or polycrystalline silicon (polysilicon) film.
The present invention further relates to a method of growing a metal and siliciding a single crystal or polysilicon film by heat treatment.

[Conventional technology]

Drain with impurity diffused at low concentration (LightlyD
For example, an n-MOS transistor having a structure (open drain LDD) is known, and an example thereof is shown in a cross-sectional view in FIG. 3 is a gate oxide film, 4 is a gate electrode, 15 is 5i02PiJ, 16 is n-
Layer 17 is an n+ layer. The n-layer 16 contains phosphorus (P),
Further, the n+ layer 17 is formed by diffusing arsenic (As).

Such a structure consists of a single drain (sin drain) shown in FIG.
Since the pn junction has a gentle shape compared to the gle drain structure, the structure is strong against real carriers.

[Problem that the invention seeks to solve]

In order to improve the performance of MOS FET, source.

Lateral diffusion of the drain diffusion layer must be prevented and short channel effects must be avoided. At the same time, it was necessary to reduce the resistance of the source and drain layers, and for this purpose, the structure shown in FIG. 4 was proposed. In addition, in Figure 4, 1
8 is a silicide layer. However, in this structure p−n
The junction may leak, or the contact between the silicide film and the n- layer 16 may not be sufficient.

Therefore, as shown in FIG. 5, the silicide layer 18 and n
A structure in which an n+ layer 19 is interposed between the n+ layer 16 and the n+ layer 16 has been proposed, but as devices become smaller, the resistance of the n+ layer I9 deteriorates the performance of the device. The example shown in FIG. 5 has a structure in which the n1 layer 19 is stacked on the n- layer 16 formed on the substrate.
Therefore, considering the characteristics of the device, the n+ layer is required to be as thin as possible. However, if the n+ layer 19 is made thinner, there is a problem that the substrate is eroded during silicidation.

Furthermore, the structures shown in Figures 6 and 7 have also been proposed, but since the substrate silicon reacts with the metal and becomes silicided, the substrate silicon is eroded by the metal and leakage from the p-n junction becomes a problem. Become.

On the other hand, recently, self-aligned
5ili-cade) structure is attracting attention. Referring to FIG. 8, the upper surface of the gate electrode 14 is also silicided, which is effective in reducing the resistance of the gate electrode, and when the illustrated MOS is used in a DRAM, the gate electrode is used as a word line. Therefore, a low resistance is advantageous for increasing the speed of DRAM. However, the eighth
Even in the salicide structure shown in the figure, leakage occurs at the p-n junction and the contact between the silicide film and the n-jW16 is insufficient, which is basically the same as the structure shown in Fig. 4 mentioned above. There is no turning back.

Therefore, the present invention provides a source in a MOS FET that utilizes a salicide structure that has been recently developed.

It is an object of the present invention to provide a method of manufacturing a semiconductor device that achieves low resistance of the drain and reduction of pn junction leakage.

[Means for solving problems]

The above problem is solved by forming a gate electrode on a semiconductor substrate, at least the sidewalls of which are covered with an insulating film, and then forming a silicon layer on both sides of the gate electrode in a self-aligned manner, and then forming a silicon layer on the silicon layer with the substrate. It is characterized by comprising the steps of forming a source and drain by diffusing impurities of opposite conductivity type, and depositing metal on a silicon layer, siliciding the silicon layer by heat treatment, and removing metal that does not become silicide. The problem is solved by a method of manufacturing a semiconductor device.

[Effect]

In the present invention, single crystal or polysilicon is grown in a self-aligned manner as the source and drain regions of a MOS FET, and the single crystal or polysilicon is doped by solid-phase diffusion, ion implantation, etc., and the entire surface is covered with metal. wear. After that, heat treatment is performed to silicide all the single crystal or polysilicon, and then the metal regions that are not silicided are removed.

The reason for the above is that if there is a large reaction between the metal and the substrate silicon, junction leakage will occur, so please prepare the source in advance.

Single crystal or polysilicon is piled up in the drain region, and that part reacts with the metal to reduce the reaction of the substrate silicon with the metal. The high concentration layer under the silicide may be formed after silicidation, and it is also possible to selectively grow metal or silicide only on the stacked single crystals or polysilicon.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to an illustrated embodiment.

FIG. 1 shows a cross-sectional view of an embodiment of the invention.

Refer to FIG. 1(a): A 5iOz film 12 for element isolation is formed on a semiconductor (silicon) substrate 11 using a normal MOS FET manufacturing process.
A gate oxide film 13 and a gate electrode 14 are formed, an S+02 film 15 serving as a cap is formed on the gate electrode, and an S+02 film 15 is also formed on the side walls.
An i02 film 21 is formed, and the n- layer 16 is formed by ion implantation.
form.

See FIG. 1(b): Next, the silicon layer 22 (single crystal silicon or polysilicon layer) is self-aligned to the gate electrode 14 with a thickness of 500 to 1
Deposit EtlO to a thickness of 50,000 cm, then dose EtlO"' cm, implant energy 50
Ion implantation is performed under KeV conditions to make the silicon layer 22 n+ type.

See FIG. 1(C): High melting point metal layer 23 (titanium (Ti), tungsten (W), molybdenum (Mo), etc.)
Grow into the thickness of a person. The relationship between the thickness of the metal layer 23 and the silicon layer 22 is such that the silicon layer 22 is completely reacted (eroded by the metal) by silicidation, which will be described later.
In order to prevent this, the thickness of the metal layer is grown to be smaller than the thickness of the silicon layer (for example, in a ratio of 4:6).

FIG. 1 (reference to dll) RTA is performed at 00° C. in an N2 atmosphere to form a silicide film 24.

An n+ layer 25 is formed on the surface of the silicon substrate by the ion implantation described with reference to FIGS.
is formed.

See Figure 1(e): For example, NJcO)l/H,! By etching using 02, only the metal layer that is not silicided is removed, leaving the silicide film 24.

Instead of the above method, the structure shown in FIG. 1(e) can be obtained by selectively growing metal particles or silicide and applying heat treatment in the process explained with reference to FIG. 1(b). However, the process for making the silicon layer 22 n+ type may be performed after forming the structure shown in FIG. 1(e).

Note that, prior to depositing the silicon layer 22, the gate electrode 1
If the SiO+ film on 4 is removed, a semiconductor device having the structure shown in FIG. 1(f) can be easily manufactured by the same process as described above.

In this structure, since a part of the gate electrode is also silicided, there is an effect that the resistance of the gate electrode can be lowered.

〔Effect of the invention〕

Does the salicide structure described with reference to FIG. 8 have low resistance in a self-aligned manner? It is attracting attention because it is effective in obtaining IOS FETs, but if a high-melting point metal is directly applied to a silicon substrate to form a silicide, the substrate will react (erode), which is inconvenient for miniaturization of elements, and salicide is used. The structure has not yet been put into practical use. In order to utilize the salicide structure, in the present invention, materials to be silicided are piled up, and a silicon layer that reacts with metal is deposited as a breadth layer on parts other than the substrate that are involved in the operation of the device, and then almost completely bonded with the silicon layer. Attach an amount of metal that reacts to the
By reacting, the substrate is made into a salicide structure with a silicided portion on the substrate without any scratches.

By doing this, the advantages of the salicide structure can be reduced to LDD.
It can now be used for purposes other than structures, and the problems caused by silicide have been solved, making the salicide structure highly reproducible.
An element with uniform low resistance and good characteristics can be produced without encroaching on the source and drain, and a memory capable of high-speed operation when the gate electrode is used as a word line can be provided. As described above, the present invention has the effect of lowering the resistance of the source 3 and drain and reducing junction leakage in a MOS PET.

[Brief explanation of the drawing]

Figures 1 (al to fl are cross-sectional views of the embodiment of the present invention, Figure 2 is a cross-sectional view of a normal LDD structure, Figure 3 is a cross-sectional view of a single drain structure, and Figures 4 to 7 are cross-sectional views of a conventional example). 8 are cross-sectional views of the salicide structure. In the figures, 11 is a silicon substrate, 12 is a SiO2 film, 13 is a gate oxide film, 14 is a gate electrode, 15 is a SiO2 film, 16 is an n-layer, 17 is the n+ layer, 18 is the silicide film, 19 is the n1 layer, 20 is the current path, 21 is the SiO2 film, 22 is the silicon layer, 23 is the metal layer, 24 is the silicide film, and 25 is the n+ layer. 〉Kore, poverty 21 5iOzl (N Y Mi C Sun Moon 1 in 31 Hiiku 11 Ka' Tsukasa Koni 1st figure 16 n-, 9 17n Yano change 21 5iOz order Buli ≦ 9ft 9 Sun Moon 11 ``Mihiig 1IiilH Ko Figure 1 Figure 2 16n1 Figure 3
1"116 6th flash 14 keli coins r~co, 80 figure 7

Claims (2)

[Claims] (1) After forming a gate electrode (14) on a semiconductor substrate (11), at least the sidewalls of which are covered with an insulating film (21), a silicon layer (22) is formed on both sides of at least the gate electrode (14) in a self-aligned manner. ), and then diffusing impurities of a conductivity type opposite to that of the substrate into the silicon layer (22) to form a source and a drain, and depositing a metal (23) on the silicon layer (22), silicide the silicon layer (22) by heat treatment;
A method for manufacturing a semiconductor device, comprising a step of removing metal that does not become silicide. (2) The method according to claim 1, wherein metal or silicide is selectively grown on the silicon layer (22).