JPH01182890A - Recording and reproducing device for automatic playing - Google Patents

Abstract

PURPOSE:To attain a recording at real time by setting an operating mode to a record reserving mode, which maintains a reproducing operation condition, at first when a running record mode is selected and switch-setting the operating mode to a recording mode when key-on data are generated. CONSTITUTION:In correspondence to the operation of a running record mode selecting means 3, an operating mode control means 4 sets a playing data recording means 2 to the record reserving mode which maintains the reproducing condition. When the key-on data to show the generation of a first tone are generated by the playing start of music in this reproducing condition, the operating mode control means 4 switches and sets the operating mode of the playing data recording means 2 to the recording mode in a condition to succeed the timing of playing and a playing data storing position from the reproducing condition. Then, the operation is continuously moved from the reproducing condition to a recording condition. Thus, the music can be smoothly edited at real time.

Description

[Detailed description of the invention] The invention will be explained in the following order.

Industrial Application Fields Prior Art Problems to be Solved by the Invention Means for Solving Problems Actions and Effects Embodiments Explanation of the structure of the recorder in FIG. 2 Explanation of the structure of the electronic musical instrument in FIG. 2 Description of the operation of the embodiments (1) Explanation of the operation of the electronic musical instrument shown in Fig. 2 (2) Explanation of the operation of the recorder shown in Fig. 2 2-1. Main processing (Figure 5) 2-2. Record switch processing (Figure 6) 2-3. Start/Bose switch processing (Figure 7) 2-4. Stop switch processing (Fig. 8) 2-5.4 Return switch processing (Fig. 349) 2-6. Fast-forward switch processing (Figure 11) 2-7. Input data processing (Figure 12) 2-8. Tempo interwoven processing (Figure 13) 2-9.
Automatic Performance Data Reading Process (FIG. 14) Modification of Embodiment [Field of Application in Industry A] The present invention relates to an automatic performance recording device for recording performance data for controlling the generation of musical tones in an electronic musical instrument, etc.
In particular, the present invention relates to an automatic performance recording device that is capable of starting a performance data recording operation in synchronization with performance data that has already been recorded.

[Prior Art] Conventionally, an automatic performance device for an electronic musical instrument has a performance data memory, and stores key data representing depressed keys and key event timing data representing accepted key depressions and the time of AM based on keyboard performance. It is known to create and record a musical tone, and when playing back, read key data according to a predetermined tempo and this timing data to reproduce the original musical tone (see Japanese Patent Laid-Open No. 58-211191).

[Problems to be Solved by the Invention] By the way, when such an automatic performance device attempts to modify or add to previously recorded performance data, it generally requires re-recording the performance data from the beginning or reproducing the performance data. to find the beginning of the position section that you want to modify or add, and
Then I turned it into recording mode and recorded the performance data, but
This had the disadvantage that it was difficult to get the timing right and it was also difficult to get everyone's heads together.

In view of the problems with the conventional type, an object of the present invention is to provide an automatic performance recording/playback device that records performance data for controlling the generation of musical tones as the music progresses in real time as the music progresses. An object of the present invention is to provide an automatic performance recording/playback device capable of modifying any section of performance data.

[Means for Solving the Problems] In order to solve the above problems, the automatic performance recording and reproducing apparatus of the present invention uses performance data for controlling the generation of musical tones according to the progress of the music, as shown in FIG. a performance data memory means 1 for storing performance data; a performance data recording means 2 for recording performance data sequentially input as the music progresses in the performance data memory means 1; a running record mode selection means 3; When the running record mode is selected by the mode selection means 3, the operation mode of the means 2 is first set to the recording reservation mode in which the playback operation state is maintained, and then the key-on data indicating the generation of the first musical tone is set. The present invention is characterized in that it is equipped with an operation mode control means 4 that continuously switches to the recording mode without changing the address in the reproduction operation state when this occurs.

[Function] In the present invention configured as described above, when attempting to modify or add to performance data that has already been recorded, the music performer or the like first selects the running record mode selection means 3, for example, by switching the running After selecting the record mode, start playing at or just before the beginning of the section you want to correct or add while listening to the automatic performance sound. Then, in the automatic performance recording and reproducing apparatus of the present invention, in response to the operation of the running record mode selection means 3, the operation mode control means 4 sets the performance data recording means 2 to the recording reservation mode while maintaining the reproduction state. In this playback state, when key-on data indicating the generation of the first musical tone is generated due to the start of playing the music, the operation mode control means 4 sets the performance timing and performance data storage location (address) to continue playing from the playback state. The operation mode of the data recording means 2 is switched to recording mode. As a result, the automatic performance recording and reproducing apparatus of the present invention continuously shifts from the reproducing state to the recording state.

[Effects] As can be understood from the above description of the operation, according to the present invention, recording can be restarted by turning on the key at any timing during play. That is,
You can overdub (overwrite) at any timing, so even if you make a mistake in recording some performance data manually, you can edit that part extremely smoothly in real time without any timing shift. can.

[Embodiment] The present invention will be described in detail below with reference to the drawings. FIG. 2 shows a block diagram of an automatic performance system using an automatic performance recording and reproducing apparatus according to an embodiment of the present invention. This automatic performance recording and reproducing device 10 is an MID
cal Instrument DigitalInt
It is a device called a MIDI ID-da that complies with the MIDI standard, and is capable of transmitting and receiving performance data with other devices that comply with the MIDI standard. Here, an automatic performance system is created by connecting an electronic musical instrument 60 that complies with the MIDI standard, which is equipped with both a keyboard as a human-powered device and a sound source (musical tone forming circuit) as an output device, to the MIDIID-da 10. It consists of

(Explanation of the configuration of the recorder shown in FIG. 2) The MIDI ID-dar 10 shown in FIG. 2 is configured so that its entire operation is controlled using a microcomputer 12. The microcomputer 12 consists of a program memory 16, a CPU 18, and a working memory 20, each connected to a bus 14. This bus 14 has
Further, an operator switch circuit 22, a display control circuit 24,
Buffer circuit 26, tempo oscillator 28, timer oscillator 3
0, various registers and buffers 32, and performance data memory 34 are connected.

The program memory 16 is composed of a ROM, and is shown in FIGS.
A main program, timer interwoven programs, tempo interwoven programs, and subprograms thereof are stored, which correspond to the flowchart shown in FIG. 14.

The CPU 18 starts executing the main program when the power switch 46 (see FIG. 3) is turned on, and repeatedly executes the program until the power switch 46 is turned on. When TMPINT and TIMEIRT) arrive, the execution of the main program is interrupted and the tempo and timer-interrupted program is executed.

The working memory 20 is composed of RAM, and the CPU 1
8 temporarily stores various data generated when executing the program. The following flags, registers, etc. are set in the working memory 20. In addition, in the following, registers etc. and their contents (
data) shall be displayed with the same label.

Recording flag REC: This flag indicates the operating state of the recorder 10. 1" indicates that performance data is being written to the performance data memory 34 (recording mode), and 0" indicates that the recording is in progress. Indicates that it is not a mode.

Record Bose flag RECPSE...Recorder 10
This is a flag that indicates the operating state of the record synchronization start state (recording standby mode) at "IN".In this state, the key is turned on (K
ON) signal is generated, the above operating state changes to the record state (
recording mode).

Playback flag FLY: This flag indicates the operating state of the recorder 10. When set to "1", it indicates that automatic performance data is being read from the performance data memory 34 (playback mode), and when set to "0". indicates that the mode is not the playback mode.

Play pause flag PLYPSE: A flag representing the operating state of the recorder 10, and when set to "1", it indicates the play synchronization start state (playback standby mode).

If a key-on (KON) signal is generated in this state, the operating state becomes a play state (reproduction mode).

Running record flag RUNREC: This flag indicates the operating state of the recorder 10, and ``1'' indicates the running record mode (playback idle recording standby mode).This mode allows recording to be performed while playing performance data. In this mode, the recorder 10 changes from the play state to the record state when a key-on (KON) signal is generated.

Tempo counter TCNT...Every time the tempo oscillator 28 generates the tempo interwoven signal TMP I NT,
This is a counter register that increments by 1'', and its count value represents the progress position within one bar of automatic performance.

Previous tempo counter TCNT (PR): A counter register that stores the tempo count TCNT value at the start of the latest record. If there is a key-on KON in record synchronization start mode or running record mode, that evening? Temporarily memorize mink.

Address pointer ADR: Counter register for specifying the address of the performance data memory 34.

Previous address ADH (PR): A counter register that stores the address ADR value at the start of the latest record. Key-on KON in record synchronization start mode or running record mode
If there is, the performance data memory 34 at that key-on
Temporarily store the address of.

Rewind flag REW...Recorder 10
This flag indicates the operating state of the address ADR, and when it is set to "1", it indicates a rewind mode in which the address ADR value is repeatedly decremented in a relatively short period.

Fast forward flag FF: A flag representing the operating state of the recorder 10, and when set to "1", it indicates a fast forward mode in which the increment of the address ADR value is repeated in a relatively short cycle.

FIG. 3 shows an overview of the panel section of the recorder 10. This panel section has a record (RE) for setting operation modes related to recording, such as recording mode, record synchronization start mode, and running record mode.
CORD) operator 36, starts playback and recording operations, and stops playback, recording, fast forward, and rewind operations without manipulating the previous tempo count value TCNT (PR) and previous address value ADR (PR). (stop at -)
a start/Bose (SRT/PSE) operator 38 for moving the address ADR forward and backward at a relatively high speed; a fast forward (FF) operator 40 for advancing and rewinding the address ADR at a relatively high speed; The previous tempo count value TCNT (PR
) and a previous address value ADH (PR) to initially set the stop mode, a stop (STOP) operator 44, a power switch 46, and a display 48 are provided. These mode setting control groups 36 to 4
4 is detected by a plurality of operator switches provided corresponding to each operator in the operator switch circuit 22 shown in FIG.
The display is controlled by 4.

The buffer circuit 26 connects the MIDI input terminal 50 and the MIDI
Data buses 54 and 5 connected to DI output terminal 52
This is an interface for transmitting and receiving performance data to and from the electronic musical instrument 60 via the electronic musical instrument 60.

The tempo oscillator 28 consists of a frequency divider with a variable frequency division rate, and divides the frequency of the clock pulse of a constant period output from the timer oscillator 30 according to a set tempo, and generates a tempo-interrupted signal TMP I NT according to the tempo. bus 14
It is output to the microcomputer 12 via.

The timer oscillator 30 is composed of an oscillator with a fixed frequency, and outputs an oscillation output of a fixed frequency to the tempo oscillator 28, and also outputs a timer-interrupted signal TIMEIRT.
It is outputted to the microcomputer 12 via the bus 14 as a. This timer intertwined signal TIMEIRT indicates the fast forward and rewind speeds, that is, the address A at this time.
Used to determine the rate of change of DR.

The various registers and buffers 32 are for temporarily storing various data generated when the microcomputer 12 executes the program, and are constituted by RAM, for example, the data that the microcomputer 12 takes in from the buffer circuit 26. It consists of an event buffer IVTBUF for temporarily storing performance data.

The performance data memory 34 is composed of a RAM, and has a large number of storage locations AP addressed by the address ADR set in the address register in the working memory 20.
M (ADR). Each memory location APM (ADR
) stores the following various types of automatic performance data in a data format as shown in FIG. The upper two bits of each data except for the end code are identification marks indicating the type of data.

Timing data: Consists of an identification mark indicating that it is timing data, and time data TIMD indicating the elapsed time from the beginning of the measure. This time data TIM
Data corresponding to the tempo count value TCNT is written as D.

Key press data: an identification mark indicating that the data is a key press event data on a keyboard (not shown) of the electronic musical instrument 60;
It consists of a key code KC representing the pressed key.

I%I key data: Consists of an identification mark indicating that it is key release event data for the keyboard, and a key code KC indicating the released key.

Tone data, etc.: an identification mark indicating that the tone data or effect data has been updated by a tone control group or effect control group on the operation panel (not shown) of the electronic musical instrument 60, and the updated tone or effect. It consists of tone color and effect name data representing the name.

Measure code: This data indicates that the progress timing of automatic performance corresponds to the beginning of a measure, the identification mark is equal to the timing data, and the time data is equal to the timing data indicating the end of the measure.

End code: Indicates that it is time to end automatic performance.

(Description of the structure of the electronic musical instrument shown in FIG. 2) The electronic musical instrument 60 shown in FIG. 2 includes a key switch circuit 62 and an operator switch circuit 64. key switch circuit 6
2 has a plurality of key switches provided corresponding to the acceptance of a keyboard (not shown) for specifying a musical tone, and detects an acceptable press/release of a key on the keyboard based on the opening/closing of each key switch.

The operator switch circuit 64 includes a plurality of operator switches each corresponding to a tone operator group and an effect operator group arranged on an operation panel (not shown) for instructing the application of timbres and effects to musical sounds. , detects the operation of each operator on the operation panel based on the opening/closing of each operator switch. These key switch circuit 62 and operator switch circuit 64 are connected to a bus 66.

Furthermore, a buffer circuit 68, a musical tone signal generation circuit 80, and a microcomputer 90 are connected to the bus 66. The buffer circuit 68 is for transmitting and receiving performance data to and from the recorder 10 via the aforementioned data buses 56 and 54 connected to the MIDI input terminal 70 and output terminal 72. The musical tone signal generation circuit 80 is
It is equipped with multiple musical tone signal forming channels that each form musical tone signals corresponding to musical instruments such as pianos and violins.
Information generated in response to key presses and releases on the keyboard and operations of tone control groups and effect control groups on the operation panel, as well as performance data memory 3 in recorder 10.
4 and input via the buffer 1 circuit 26, 68 and the data bus 56, a musical tone signal is formed and output based on the performance data supplied from the microcomputer 90 via the bus 66. do. This musical tone signal is supplied to an amplifier 82. The output of the amplifier 82 is connected to a speaker 84, and the speaker 84 produces a musical tone corresponding to the musical tone signal supplied from the amplifier 82.

Microcomputer 90 consists of a program memory 92, a CPU 94, and a working memory 96, each connected to bus 66. The program memory 92 is a ROM
It stores a program corresponding to the flowchart shown in FIG. The CPU 94 starts executing the above program when a power switch (not shown) is turned on, and repeatedly executes the program until the power switch is turned on. The working memory 96 is composed of a RAM and temporarily stores a plurality of data and flags necessary for executing the program. The data to be temporarily stored in the working memory 96 includes, for example, event data indicating that the operation status of the keyboard and operation panel has changed, and performance data input from the recorder 10, and the memory 96 temporarily stores each of these data. Event buffer register IIVTBυF1 for storing
and IIVTBUF2 are set.

(Explanation of the operation of the embodiment) Next, the operation of the embodiment configured as described above will be explained in FIGS.
This will be explained with reference to the flowchart in FIG.

(1) Operation description of electronic musical instrument 60 When a power switch (not shown) is turned on in electronic musical instrument 60, CPU 94 of electronic musical instrument 60 starts executing the main program at step 100 in FIG. By clearing each register in the working memory 96, the microcomputer 90 is set to an initial state. After this initial setting, the CPU 94 scans each key switch in the key switch circuit 62 and each operator switch in the operator switch circuit 64 in step 102, thereby obtaining press slI information regarding the keyboard and information regarding the operation panel. The operation information of the controller is read through the bus 66, and the buffer circuit 68
If there is input information from the recorder 10, it is read therein, and in step 103, based on the read key press/release information, operation information, and input information, key press/release events on the keyboard are recorded in cooperation with the working memory 96. , the presence or absence of an operation event on the operation panel and an input event to the input terminal 70 is detected.

If no key is pressed on the keyboard, no operator is operated on the operation panel, and no information is input to the input terminal 70, the CPU 94
In step 103, it is determined that rNOJ, that is, there is no event, the program returns to step 102, and the circular processing consisting of steps 102 and 103 continues to be executed.

Also, if any key is pressed on the keyboard, any operator is operated on the operation panel, or some information is input to the input terminal 70, the C
Pt194 determines in step 103 that there is an event, that is, rYEsJ, and executes the program in step 104.
Proceed to key/timbre/effect event processing consisting of ~107. In step 104, the events detected while the CPU 94 executes one cycle of the cyclic processing in steps 102 and 103 are treated as having occurred simultaneously, and the event data that has occurred simultaneously is stored in the event buffer register IIVTBUF1 and the event buffer register IIVTBUF1 in the working memory 96. Incorporated into 2. Here, the press*i information regarding the keyboard and the operation information of each operator regarding the operation panel are taken into the event buffer register IIVTBUFI, and the recorder 1
Input information from 0 is event buffer register IIVT
It is taken into BUF2. Further, in step 105, all event data in event buffer registers IIVTBUFI and 2 are output to musical tone generation circuit 80. In this case, if the event data is data representing a key press on the keyboard (key press data), the musical tone signal generation circuit 80 generates a musical tone signal of a key tone high frequency corresponding to the key indicated by the key press data. and supplies the formed musical tone signal to the speaker 84 via the amplifier 82. As a result, the speaker 84 emits a musical tone having a key pitch frequency corresponding to the key pressed on the keyboard and the key specified by the key pressed data in the input information. Further, if the event data is data representing the wi key on the keyboard (key release data), the musical tone signal generation circuit 80 generates the released key and the input information that have been being formed up to now as described above. The formation and output of musical tone signals related to the key specified by the key release data is stopped. As a result, the speaker 84 no longer produces musical tones related to the key released on the keyboard and the key specified by the key release data in the input information.

On the other hand, if the event data supplied to the musical tone signal generation circuit 80 is related to a tone control group or an effect control group as described above, the same generation circuit 80 is operated based on the supplied event data. The timbre of the generated musical tone signal or the effect imparted to the signal is controlled in accordance with the operator specified by the operator specified by the operator and the operator specified by the timbre and other data in the human input information. As a result, the timbre of the musical tones to be produced and the effects imparted to the musical tones are controlled in accordance with the operations of the tone color operator group and the effect operator group and the input information.

After the processing in step 105 above, the CPU 94 performs step 1
At step 06, all event data in the event buffer register IIVTBUFI is output to the external output terminal 72. Thereby, key press/release information regarding the keyboard of the electronic musical instrument 60 and operation information of each operator regarding the operation panel are outputted to the recorder 10 as performance data.

Subsequently, the CPU 94 clears all event data in the event buffer registers IIVTBUFI and 2 in step 107, and returns the program to step 1.
Return to 02. Then, the CPU 94 again performs step 1 above.
02 and 103 is executed, and during the circulation process, if there is a key press on the keyboard, an operation on the timbre operator group and the effect operator group, or performance data from the recorder 10, the steps 104 to 103 described above are performed. Through the process 107, the generation of musical tones is controlled in accordance with the press *m or operation or input information as described above.

(2) Operation explanation of recorder 10 2-1. When the power switch 46 (FIG. 3) is turned on in the main processing recorder 10, the CPU 18 of the recorder 10 starts executing the main program in step 200 in FIG. The microcomputer 12 is set to an initial state by clearing the registers and flags. After this initial setting, CP
U18 detects the presence or absence of an event at input terminal 50 by accessing buffer circuit 28 in step 202. Furthermore, in each of steps 203 to 207, the record switch 36, start/bose switch 38, stop switch 44, rewind switch 42, and fast forward switch 40 are scanned to detect the presence or absence of an event at each switch. No information is input to the input terminal 50, and each switch 38 to 4
If none of Steps 202 to 207 have been operated, the CPU 18 determines "NO" in each of Steps 202 to 207, that is, there is no event, and continues to execute the circular process consisting of Steps 202 to 207.

2-2. Record switch process During the circulation process consisting of steps 202 to 207 in FIG. 5, when the record switch 36 is operated, the CPU 18
In step 20.3, it is determined that there is an event, and the program proceeds to step 209.
At step 209, record switch processing shown in detail in FIG. 6 is executed.

In this record switch process, step 300
Its execution is started in steps 301 to 303, and it is determined whether the playing flag FLY, recording flag REC, and playback flag FLYPSE set in the working memory 20 are each 1''. .

When the cpuia determines that both rNOJ, that is, the playing flag FLY and the recording flag REC are "0" in the determination processing of steps 301 and 302, it performs the determination of step 303 and If the flag FLYPSE is “1”, step 304
After resetting the flag FLYPSE at , if the flag FLYPSE is “0”, skip step 304 and set the flag FLYPSE to the reset state (“0”).
''), the program proceeds to step 305.The CPU 18 further sets the record board flag RECPSE in step 305, and then terminates the execution of this record switch process in step 306, and continues the program. The process returns to step 204 in Fig. 5. That is, when the record switch 36 is operated during an operation mode other than playback and recording (and fast forwarding and rewinding), the operation mode of the recorder 10 is set to the record synchronization start state. This record synchronization start state is a mode in which the recording operation is temporarily stopped in the recording standby state and the recording operation is started in synchronization with the press 1! (key-on) on the electronic musical instrument 60.

Further, if the reproducing flag FLY is "1" in the determination process of step 301, the process proceeds to step 307, sets the running record flag FLUNREC, and then ends the record switch process in step 306. , returns the program to step 204 in FIG. That is, when the record switch 36 is operated during playback, the operation mode of the recorder 10 is set to the running record flag. This running record mode allows you to reserve recording while continuing the playback operation.
This mode shifts to the recording state in synchronization with the key-on of the 0 key.

Furthermore, if the reproducing flag FLY is "O" and the recording flag REC is 1" in the determination processing of steps 301 and 302, the previous tempo count value TCNT ( PR) and previous address value ADH (PR'
), the recording flag REC is reset, and the record board flag RECPSE is set in step 305.
After setting, the execution of the record switch process is ended in step 306, and the program returns to step 204 in FIG. Set to beam/record mode. This recording mode is a mode for re-recording from the recording position at the start of the most recent recording operation before the record switch 36 was operated, and the tempo count TCNT and address AD
In this mode, after setting the H to the recording position, the record synchronization start state is entered, and the recording operation is resumed in synchronization with the key-on of the keyboard of the electronic musical instrument 60.

2-3. Start/Bose Switch Processing During the circulation process consisting of steps 202 to 207 in FIG.
When the Bose switch 38 is operated, the CPU 18 determines rYESJ, that is, an event has occurred, in step 204, advances the program to step 210, and executes the start/Bose switch process detailed in FIG. 7 in step 210. .

In the start/Bose switch process of FIG. 7, execution begins at step 350, and step 351
The record Bose flag RECPSE and recording flag RE set in the working memory 20 at ~356
It is determined whether the C1 fast-forward flag FF, rewind flag REW, reproducing flag PLY, and playback flag PLYPSE are each "1".

In the determination processing of steps 351 to 355, the CPU 18 sets rNOJ, that is, the record Bose flag R.
ECPSE, recording flag REC.

When it is determined that the fast forward flag FF, rewind flag REW, and playing flag FLY are all 0,
After making the determination in step 356, the playboze flag F
If LYPSE is 1", the flag FLYPSE is reset in step 361, and if the flag FLYPSE is "0", the flag FLYPSE is kept in the reset state ("0") from step 356. The program proceeds directly to step 357.

The CPU 18 further inverts (i.e. sets) the playback flag FLY in step 357, and then proceeds to step 35.
At step 8, the execution of the start/Bose switch process is completed and the program returns to step 205 in FIG.
The operation mode of the recorder 10 becomes the playback mode.

If the record Bose flag RECPSE is 1'' in the determination process of step 351, the process proceeds to step 359, where the record Bose flag RECPSE is reset, and after setting the record flag REC, this start/Bose switch process is performed in step 358. is finished, and the program returns to step 205 in Figure 5.In other words, in the record synchronization start state,
When the Bose switch 38 is operated, the operation mode of the recorder 10 becomes a recording mode.

In the determination processing of steps 352 to 354, the recording flag REC, fast forward flag FF, and rewind flag REW are set.
If any one of them is "1", the program proceeds directly from these steps to step 358, ends the execution of the start/Bose switch processing, and returns the program to step 205 in FIG. That is, even if the start/bose switch 38 is operated during recording, fast forwarding, or rewinding, the operation is ignored in this start/bose switch processing.

Furthermore, in the determination process of step 355, the reproduction flag P
If LY is 1'', the playback flag FLYPSE is set in step 360, the playback flag FLY is inverted (ie, reset) in step 357, and the start/bose switch processing is executed in step 358. When finished, run the program to step 2 in Figure 5.
Return to 05. That is, when the start/pause switch 38 is operated during playback, the operation mode of the recorder 10 becomes the play synchronization start mode. In this play synchronization start mode, when the keyboard of the electronic musical instrument 60 is operated and a key-on signal is generated, playback (automatic performance) is started in synchronization with the keyboard operation.

2-4. Stop switch processing A cycle consisting of steps 202 to 207 in FIG.
During processing, when the stop switch 44 is operated, the CPU
18 determines in step 205 that "rYES", that is, there is an event, and advances the program to step 211, where the stop switch process shown in detail in FIG. 8 is executed.

In the stop switch process shown in FIG.
Its execution starts at step 00, and at step 401, the record board flag RECPSE and play board flag FLYP set in the working memory 20 are set.
S E, recording flag REC and playback flag FLY
is reset, address ADH, previous tempo counter register TCNT (PR) and previous address register AD
After H(PR) is cleared, the execution of the stop switch process is ended in step 402, and the program returns to step 206 in FIG. That is, when the stop switch 44 is operated in a mode other than fast forward or rewind, the operation mode of the recorder 10 is set to the stop mode. In addition, when fast forwarding and rewinding,
As will be described later, the operation of this stop switch 44 is ignored.

2-50 Rewind switch process When the rewind switch 42 is operated during the circulation process consisting of steps 202 to 207 in FIG. The process advances to step 212, and in step 212, the rewind switch process shown in detail in FIG. 9 is executed.

In the rewind switch process of FIG.
The execution starts at step 0, and the record Bose flag R set in the working memory 20 at step 501.
After ECPSE, playback flag FLYPSE, recording flag REC, reproduction flag FLY, and fast forward flag FF are reset, it is determined in step 502 whether address value ADR is "0". If the address value ADH is "0", this is the beginning position of the performance data memory 34 and no further rewinding is possible, so the CPU clears the tempo count value TCNT in step 503 and sets the play pause flag. FLYPS
After setting E, the execution of the rewind switch process is terminated in step 504, and the program returns to step 207 in FIG. In other words, the address value ADR is “O
'', when the rewind switch 42 is operated, the operation mode of the recorder 10 is not set to the rewind mode but to the play synchronization start state.

On the other hand, if the determination in step 502 is rNOJ, that is, if the address value ADR is other than "0", the CPt 118 advances the program to step 511;
The rewind flag REW is set in step 512, and the address value ADH is decremented (r-1'') in step 512, and the performance data recording amount (or remaining memory amount) is set in the panel section based on the new address value ADH. indicator 48
(FIG. 3) - After displaying the bar graph, it is determined in step 513 whether the address value ADR is "0". If rNOJ is not "0" in the judgment in step 513, then in step 514 the start/Bose switch 38
Determine whether or not the has been operated. If the switch 38 has not been operated, the timer value T is checked in step 515, and an idle link process is executed in which the processes of steps 514 and 515 are repeated until the timer value T becomes "0" or the switch 38 is operated. When the timer value T becomes "0" as determined in step 515, the CPU 18 returns the program to step 512 and decrements the address value ADH.

The timer value T is determined by the interrupt signal TIME from the timer oscillator 30.
Each time IRT is output, the CPU 18 executes the timer interwoven process shown in FIG. 10, which decrements the predetermined value n, and becomes "0" for every n interrupt signals TIMEIRT. That is, the address value ADR is decremented at a cycle that is n times the cycle of the interrupt signal TIMEIRT.

When the address value ADH becomes "0", rYEsJ is determined in step 513 of FIG. 9, and the program proceeds to step 516. The CPU 18 performs step 51.
After the rewind flag REW is reset in step 6, the execution of the rewind switch process is ended in step 504, and the program returns to step 207 in FIG. That is, when the address value ADR becomes "0" during the rewinding operation, the operation mode of the recorder 10 becomes the stop mode.

If the start/pause switch 38 is operated during the rewinding operation, the determination in step 514 is rYEsJ, and the program proceeds to step 516.

In step 516, the CPU 18 sets the rewind flag RE.
After resetting W, the execution of the rewind switch processing is terminated in step 504, and the program returns to step 207 in FIG. 5. That is, when the start/bose switch 38 is operated during the rewinding operation, the operation mode of the recorder 10 becomes the stop mode.

Note that during this rewinding operation, operations on switches 36 and 46 to 48 other than the start/Bose switch 38 are ignored.

2-6. Fast forward switch processing When the fast forward switch 40 is operated during the cyclic process consisting of steps 202 to 207 in FIG. At step 213, fast forward switch processing shown in detail in FIG. 11 is executed.

In the fast forward switch process of FIG. 9, step 60
The execution is started at step 601, and the record Bose flag R set in the working memory 20 is set at step 601.
ECPSE, playboze flag PLYPSE
, the recording flag REC, the playback flag FLY, and the rewind flag REW are reset, and in step 602, the address value ADR is incremented (r+IJ), and the performance data recording amount (and memory remaining amount) on the panel display 48 (
After displaying the bar graph in FIG. 3), in step 603 it is determined whether the data stored in the storage location APM (ADR) of the performance data memory 34 is an end code. If it is not an end code, the CPU 18 determines in step 604 whether the start/Bose switch 38 has been operated. If the switch 38 is not operated, the timer value T is checked in step 605, and the processing of steps 604 and 605 is repeated until the timer value T becomes "0" or the switch 38 is operated. Execute processing. When the timer value T becomes "O" as determined in step 605, the CPU 1B returns the program to step 602 and increments the address value ADR. The timer value T is decremented in the timer interlude process of FIG. 10 in the same way as in the rewind switch process as described above. Therefore, the cycle of incrementing the address value ADR in this fast-forward switch process is also n times the cycle of the interrupt signal TIMEIRT.

When the address value ADR advances and the end code is read from the storage location APM (ADR), fast forwarding is meaningless because no performance data is stored in the subsequent storage location. In this case, the determination in step 603 is rYEsJ, and the program proceeds to step 606. C.P.
After resetting the fast-forward flag FF in step 606, U18 finishes the execution of the fast-forward switch process in step 607, and returns the program to step 2 in FIG.
Return to 02. If the start/pause switch 38 is operated during the fast-forward operation, the determination in step 604 is rYEsJ, and the program proceeds to step 606. After resetting the fast-forward flag FF in step 606, the CPU 18 terminates the execution of the fast-forward switch process in step 604, and returns the program to step 207 in FIG. 5. That is, when the end code is read out during the fast forward operation or the start/bose switch 38 is operated, the operation mode of the recorder 10 becomes the stop mode. It should be noted that during this fast forward operation, the operations of the switches 36 and 46 to 48 other than the start/Bose switch 38 are ignored, as in the case of rewinding.

2-7. In the input data multi-processing recorder 10, steps 202 to 2 in FIG.
During the circulation process consisting of step 07, when performance data is input from the electronic musical instrument 60 to the input terminal 50 as a result of the electronic musical instrument 60 executing the process of step 106 in FIG.
8 determines in step 202 that there is an event, that is, rYEsJ, and advances the program to step 208.
In step 208, input data processing shown in detail in FIG. 12 is executed.

In the input data processing of FIG.
The execution starts at step 70, and the CPU 18 executes step 70.
After all event data in the buffer circuit 2B is loaded into the event buffer IVTBUF in step 1, step 70
In step 2, it is determined whether the event data in the event buffer IVTBUF includes key code data. If it is determined in step 702 that the key code data is stored in rYEsJ, that is, in the event buffer IVTBUF, the CPU 18 executes the program in step 70.
Proceed to Step 3, and the play Bose flag PLYPSE and record Bose flag REC set in the working memory 20 in each step 703 to 706 are set.
It is determined whether PSE, running record flag RUNREC, and recording two-lag REC are each "1".

, If rNOJ is determined in the determination processing of steps 703 to 706, that is, if it is stopped or playing, CP
In step 707, U18 stores the event buffer IVT.
After clearing the BUF, the execution of this input data processing is ended in step 708 and the program returns to step 203 in FIG. 5. In this case, the performance data input from the electronic musical instrument 60 to the input terminal 50 is completely ignored. will be done.

If the playboze flag PLYPSE is 1'' in the step 7030 determination process, that is, the recorder 10 is in the play synchronization start state, the CPU 18
The program advances to step 710, and step 10
At the same time, the play pause flag PLYPSE and recording flag REC are reset, and the playback flag FL is reset.
After setting Y, the event buffer IVTBUF is cleared in step 707, the execution of this manual data processing is ended in step 708, and the program returns to step 203 in FIG. 5. That is, in the play synchronization start state, playback (automatic performance) is started in synchronization with key-on.

In the judgment process of step F04, if the record board flag RECPSE is "1", that is, if the recorder 10 is in the record synchronization start state, the CPU 18 advances the program to step 720, and in step 720 sets the record board flag REC. At the subsequent step 721, the recording flag REC is set, the playing flag FLY is reset, and the current tempo count value TCNT is set in the previous tempo counter register TCNT (PR) and the previous address register ADH (PR), respectively. and after storing the address value ADR,
In step 706, it is determined whether the recording flag REC is "1". In such a case, since the recording flag REC was set in step 21, step 7 is executed.
The determination process for 06 is rYEsJ, and the program proceeds to step 731, and for CPo 18, step 731
The automatic performance data writing routine of ~737 is executed. That is, in the record synchronization start state, recording (writing) starts in synchronization with key-on.

For this reason, there is no blank space between when the recording mode is set and when the keyboard is played, and during playback, there is no sound at the beginning, making the performer uneasy, and the blank space wastes memory. Furthermore, when inputting a so-called weak-start song that is played slowly after a rest at the beginning of the song, first operate the record switch 36 to set the record synchronization start mode, and then It is only necessary to operate the start/Bose switch 38 to switch to the recording mode, and to start playing (key-on) when a period corresponding to a rest has elapsed.

In the performance data writing routine, first, in step 731, the storage location APM of the performance data memory 34 is
Timing data is stored in (ADH) as performance data. As shown in FIG. 4, this timing data consists of an identification mark and time data TIMD, the identification mark is set to a code indicating that the performance data is timing data, and the time data TIMD is set to a tempo count TCNT. is set to the value shown. As a result, the time data TIMD indicates timing corresponding to the time from the bar break.

After the processing in step 731, the CPU 18 processes address ADR in step 732 by sidewalk processing (ADH=ADR
+1)L, , new address value AD in step 733
After displaying the performance data recording amount in a bar graph on the display 48 of the panel section (FIG. 3) based on R, in step 734, one piece of event data stored in the event buffer register IVTBUF by the process of step 701 is displayed. Then, an identification mark is attached to the extracted event data to make it performance data, and it is stored in the storage location APM (ADR) of the performance data memory 34. Further, in step 735, the event data retrieved in step 734 in the event buffer register is cleared, and in step 736, it is determined whether any event data remains in the event buffer register. In such a case, if event data remains, step 736 described above is performed.
It is determined that the event is rYEsJ, and the CPo 18 returns the program to step 732 to execute the next event data write process. On the other hand, when there is no remaining event data in the event buffer register, the CPU 113 makes a "NO" determination in step 736 and advances the program to step 737. Furthermore, after the address ADR is incremented in this step 737, the execution of this input data processing is terminated by the processing in step 708, and the program returns to step 203 in FIG.

In the determination process of step 705, the running record flag RUNREC is "1", that is, the recorder 10
is set to running record mode, the CP
U 18 advances the program to step 721 to reset the running record flag RUNREC, and after executing the processes of steps 721 and 706, executes the automatic performance data writing routine of steps 731 to 737. That is, in the running record mode, the reproducing operation is executed and the reproducing state is continuously shifted to the recording state in synchronization with the key-on.

Therefore, according to this mode, recording can be restarted by turning on the key at any timing during play, making it easy to modify or add performance data. For example, even if you make a mistake, by playing back the correct part and starting the performance (key-on) just before the wrong part, you can edit extremely smoothly in real time without timing deviation.

Furthermore, in this recorder 10, the step 7
At step 21, the tempo count value TCNT and address value ADH at the time the key is turned on in the record synchronization start mode or running record mode are memorized.
When the recording switch 36 is operated, step 308 (
In FIG. 6), the tempo counter TCNT and address pointer ADR are set. In other words, by operating the recording switch 36 during recording, it is possible to synchronize the next recording with the timing TCNT and storage position ADR set to the point at which the previous recording was started, or to realize a record state. This allows real-time editing of performance data to be cut into small pieces.
You can try until you can execute it perfectly. Further, the beginning of this "broken" section can be arbitrarily set to be the point of a mistake or a sharp point just before the point of a mistake. Incidentally, if the edit operation is not required, the stop switch 44 can be operated to cancel the record state and bring the record state to a stop state.

If the recording flag REC has already been set in step 721 or Stellar 359 (FIG. 7),
That is, if recording is in progress, steps 703 to 705 are performed.
Both judgments are rNOJ, and step 7
The determination of 06 is rYES. Therefore, in this case as well, when event data including key code data is manually input to the input terminal 50 from the electronic musical instrument 60, step 731
In the automatic performance data writing routine consisting of steps 737 to 737, the event data and the occurrence timing TIMD of the event data are recorded in the performance data memory 34.

Through the process of step 701, the event buffer IV
If the key code data is not included in the event data imported to TBUF, that is, if the event data is only timbre data and measure data, the determination in step 702 is rNOJ, and CPIJIB.
advances the program to step 740 and sets the recording flag R.
Check EC and record pause flag RECPSE. If the recording flag REC and the record pause flag RECPSE are both "0", the program proceeds to step 707, where the event buffer IVTBLIF is cleared, and in step 708, this input data processing is completed. When the execution is finished, the program returns to step 203 in FIG.

On the other hand, in the determination at step 740, rYEsJ, that is,
Recording flag REC and record pause flag REC
If any of the PSEs is "1", the CPU advances the program to step 733 and executes the processes of steps 733 to 737 and 732 described above. As a result, when event data that does not include key code data is input to the input terminal 50, only the event data is recorded in the performance data memory 34 without timing data. Therefore, even in the synchronized record start state, automatic performance data based on changes in tone color or setting operations can be recorded without advancing the timing.

2-8. Tempo interlat processing Main processing or its subroutine processing shown in FIG. 5 (
6 to 12), when the tempo clock signal TMP I NT is generated from the tempo oscillator 28, the CPU
Step 18 interrupts the execution of the program and starts executing the tempo interwoven program shown in FIG. 13 from step 900, and in step 903 the playing flag FLY is set to
1". In this case, if the reproducing flag FLY is "O", that is, if the recorder 10 is set to a mode other than the reproducing mode, the determination process of step 903 determines rNOJ, The program proceeds to step 904.
In step 04, the tempo count TCNT is incremented by "1" by executing the calculation TCNT=TCNT+1, and in step 905 it is determined whether or not the incremented tempo count TCNT indicates the end value of the measure. Tempo count TC
If NT does not indicate the measure end value, it is determined to be rNOJ in the determination process of step 905, and the program proceeds to step 906, where step 90
At step 6, the execution of the tempo interwoven process ends.

On the other hand, the tempo count TC incremented in step 904
If NT is the bar end value, the CPU 18 determines "rYES" based on the tempo count TCNT in the determination process of step 905, and then performs step 907.
In step 908, the tempo count TCNT is initialized to "0" and the program proceeds to step 908. Step 90
In step 8, it is determined whether or not the recording flag REC is set to 0.
Therefore, the CPU 18 returns "NO" in step 908.
”, and in step 906 the execution of this tempo interwoven processing is terminated. In addition, if the determination in step 908 is ``YESJ'', that is, the recorder 10 is set to the recording mode and the recording flag REC is 1'°, the CPU
18 advances the program to step 909, where the storage location APM (
A measure code (see FIG. 4) consisting of identification data representing timing data and the value before incrementing in step 904 (measure end value - 1) is written in ADH), and in step 910 ADR After the address ADH is incremented by "1" by executing the calculation =ADR+1, the execution of the tempo interrupt program is ended in step 906.

2-9. Automatic Performance Data Reading Routine Process As mentioned above, during the cyclic process consisting of steps 202 to 207 (FIG. 5), the start/Bose switch 38 is operated in the stopped state, or the start/Bose switch 38 is operated in the play synchronization start state. 38 is operated or the keyboard performance of the electronic musical instrument 60 is started (key-on), the recorder 10 is set to the playback mode.

In this state, when the tempo clock signal is generated from the tempo oscillator 30, the tempo interwoven process is executed, and the tempo count TCNT is executed by the processes of steps 900 to 908.

In such a case, if the playback flag FLY is set to "1", the C
The PU 72 determines rYEsJ in step 903, and in step 911 executes the automatic performance data reading routine shown in detail in FIG.

This automatic performance data reading routine is executed at step 95.
0, the CPU 18 first executes step 951.
It is determined whether the read timing data RDTIM is equal to the tempo count TCNT. Now, the read timing data RDT I M and the tempo count TC
If the NTs are not equal, it is determined in step 951 that the result is rNOJ, and in step 952 execution of this automatic performance data reading routine is terminated. On the other hand, when the tempo count TCNT increases and the read timing data RDT I M becomes equal to the tempo count TCNT, the CPU 18 executes rYEsJ in step 951.
It is determined that the address ADR is "1" in step 952.
At step 953, the automatic performance position is displayed as a bar graph on the display section 48 of the panel section (FIG. 3) based on the incremented address ADR, and at step 954, the performance data memory 34 is Memory location APM
(ADR) and sets the read performance data as read data RDDT.

Next, the CPU 18 executes steps 955, 956 and 9.
57, it is determined whether the read data RDDT is timing data, end code, measure code, or other data (key press data, key release data, tone color data, etc.). Now, if the read data RDDT is other data (key press data, key release data, tone data, etc.), step 95
5. All rNOJ in each judgment process of 956 and 957
It is determined that the read data RDD is read in step 958.
T is output to the output terminal 52. In the electronic musical instrument 60, this read data RDDT is input to the input terminal 70 via the data bus 56, and the read data RDDT is inputted to the input terminal 70 via the data bus 56, and
3 (FIG. 15), it is detected as an input information event, and is output to the musical tone signal generation circuit 80 via the bus 66 in the process of step 106. The musical tone signal generating circuit 80 controls the formation of a musical tone signal based on the supplied key press data, key release data, tone color data, etc., and outputs the formed musical tone signal to the speaker 84 via the amplifier 82. , a musical tone corresponding to the musical tone signal is emitted from the speaker 84. As a result, the speaker 84 starts producing automatic performance sounds based on the performance data stored in the performance data memory 34 of the recorder 10.

In the recorder 10, after the processing in step 958, the CPU 18 returns the program to step 952, increments the address ADR by "1" in step 952, displays the bar graph in step 953, and then The storage location APM in the performance data memory 34 specified by the incremented address ADR at 954
The performance data stored in (ADR) is set again as lead data RDDT, and furthermore, the type of this lead data RDDT is determined by the processing of steps 955 to 957. In such a case, if the read data RDDT is again key press data, single key data, tone color data, etc., the generation of musical tones is controlled again by the process of step 958.

In this way, all key press data stored at the same timing! 11! Data, timbre, and other data are read from the performance data memory 34 to control the generation of automatically performed musical tones.

During the circulation process consisting of steps 954 to 958, when the setting in step 954 or the one-day data RDDT becomes timing data, the CPU 18 returns to step 95.
In step 5, it is determined that the read data RDDT is rYEsJ, and in step 959, the same read data RDDT is read timing data RDT I.
M is set, and the execution of the automatic performance data reading routine is ended in step 952. Furthermore, when the -do data RDDT set in step 954 becomes a bar code, the CPL 118 sets rY in step 957.
EsJ is determined, and in step 961 the data RDT I
Set M to a value that is 1 less than the measure end value in step 905 (FIG. 13), and step 952
Then, the execution of the automatic performance data reading routine is ended. After that, the process consisting of steps 950 to 952 described above is executed every time the tempo interlat process is executed, and when the set read timing data RDT I M becomes equal to the tempo count TCNT, the CPU 18 executes the process consisting of steps 954 to 958 described above. The above processing is executed to control the pronunciation of automatically played musical tones.

In addition, the read data R set in step 954 above
When DDT becomes the end code, the CPU 18 proceeds to step 9.
After determining rNOJ at step 55, rYE at step 956.
sJ, and in step 962, the reproducing flag FLY is set to 0'' to stop the automatic performance reproducing mode.
At step 952, execution of the automatic performance data reading routine is ended.

[Modifications of Embodiments] Note that the present invention is not limited to the above-mentioned embodiments, and can be implemented with appropriate modifications. For example, in the above example, the performance data output from the electronic musical instrument 60 does not include time axis data such as timing, and the recorder 10
However, the timing data is also included in the performance data output from the electronic musical instrument 60, and the recorder 10 measures the manual timing of the performance data and adds time axis data. Data may also be simply recorded.

Further, in the above description, no particular mention was made of the recording of the end code, but this end code can be recorded by applying the same concept as that of conventionally known devices.

Furthermore, in the above description, the tempo count TCNT is reset at each bar break, but it may be reset when event data arrives or is read. That is, in the above embodiment, the tempo count TCNT value indicates the timing within a bar, but it may also indicate the time interval between each event.
In the latter case, when reading performance data, the time data at the time of the event can be taken into a timer register, and the value of this register can be counted down by -1 every tempo pulse using a subtraction method.

[Brief explanation of the drawing]

FIG. 1 is a claim correspondence diagram corresponding to the above claims; FIG. 2 is a block diagram of an automatic performance system equipped with an automatic performance recording and reproducing device according to an embodiment of the present invention; FIG. 2 is an overview diagram showing details of the panel section of the recorder in the system of FIG. 2, FIG. 4 is a format diagram of various performance data stored in the performance data memory of FIG. 2, and FIGS. 5 to 14 are FIG. 2 is a flowchart corresponding to an example of a program executed by the microcomputer of the recorder, and FIG. 15 is a flowchart corresponding to an example of the program executed by the microcomputer of the electronic musical instrument in FIG. 2. . 10: Recorder, 12: Microcomputer, 22:
Operator switch circuit, 28: Tempo oscillator, 34: Performance data memory, 36: Record switch, 38 Start/pause switch, 62: 11 Switch circuit, 64
: Operator switch circuit, 80: Musical tone signal generation circuit, 90
: Microcomputer.

Claims (1)

[Scope of Claims] 1. Performance data memory means for storing performance data for controlling the generation of musical tones as the music progresses, and a performance in which the performance data that is sequentially generated as the music progresses is stored in the performance data memory means. A data recording means, a running record mode selection means, and an operation mode of the performance data recording means are first set to a recording reservation mode in which the playback operation state is maintained when the running record mode is selected by the mode selection means. and operation mode control means for continuously switching to the recording mode without changing the address during the reproduction operation state when key-on data indicating the generation of the first musical tone is generated. Automatic performance recording and playback device.