JPH0117178B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a control section of a digital computer, and more particularly, to a control section of a digital computer using an arrangement for quickly, flexibly, and efficiently decoding a computer's machine language instructions. Pertains to microprogram controlled memory. Here, the present invention is a MOS/
Although primarily described with respect to LSI configurations, the basic techniques of the invention are also applicable to other types of configurations, such as standard bipolar components.

BACKGROUND OF THE INVENTION Modern computers use microprogramming techniques to configure their controls. This involves storing in a control memory microprograms representing sequences of machine controls for executing microinstructions or machine language instructions. This control memory may consist of some type of read-only memory (ROM) or writable memory. Sequencing through the microprogram is controlled by a microlevel program counter, or by sending the address of the next microinstruction in a control word with the microinstruction. Although this latter method is described herein, the invention is not limited thereto.

In order to execute a computer's machine language instructions, it is necessary that the microprogram sequencer be directed to the beginning of the microprogram sequence for the current machine language instruction that is present in the instruction register and is being executed. The usual way to decode computer instructions and direct microprogram sequences is to "map" the instructions, especially the operating code, to a start control memory address via ROM or PLA (Programmable Logic Array). . In many cases, only one initial mapping is necessary to direct the control logic into the correct sequence to execute the instructions. Subsequent mapping can be performed, or a conditional micro-level branch can be taken by testing some bits or combinations of bits in the instruction register.
Micro-level subroutines can be used to aid in the execution of instructions and to transfer control to other parts of the microprogram without losing the results of the initial mapping, but of course when calling a subroutine, The first mapping is picked up from the address.

Generally, the mapping mechanism provides a control memory address that is used to access the first microinstruction obtained by decoding the instruction. The serial operation of first obtaining the address by a mapping operation and then accessing the first control word is a waste of time. This is because the mapping time is generally approximately the same as the time for accessing the control memory. The present invention relates to saving substantial time in decoding machine language instructions.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a microprogram controlled memory using an arrangement that quickly, flexibly, and efficiently decodes computer machine language instructions. be.

Another object of the invention is to provide a microprogram control memory that simultaneously decodes computer machine language instructions and accesses a first control word resulting from the decoding.

Yet another object of the invention is to allow one or more control words to change the bits or codes of other control words to change their interpretation, thereby reducing the number of control words needed. It is an object of the present invention to provide a microprogram control memory that reduces

Still another object of the present invention is to provide a PLA and a ROM section, wherein the control word accessed without direct dependence on the current instruction or branch condition is in the PLA.
Generally smaller and cheaper than structures
The control word stored in the ROM part structure and accessed depending on the current instruction is to provide a microprogram control memory that can be stored in the PLA structure.

Yet another object of the present invention is to have both ROM and PLA structures in the form of MOS/LSI circuits, which by merging reduce circuits and interconnect lines to reduce the size of the chip. The purpose of the present invention is to provide a microprogram controlled memory that can be controlled by a microprogram.

Yet another object of the invention is that the control word is accessed by both the instructions being executed and the state of the machine, so that the sequencing of the computer's controls is controlled by the computer machine instructions being executed by the PLA and by the current state of the machine. The purpose of the present invention is to provide a PLA portion of the microprogram control memory that directly depends on certain branch conditions that reflect the state of the machine.

Yet another object of the invention is to provide a control memory that uses the PLA portion of the microprogram control memory as a means for decoding instructions and machine states, and that uses ROM to efficiently store control words. That's true.

Means for Solving the Problems According to one aspect of the invention, it is an object of the invention as set forth above to provide a PLA or programmable logic array for storing control words; This is accomplished by providing a microprogrammed computer control with both ROM or read-only memory. The addressable portion of the ROM storage structure is selected by the address input from the next address register. The PLA control word is selected by some or all of the instruction inputs from the instruction register, address inputs, and branch signals representing the current machine state. A multiplexer connected to the ROM section and the PLA section selects their output based on a decoded bit of the address input from the address register. This output provides the microinstruction and the address of the next sequential microinstruction. Means are also provided for connecting the next address output from the multiplexer to the next address register.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The microinstruction storage device of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings which illustrate embodiments thereof.

The present invention is a PLA for storing control words.
This constitutes a computer control unit having a control memory formed by a type and a ROM type structure. Read only memory (ROM) 4, shown in FIG. 1, is a random, access storage device in which data is permanently stored in memory and can therefore only be read. This memory has n address inputs which, when fully decoded, uniquely define 2 ⁿ storage locations. EPROM,
Devices such as PROM are also included in this same type.

The programmable logic array (PLA) 2 shown in FIG. 1 consists of two arrays, one of which is a set of AND gates, and the other is a set of OR gates. ) is a gate. The AND gate has as its input signals the true and its complement of the n inputs, which can be programmed to connect to the inputs as desired. The OR gate has an input from the output of the AND gate, and the connections of the AND gate array to the AND gate can be programmed as desired.

Both the ROM and PLA structures store control words consisting of microinstructions and next addresses, respectively. This control memory is shown in FIG. 1, made of a PLA type structure 2 and a ROM type structure 4 for storing control words. Each storage structure 2
and 4 each receive address inputs from register 6 of the next address through lines 12 and 14, respectively. Next address register 6 receives the next address portion of the last control word via next address line 30. PLA 2 also receives input signals 22 from the instruction register 8 and other input sources to be decoded. Other inputs to be decoded include input signals based on the state of the processor, for example for branching purposes (this state is well known and will not be described here). Typically, both the true and its complement of the input signal are used by the AND gate decoder of the PLA structure 2 and the ROM structure 4.

The ROM structure 4 comprises a ROM storage array 16 which actually stores the control words, and a row address decoder array 18. Row address decoder array 18 receives a portion of the address as its input, and its output is connected to ROM storage array 16.
Activate the row selection line. Each row selection line issued from the row decoder 18 is connected to the ROM storage array 1.
6, one of which is then selected by column multiplexer 20 under control of the remaining address bits from register 6 of the next address. Row decoder 18 is shared by multiple control words on each row select line and contains control memory.
Having fewer inputs than the AND gate decoder of PLA structure 2 is important when considering the silicon area required to implement the control memory as a MOS/LSI component.

PLA structure 2 comprises two parts: an OR gate array 24 and an AND gate array 26. In one particular embodiment, OR gate array 24
is ROM4 except that only one control word can be selected by each row selection line.
is constructed in the same manner as the storage array 16 of. AND gate array 26 performs an operation similar to that performed by row decoder 18, ie, acts as a decoder to activate the row select lines.
Since the PLA is essentially a single column, selecting a row is equivalent to selecting each control word in OR gate array 24. The PLA structure and gate array 26 are more important than the ROM storage array 16.
It is inefficient in terms of the amount of chip surface area required for LSI placement. This is because there is one decoder AND gate for each word, and AND gate array 26 has more inputs than row decoder 18 of ROM 4. The reason there is only one redecoder AND gate per control word is that the programming of AND gate array 26 must be unique for each control word. Each control word stored in the PLA structure 2 of the control memory is determined by the appropriate state of the address input supplied through line 12 and the command input to be decoded supplied through line 22, for example by the contents of a computer's command register. be accessed.

The selection between the PLA OR gate array 24 and the ROM storage array 16 is made by the multiplexer 28 in response to a signal consisting of a certain bit or combination of bits from the address stored in the register 6 at the next address 12. It is carried out with The number of bits required for selection depends on the number of rows (and gates) in PLA2, the number of rows in ROM4, and the number of control words accessed in each row of ROM4.

It is important to note that in this control memory organization, control words can reside in any part of memory. instruction register 8
The control word to be accessed by decoding the contents of the microinstruction code to a certain extent and decoding the state of the machine that would result in a branch of the microinstruction sequence is placed in the OR gate array 24 of the PLA. On the other hand, instructions and other words that do not directly depend on the state of the machine are placed in the storage array 16 of the ROM or the OR gate array 24 of the PLA. Successive words can be equally accessed from either PLA or ROM structures by specifying the next address in the desired storage range. The program's microinstructions can be intermixed in some way between the ROM's storage array 16 and the PLA's OR gate array 24, and in some embodiments may be directly attached to instructions (or branch conditions). Dependent microinstructions are
It only needs to be present within the OR gate array 24 of the PLA. Appropriate allocation can be handled by the assembly program when creating the microprogram.

As already mentioned, the inputs to AND gate array 26 of PLA structure 2 are generally the true and complement of the contents of register 6 at the next address sent over line 12 and the true and complement thereof from instruction register 8 on line 22. and the portions necessary to control the microinstruction program's sequencing of instructions sent to the PLA2 through the microinstruction program. The AND gate array 26 is
It is not necessary to completely decode the inputs, as is the case with the row decoder 18 of ROM 4, but only as many input signals from lines 12 and 22 as necessary to access each word. The next address from line 12 serves as a "mapping code" that selects a group of AND gates in AND gate array 26. The AND gate that is activated for each mapping code depends on the code of the instruction input provided over line 22 from instruction register 8. This process is described in the example below. The address range assigned to PLA structure 2 is not necessarily all used.
This is because the number of mapping codes required is equal to the number of mappings required. Using the mapping code as the next address, the access actuation of the control word is the code of the instruction register 8 or the individual bits (or the state of the machine that determines the branch in the microsequence).
The points of the microprogram that are affected by this are displayed. In practice, this mapping is similar to mapping described earlier with respect to other forms of control where mapping yields control addresses, but here
PLA structure 2 directly generates a microinstruction rather than the address of the microinstruction. This results in faster access to the microinstruction than if the mapping only provided the address of the control word. It also allows mapping to be done in control memory rather than in a separate structure. Each mapping code is an AND gate array 2
Since any number of AND gates can be controlled in 6, the PLA structure 2 can have an assigned address and any number of mappings up to the number of AND gates available. Flexibility is provided to the controller by allowing instruction inputs to be mapped or tested at any point in the microprogram without loss of time. Additionally, AND gates can be programmed with "careless" inputs, i.e., inputs that do not affect the mapping whose state is achieved.
One range or one set of mapping cords and/or
Or respond to an instruction code. This, when combined with the ability to modify control words as described below, results in a powerful microprogramming technique.

OR gate array 24, like storage array 16 of ROM 4, generates control words. Each control word is accessed under the control of an AND gate in AND gate array 26. One unique feature of this control mechanism is that logic functions can be performed on OR gate array 24 when more than one AND gate is activated at a time. This allows more than one word to be accessed at a time, and the resulting output is the OR or AND of all selected control words. The logic function performed depends on the logic polarity definition used for OR gate array 24. One or more control words overriding 1 or 0 can be used to modify another control word. This modification occurs at the next address portion of the microinstruction or control word. Using this technique requires specifying the address and microinstruction bits and codes so that the proper modification of the control word occurs. For example, a group of microinstructions can be programmed for byte operation, and all microinstructions in the group can be Instructions can be modified for word operation. Such a change word overrides the code or bits specifying byte operation with the code or bits specifying word operation.

Figure 2 shows the organization of the combined PLA and ROM structure. (Note that in the accompanying drawings the same or corresponding parts are designated with the same reference numerals.) The control memory is implemented in a MOS/LSI type configuration. Therefore, PLA and ROM structures can be combined on the same silicon chip. 2
By merging the two storage structures, the area occupied by the control structure can be reduced to some extent than having two separate structures. In conventional ROM designs, all example bit lines of a particular bit are placed adjacent to each other to facilitate output multiplexer layout. When the PLA and ROM are combined as in the embodiment shown in FIG. 2, the individual bit lines of the OR array of the PLA are as shown in FIG.
The ROMs may be placed adjacent to and interleaved with the corresponding ROM column bit lines. By interleaving the ROM and PLA bit lines in a ROM/PLA configuration and placing the corresponding bit lines adjacent to each other, a significant amount of busses is eliminated, and the area of the chip occupied by the ROM and PLA is reduced. Smaller size and higher operating speed. PLA bit lines 103 and 1
04 ROM bit lines 101 and 10 respectively
It should be noted that the intervening arrangement of adjacent gates 2 facilitates the connection of multiplexer 105 to the individual AND gates and OR gates.

In large ROM designs, the row decoder array is placed in the center of the storage array, and the row selection lines extend from either side of the decoder to the length of the selection line from the row decoder array to the far end of the storage array. It is common to drive up to half the control storage array. This speeds up access times by reducing row select line propagation delays. Such a technique is generally illustrated in FIG. Second
In the illustrated combined structure, a single AND gate/decoder combination 42 is located at the center of the storage array 44. This AND gate/decoder combination 4
2 serves as an AND gate array for PLA and a decoder array for ROM. Each row select line is activated by the output of one AND gate. Each of these AND gates acts as a PLA AND gate for one control word sent from the PLA structure via the row select line;
It also functions as a ROM decoder for other control words on the row selection line.

AND gate/decoder combination of combination structure 4
2 has two sets of inputs. Input 1 of one set
4 is the ROM sent through line 14 in Figure 1.
The inputs of structure 4 are the same and the other set of inputs 12 is sent through line 12 of FIG.
It is the same as the input of PLA structure 2. The AND gate of the AND gate array 42 is a combination of a PLA AND gate and a ROM decoder AND gate. The AND gate array 42 shown in FIG.
To operate as a PLA AND gate, the inputs of the PLA set are applied and all inputs of the ROM are enabled. The AND gate performs the function of PLA programming since enabling the ROM input effectively passes only the decoded PLA input.
Similarly, this AND gate/decoder combination 42
To act as a ROM decoder, the inputs of the ROM set are applied and all inputs of the PLA are enabled and effectively passed through the decoded ROM inputs. Combined AND gate array 42 is adapted to act as a PLA AND gate when the next address falls within the address range assigned to the PLA. At this time, one of the PLA column bitlines is selected by output column multiplexer 40. When the next address is within the address range assigned to the ROM, AND gate/decoder combination 42 is made to act as ROM decoder 18 and one of the ROM column bit lines is selected by output column multiplexer 40. Ru. AND gate/decoder combination 42 allows interleaving of ROM bit lines and PLA bit lines while simultaneously keeping the row select lines as short as possible. Chip area is also saved because the load pull-up or precharge circuit for a set of AND gates and the associated buffer amplifier, which are typically present in conventional configurations, are eliminated. .

An example of a circuit portion of a combined ROM and PLA control memory is shown in FIG. Although this example is basic and is shown for illustrative purposes only, the basic technique is applicable to many different control word and address bit lengths.

In this example, there are nine 2-bit control words, four in the ROM section and five in the PLA section of control storage 100. Control storage 100 is essentially divided into halves, ie, ROM storage array 16 of FIG.
one set of bit lines 101 and 102 for generating the control word (or portion of the control word in the illustrated example) to be generated by the OR gate array 24 of FIG. The other set of bit lines 103 and 104 generate portions of words. These two sets of bit lines are connected to address input 304.
A multiplexer consisting of AND gates 106 to 109 and OR gates 110 and 111 under the control of (A2 and the complement of A2) and performing the multiplexing action of multiplexer 28 of FIG. 1 and column multiplexer 40 of FIG. 105. Note that the example shown in Figure 2 does not explicitly demonstrate the technique of Figure 2, which places the AND gate/decoder combination in the center of the storage array and drives the row select lines from both sides of the decoder array. sea bream. Second
The configuration of the diagram is as follows: row selection bit lines 200 to 20
4 to the left and by locating the amplifiers 700 to 704 on the right side and the control storage device 100 in mirror image on the left side as well.

There are five row select lines 200-204, but only four of them 200-203 are used for ROM and five for PLA. (The extra row select line used only for this PLA is a bit inefficient since there is space for the 5th ROM word, but since the ROM's address inputs 303 and 304 are already fully utilized, (The fifth ROM word cannot be executed.) There are 10 inputs to this control memory. i.e. A0, A1 and A2
The three address lines and their complement lines (address inputs 300, 301 and 304) shown as
and two instruction register lines labeled I0 and I1 and their complement lines (instruction inputs 302 and 303). The address input 304 is
Multiplexer 105 is enabled to select between ROM and PLA. Address input A
2 ^* is applied and address input A2 is not applied, the ROM is selected and the signals from the bit lines 101 and 102 of the ROM are transmitted to the two output lines 600 and 601, and the PLA of the AND gate/decoder combination. 8 PLA inputs of AND gate part (OR gate 500 to 507
input) is energized. Address input 304
Address input A2 is given and address input A2 ^*
is not given, bitline 10 of PLA
The signals from 3 and 104 are connected to two output lines 60
0 and 601, and the four inputs of the ROM decoder portion of the AND gate/decoder combination (the inputs through OR gates 400-403) are activated.

In the example of FIG. 3, a large number of gates are represented by half-black circles and intersecting lines. A first orientation and two gates 800 are shown in FIG. 4a separated by dotted lines. The black circles 99 of these gates 800 indicate gate inputs. Input lines 811 and 812 are connected to gate input 99. A complete gate is indicated when either line (here line 820) is orthogonal to the input lines (here 811 and 812) and bisects circle 98. . Therefore, line 82 in Figure 4a
0 acts as an output line. An example of implementing the control memory in a ROM/FET type configuration is shown in FIG. 4b. The "gate" terminal 801 of the transistor functions similarly to the gate input 99 of FIG. 4a and is connected to input lines 811 and 812. The "drain" terminal 802 of the transistor is connected to an output line 820 which is orthogonal to the input lines 811 and 812. The "source" terminal 803 of the transistor is connected to a logic ground point 804. In the second orientation of FIG. A certain gate 900 is
It works similarly to gate 800 except that the supply line and gate connections are rotated 90 degrees counterclockwise.

An example of the code of the control memory shown in FIG. 3 is shown in FIG. Address bit A2 is 0
The first four addresses (ie, binary address values 000-011) access four words stored in the ROM portion of memory. The six addresses 100 and 101, where address A2 is 1, serve as mapping codes and enable part of the PLA portion of memory. Figure 3
The actual words generated by control store 100 in response to signals from the PLA AND gate array are provided by instruction inputs 302 and 3 from the instruction register.
It depends on the code of 03. An address input of 100 and a command input of any value (the symbol "X" in the table of Figure 5 indicates that the specified output signal will be generated for any value of the signal represented by this "X"). Please note that the (shown below) produces a default output of 0. The override principle is enabled by the translation code address inputs, all 101, and is illustrated in the last three entries of the table of FIG. The last two entries in the table of FIG. 5 are mutually exclusive; this is the instruction input 302
(i.e., signal I1 from instruction register 48 of FIGS. 1 and 2) and yields outputs of 10 and 01, respectively. The third input from the end of the table of FIG. 5 is a function of command input 302. When input 302 is given, this input is one of the last two inputs.
Selected together with one. The resulting output is the logical sum of the selected words, ie in this case 10's or 11's.

The ideas illustrated in the examples above can be applied to many different processing systems with the same effect. It will be apparent to those skilled in the art that numerous modifications may be made without departing from the invention. It is therefore intended that the appended claims cover all such modifications that fall within the scope of the invention.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microprogram control memory used to carry out the present invention, and FIG. 2 is a block diagram of one embodiment of the present invention.
PLA structures and ROM structures are merged alternately,
FIG. 3 is a diagram illustrating a combined control memory of ROM and PLA, showing that a single column bit line of a PLA can be arranged with a corresponding column bit line of a ROM. 4a and 4b are diagrams showing schematically the symbols used as gates in FIG. 3, and FIG. 4 is a table showing a condensed code of the control memory shown in FIG. 3; 2...PLA structure, 4...ROM structure, 6...
...Next address register, 8...Instruction register, 16...ROM storage array, 18...
ROM row decoder, 24...PLA OR gate array, 26...PLA AND gate array,
28... multiplexer, 40... column multiplexer, 42... AND gate/decoder combination,
44...Memory array.

Claims (1)

Claims: 1. Processing means operative in response to a control word from a controller in a data processing device to generate a control word containing a respective next address portion in response to an instruction and a previous control. A control device for use in a processor comprising: (a) instruction storage means for receiving and storing instructions; (b) next address portion storage means for receiving and storing a next address portion; (c) (i) generating a control word as an output signal in response to the contents of said instruction storage means and the contents of said next address portion storage means and responsive only to the contents of said next address portion storage means; (ii) programmable logic array means connected to said instruction storage means and said next address portion storage means to generate a control word as an output signal; (d) read-only memory means connected to said next address portion storage means for responsively generating a control word as an output signal; (d) said next address portion storage means; said programmable logic array means and said read-only memory means for selectively transmitting control word output signals from said programmable logic array means or said read-only memory means to said processing means in response to the contents of said programmable logic array means and said read-only memory means; A control device comprising: selective transmission means connected to the memory means; 2. The selective transmission means is further coupled to the next address portion storage means for transmitting the next address portion of the selected control word output signal to the next address portion storage means. The control device according to item 1. 3. said read only memory means having an address signal input connected to said next address portion storage means for generating a control word output signal in response to the contents of said next address portion storage means; Claim 1 containing
Control device as described in section. 4 (a) said programmable logic array means: (i) connected to said selective transmission means each having one
(ii) a first memory means having a plurality of addressable memory locations for storing one control word; storage means, first decoder means connected to the instruction storage means and the next address partial storage means and for coupling the generated address to the first storage means; the first storage means includes coupling means for coupling the contents of the addressed memory location to the selective transmission means; (b) the read-only memory means: (i) the selective transmission means; connected to 1 each
(ii) said second storage means and said next address partial storage means for generating an address from the contents of said next address partial storage means; second decoding means connected to the next address partial storage means and for coupling the generated address to said second storage means, said second storage means being connected to the next address partial storage means; 2. A control device as claimed in claim 1, further comprising coupling means for coupling the contents of a storage location to said selective transmission means. 5 (a) said first decoder means having inputs connected to said instruction storage means and said next address part storage means, respectively, and an output connected to one storage location of said first storage means; and generating an output signal in response to the contents of the instruction storage means and the next address portion;
a plurality of first coincidence gate means for enabling said programmable logic array means to couple the contents of a storage location of a first storage means to said selective transmission means to which said output is connected; (b) said second decoder means each having an input connected to said next address part storage means and an output connected to one storage location of said second storage means; , generating an output signal in response to the contents of said next address portion storage means, said second address portion storage means for coupling the contents of a storage location of said second storage means to said selective transmission means to which said output is connected; 5. The control device according to claim 4, further comprising a plurality of second coincidence gate means for enabling the storage means of the second coincidence gate. 6. Each of the first coincidence gate means and the second coincidence gate means has at least one
a control line having one circuit element and an output, each said circuit element being energized by one stage of said instruction storage means or said next address partial storage means; 6. The control device of claim 5, wherein the line transmits an output signal only when all circuit elements connected to the line are energized. 7. At least one of said first coincidence gate means and one of said second coincidence gate means share the same control line, and said selective transmission means transmits a control word from said read-only memory means. When transmitting an output signal, all circuit elements associated with the circuit elements of said first coin idence gate means are selectively energized, and said selective transmission means also Claim 1, further comprising means for selectively energizing all circuit elements associated with the circuit elements of said second coincidence gate means when transmitting a control word output signal from said means. The control device according to item 6. 8. Each of the first storage means and the second storage means each has a plurality of control lines each having at least one circuit element connected to the line and an output connected to the selective transmission means. each of the circuit elements of the first storage means having a respective input connected to a control line of the first coincidence gate means, and each of the circuit elements of the first storage means having a respective input connected to a control line of the first coincidence gate means; Each of the elements has a respective input connected to a control line of said second coincidence gate means, each control line of said first storage means each having at least one circuit element connected thereto. 7. A control device according to claim 6, which transmits an output signal when activated.