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JPH01161840A - Flexible printed wiring board - Google Patents

Flexible printed wiring board

Info

Publication number
JPH01161840A
JPH01161840A JP62320303A JP32030387A JPH01161840A JP H01161840 A JPH01161840 A JP H01161840A JP 62320303 A JP62320303 A JP 62320303A JP 32030387 A JP32030387 A JP 32030387A JP H01161840 A JPH01161840 A JP H01161840A
Authority
JP
Japan
Prior art keywords
chip
substrate
fpc board
holes
flexible printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62320303A
Other languages
Japanese (ja)
Inventor
Masahiro Kaizu
雅洋 海津
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujikura Ltd
Original Assignee
Fujikura Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujikura Ltd filed Critical Fujikura Ltd
Priority to JP62320303A priority Critical patent/JPH01161840A/en
Publication of JPH01161840A publication Critical patent/JPH01161840A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the occurrence of cracks in the surface of boundary of a substrate and sealing resin and the deformation of the substrate itself, and to make it possible to use a through hole for positioning and the like when a bonding work is conducted by a method wherein a through hole is provided between the electrode group to be wire-bonded to an IC chip and also on the circumference of the position where the IC is mounted. CONSTITUTION:Circuit electrodes 3,... are composed of a plurality of electrode groups 3A-3D. These electrode groups 3A-3D are provided on the circumference of the position 16 where an IC chip 5 is mounted in such a manner that they are extending towards the outside, and the circuit electrodes 3,... are wire-bonded to the IC chip 5. Also the through holes 15,..., penetrating a substrate 4 in its thickness direction, are formed respectively on the circumference of the mounting position 16 of the IC chip 5 and also between the electrode groups 3A-3D. The leg parts 17A,... of the guide frame 17, made of a hard material, are inserted into the through holes 15,..., they are adhered to the substrate 4, the substrate itself is supported by the guide frame 17 with moderate tension, and the distortion and the deformation of the substrate can be prevented. Also, the generation of cracks on the boundary surface of the substrate 4 and the sealed resin 18 of the IC chip 5 can be prevented.

Description

【発明の詳細な説明】 「産業上の利用分野」 この発明は、ICチップが基板上に直接グイポンディン
グされて、各種電子回路等が形成されるフレキシブルプ
リント配線板に関するものである。
DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a flexible printed wiring board on which various electronic circuits and the like are formed by directly bonding an IC chip onto a substrate.

「従来の技術」 近年、実装回路部品の小を軽量化、ローコスト化を目的
として、ICチップを直接配線基板上に実装する技術が
特に硬質配線板において一般化してきており、同様の目
的により、フレキシブルプリント配線板(以下、FPC
基板と略記する)への適用も頻繁に行なわれている。
"Prior Art" In recent years, the technology of mounting IC chips directly onto wiring boards has become popular, especially for hard wiring boards, with the aim of reducing the size, weight, and cost of mounted circuit components. Flexible printed circuit board (hereinafter referred to as FPC)
It is also frequently applied to substrates (abbreviated as “substrates”).

ところで、上記FPC基板は一般的には数十から数百ミ
クロンの柔軟なベースフィルムに、接着剤層を介在させ
て数十ミクロンの導電板(後述する回路電極に相当)を
積層した構造となっているので、硬質配線板に対するI
Cチップの実装と同様の方法でICチップの実装を行っ
たのでは、FPC基板そのものに反り、たわみなどが発
生し、接続信頼性の面で問題がある。
By the way, the above-mentioned FPC board generally has a structure in which conductive plates (corresponding to circuit electrodes described below) of several tens of microns are laminated on a flexible base film of several tens to several hundred microns with an adhesive layer interposed. Therefore, the I
If the IC chip is mounted using the same method as the C chip, the FPC board itself will warp or bend, causing problems in terms of connection reliability.

その為、FPC基板に直接実装されたICチップは、熱
硬化性の封止樹脂によって封止されるのが一般的であり
、この封止樹脂によりICチップの耐環境性を向上させ
るとともに、硬化した樹脂の剛性によって、ICチップ
の実装部分におけるFPC基板の反り等の変形を抑制す
る効果がある。
Therefore, IC chips mounted directly on FPC boards are generally sealed with a thermosetting sealing resin, which improves the environmental resistance of the IC chip and hardens it. The rigidity of the resin has the effect of suppressing deformation such as warping of the FPC board in the area where the IC chip is mounted.

このようなFPC基板に対するICチップの実装形態を
第7図〜第9図の断面図にそれぞれ示す(構成が共通す
る部分には同一符号を付す)。
The mounting form of an IC chip on such an FPC board is shown in the cross-sectional views of FIGS. 7 to 9, respectively (the same reference numerals are given to the parts having the same structure).

第7図に示す実装形態は最も標準的なものであって、上
述したようにベースフィルム1、接着剤層2、回路電極
(導電板)3によって構成されてなるFPC基板4の回
路電極3にICチップ5をワイヤボンディングしくボン
ディングワイヤを符号5A・5Aで示す)、更に、この
ICチップ5を熱硬化性樹脂6によりドロップコーティ
ングしたものである。
The mounting form shown in FIG. 7 is the most standard one, and as described above, the circuit electrode 3 of the FPC board 4 is composed of the base film 1, the adhesive layer 2, and the circuit electrode (conductive plate) 3. The IC chip 5 is wire-bonded (bonding wires are indicated by symbols 5A and 5A), and the IC chip 5 is further drop-coated with a thermosetting resin 6.

また、第8図に示す実装形態は、符号7・7で示すよう
なガイド枠をFPC基板4に接着した上で(接着層を7
A・7Aで示す)、これらガイド枠7・7内に、ICチ
ップ5を封止する熱硬化性樹脂8を注入したものであり
、このガイド枠7・7は、ICチップ5を封止した熱硬
化性樹脂8の高さが一定となるように保持するものであ
る。
In addition, in the mounting form shown in FIG.
7A), a thermosetting resin 8 for sealing the IC chip 5 is injected into these guide frames 7, 7; This is to maintain the height of the thermosetting resin 8 to be constant.

「発明が解決しようとする問題点」 ところで、第7図に示すような樹脂6だけによる封止の
場合、樹脂6とFPC基板4との熱膨張率の差などによ
り、樹脂6とFPC基板4との間の境界面にストレスが
集中して該境界面にクラックを発生させたり、また、樹
脂6の硬化の際にFPC基板4を変形させ、しわなどを
発生させる場合がある。
"Problems to be Solved by the Invention" By the way, in the case of sealing using only the resin 6 as shown in FIG. 7, due to the difference in thermal expansion coefficient between the resin 6 and the FPC board 4, Stress may concentrate on the interface between the FPC board 4 and cause cracks to occur at the interface, or the FPC board 4 may be deformed during hardening of the resin 6, causing wrinkles or the like.

また、第8図に示すような、FPC基板4に接着剤で固
定されたガイド枠7・7を使用した樹脂8による封止の
場合には、樹脂8がFPC基板4上に均一の厚さで注入
されているので、第7図に示すもの程ではないが、樹脂
8とFPC基板4との熱膨張率の差などにより、同様に
、樹脂8とFPC基板4との境界面にクラックを誘発す
ることがある。
Furthermore, in the case of sealing with resin 8 using guide frames 7 fixed to FPC board 4 with adhesive as shown in FIG. Similarly, cracks may occur at the interface between the resin 8 and the FPC board 4 due to the difference in thermal expansion coefficient between the resin 8 and the FPC board 4, although not as much as shown in FIG. 7. It may be triggered.

また、前記ガイド枠7・7をFPC基板4に接着する際
には、これらガイド枠7・7をFPC基板4に押圧する
ので、該FPC基板4にゆがみ、しわ等が発生し易く、
その結果、FPC基板4に接着したICチップ5の下面
、該ICチップ5に接続される回路電極3が同一平面上
に位置しなくなり、FPC基板4とICチップ5との接
続そのものの信頼性を低下させることになる。
Furthermore, when the guide frames 7, 7 are bonded to the FPC board 4, since these guide frames 7, 7 are pressed against the FPC board 4, the FPC board 4 is likely to be distorted, wrinkled, etc.
As a result, the lower surface of the IC chip 5 adhered to the FPC board 4 and the circuit electrode 3 connected to the IC chip 5 are no longer located on the same plane, which reduces the reliability of the connection between the FPC board 4 and the IC chip 5 itself. It will lower the

一方、上述したような境界面のクラック、及びFPC基
板自体の変形等を回避する手段として、第9図に示すよ
うに、FPC基板4の背面に補強板9を接着することが
行なわれているが、このような補強板9が接着されたF
PC基板4は、第7図、第8図に示すものと比較して全
体の厚さが大きくなり、これによって、本来の目的であ
るFPCを使用した場合の利点である軽薄化を一部犠牲
にせざるを得ないという問題があった。
On the other hand, as a means to avoid cracks at the interface and deformation of the FPC board itself as described above, a reinforcing plate 9 is bonded to the back surface of the FPC board 4, as shown in FIG. However, F to which such a reinforcing plate 9 is glued
The overall thickness of the PC board 4 is larger than that shown in FIGS. 7 and 8, and as a result, the original purpose of using an FPC, which is an advantage of thinning and thinning, is partially sacrificed. The problem was that it had to be done.

「問題点を解決するための手段」 この発明は、上記の事情に鑑みてなされたものであって
、FPC基板とICチップを封止した樹脂との境界面に
発生するストレスから該境界面にクラックが生ずること
を回避する、FPC基板自体の変形を回避する、ICチ
ップをFPC基板の回路電極にワイヤボンディングする
際の位置決め等の種々の用途に適用される貫通孔を有す
るフレキシブルプリント配線基板を得ることを目的とし
、この目的を達成するために、FPC基板におけるIC
チップの実装位置の周囲に、該ICチップにワイヤボン
ディングされる複数の電極群を外方に延びるように設け
、更に、これら電極群の間で、かつICチップの実装位
置の周囲に、前記FPC基板を厚さ方向に貫通する貫通
孔を設けるようにしている。
"Means for Solving the Problems" This invention has been made in view of the above circumstances. Flexible printed wiring boards with through holes are used for various purposes such as avoiding cracks, avoiding deformation of the FPC board itself, and positioning when wire bonding IC chips to circuit electrodes on the FPC board. In order to achieve this purpose, the IC on the FPC board is
A plurality of electrode groups to be wire-bonded to the IC chip are provided around the mounting position of the chip so as to extend outward, and further, between these electrode groups and around the mounting position of the IC chip, the FPC A through hole is provided that penetrates the substrate in the thickness direction.

「実施例」 この発明の実施例を第1図〜第6図を参照して説明する
"Embodiment" An embodiment of the present invention will be described with reference to FIGS. 1 to 6.

なお、これらの図に示すフレキシブルプリント配線板は
、従来の技術で示したフレキシブルプリント配線板と基
本構成が同一であるので、構成を共通とする部分に同一
符号を付して説明を簡略化する。 ゛ 上述した回路電極3・3・・は、第2図を参照して判る
ように4つ(複数)の電極群3A〜3Dによって構成さ
れている。これら電極群3A〜3Dは、ICチップ5が
実装される位置(符号16で示す実装位置)の周囲に、
外方に延びるように設けられたものであって、これら電
極群3A〜3Dにおける各電極3・3・・は、実装位置
16に実装されたICチップ5に対してそれぞれワイヤ
ボンディングされるようになっている。
The flexible printed wiring boards shown in these figures have the same basic configuration as the flexible printed wiring boards shown in the conventional technology, so the same reference numerals are given to the parts having the same configuration to simplify the explanation. . ``The circuit electrodes 3, 3, . . . described above are constituted by four (plural) electrode groups 3A to 3D, as can be seen with reference to FIG. These electrode groups 3A to 3D are arranged around the position where the IC chip 5 is mounted (the mounting position indicated by the reference numeral 16).
These electrodes 3, 3, etc. in the electrode groups 3A to 3D are provided so as to extend outward, and are wire-bonded to the IC chip 5 mounted at the mounting position 16. It has become.

また、第1図〜第6図に符号15・15・・で示すもの
は、FPC基板4をその厚さ方向に貫通した貫通孔であ
って、これら貫通孔15・15・・は、ICチップ5が
実装位置16の周囲であり、かつ、前記電極群3A〜3
D間の四箇所にそれぞれ形成されている(第2図・第3
図参照)。
1 to 6 are through-holes that penetrate the FPC board 4 in its thickness direction, and these through-holes 15, 15, etc. are used for IC chips. 5 is around the mounting position 16, and the electrode groups 3A to 3
They are formed at four locations between D (Figures 2 and 3).
(see figure).

なお、前記貫通孔15−15・・は、電極群の数に応じ
て設けられ、また、それら個々の形状、大きさ等は任意
である。
The through holes 15-15 are provided in accordance with the number of electrode groups, and their individual shapes, sizes, etc. are arbitrary.

これら貫通孔15・15・・の利用法について説明する
The usage of these through holes 15, 15, . . . will be explained.

(1)  ワイヤボンディングを行う際の基準位置とし
て利用。
(1) Used as a reference position when performing wire bonding.

前記貫通孔15・15・・を利用して、前記ICチップ
5と基板4上の回路電極3・3・・とをワイヤボンディ
ングする際の位置決め、つまり、前記貫通孔15・15
・・をガイドとして、ポンディングワイヤを供給するキ
ャピラリ(ノズル)の位置決めがなされ、これによって
、個々のICチップにおけるワイヤボンディングを正確
に行なうことができるという効果がある。
Positioning when wire bonding the IC chip 5 and the circuit electrodes 3, 3, etc. on the substrate 4 using the through holes 15, 15, . . .
... is used as a guide to position the capillary (nozzle) that supplies the bonding wire, and this has the effect that wire bonding can be performed accurately on each IC chip.

(2)樹脂封止用のガイド枠を取り付ける孔として利用
(2) Used as a hole to attach a guide frame for resin sealing.

第3図〜第5図に示すように、符号17で示すものは、
ICチップ5を封止する熱硬化性樹脂18を注入した場
合において、この樹脂18の高さが略一定となるように
保持する、硬質材で形成されたガイド枠(枠体)である
(第5図参照)。
As shown in FIGS. 3 to 5, what is indicated by the reference numeral 17 is
It is a guide frame (frame body) made of a hard material that holds the thermosetting resin 18 that seals the IC chip 5 so that the height of the resin 18 is approximately constant when it is injected. (See Figure 5).

−このガイド枠17は、その下部に四箇所の脚部17A
 −17A・・を有するものであって、これら脚部17
A・17A・・が、前記FPC基板4の貫通孔15・1
5・・にそれぞれ挿入され、更に接着されるようになっ
ている(第3図及び第4図参照)。そして、これら前記
FPC基板4に対するガイド枠17の挿入接着によって
、FPC基板4自体がガイド枠17に支持されるように
なっている(第5図参照)。
- This guide frame 17 has four legs 17A at its lower part.
-17A..., and these leg portions 17
A.17A... is the through hole 15.1 of the FPC board 4.
5... and are further bonded (see Figures 3 and 4). By inserting and adhering the guide frame 17 to the FPC board 4, the FPC board 4 itself is supported by the guide frame 17 (see FIG. 5).

なお、前記ガイド枠17の脚部17A・17A・・の横
断面形状と、FPC基板4の貫通孔15・15・・の横
断面形状とは略同−であり、前記ガイド枠17の脚部1
7A・17A・・とFPC基板4の貫通孔15・15・
・との相互間隔(各電極3A〜3Dを間に挾む相互間隔
)も略同−に設定されている。
Note that the cross-sectional shape of the leg portions 17A, 17A, etc. of the guide frame 17 and the cross-sectional shape of the through holes 15, 15, etc. of the FPC board 4 are approximately the same, and the leg portions of the guide frame 17 are substantially the same. 1
7A, 17A... and through holes 15, 15, of FPC board 4
The mutual spacing between and (the mutual spacing between the electrodes 3A to 3D) is also set to be approximately the same.

そして、上記のような貫通孔15・15・・に、硬質材
で形成されたガイド枠17の脚部17A・17A・・を
挿入し、更に、これら脚部17A・17A・・をFPC
基板4に接着することにより、FPC基板4自体がガイ
ド枠17に適度の張力を以て支持され、これによって、
FPC基板4が歪み、変形することが防止される。
Then, the legs 17A, 17A, etc. of the guide frame 17 formed of a hard material are inserted into the through holes 15, 15, etc., as described above, and the legs 17A, 17A,...
By adhering to the board 4, the FPC board 4 itself is supported by the guide frame 17 with appropriate tension, and thereby,
The FPC board 4 is prevented from being distorted and deformed.

また、上述したように、前記貫通孔15・15・・に挿
入接着された硬質のガイド枠17によって、FPC基板
4自体がガイド枠17に適度の張力を以て支持されるの
で、FPC基板4とICチップ5を封止した樹脂18と
の境界面に発生するストレスがガイド枠17に加わり、
これによって、FPC基板4とICチップ5を封止した
樹脂18との境界面にクラックが生じることが防止され
る。
Furthermore, as described above, the FPC board 4 itself is supported by the guide frame 17 with appropriate tension by the hard guide frame 17 inserted into the through holes 15, 15, etc., so that the FPC board 4 and the IC The stress generated at the interface with the resin 18 sealing the chip 5 is applied to the guide frame 17,
This prevents cracks from occurring at the interface between the FPC board 4 and the resin 18 that seals the IC chip 5.

(3)パッケージ部品を装着する孔として利用。(3) Used as a hole for mounting package parts.

第6図に示すように、貫通孔15・15・・に挿入され
る脚部20A・20A・・を下部に有する上側モールド
部品20と、この上側モールド部品20の脚部20A・
20A・・の下端が挿入されて接着される凹部21A・
2LA・・を有する下側モールド部品21とから構成さ
れるパッケージ部品22によって、前記FPC基板4上
のICチップ5を気密封止することができる。
As shown in FIG. 6, there is an upper molded part 20 having legs 20A, 20A, etc. at the lower part thereof, which are inserted into the through holes 15, 15, and the legs 20A, 20A, etc. of this upper molded part 20.
Recess 21A into which the lower end of 20A is inserted and glued.
The IC chip 5 on the FPC board 4 can be hermetically sealed by the package component 22 composed of the lower mold component 21 and the lower mold component 21 having 2LA.

つまり、前記貫通孔15・15・・を利用して、パッケ
ージ部品22がFPC基板4に装着され、これによって
、前記ICチップ5を気密封止することができる。
That is, the package component 22 is attached to the FPC board 4 using the through holes 15, 15, . . . , and thereby the IC chip 5 can be hermetically sealed.

なお、前記貫通孔15・15・・は、ICチップ5が実
装される位置(符号16で示す実装位置)の周囲に設け
られたものであるので、該ICチップ5を中央に位置さ
せた状態で、前記パッケージ部品22による気密封止を
行うことができる。
Note that the through holes 15, 15, etc. are provided around the position where the IC chip 5 is mounted (the mounting position indicated by the reference numeral 16), so that the IC chip 5 is placed in the center. Then, the package component 22 can perform airtight sealing.

(4)上記(1)〜(3)以外の利用。(4) Uses other than those listed in (1) to (3) above.

なお、前記FPC基板4の貫通孔15・15・・は、上
述した(1)〜(3)以外に、前記FPC基板4にIC
チップ5を接着する際に配置されるワークステージの位
置決めガイド孔として利用される。
In addition to the above-mentioned (1) to (3), the through holes 15, 15, . . .
It is used as a positioning guide hole for a work stage placed when bonding the chip 5.

「発明の効果」 以上詳細に説明したように、この発明によれば、ICチ
ップにワイヤボンディングされる電極群の間で、かつ該
ICチップが実装される位置の周囲に貫通孔が設けられ
ているので、これら貫通孔を、以下に示すような種々の
用途に利用することができる。
"Effects of the Invention" As explained in detail above, according to the present invention, a through hole is provided between the electrode groups wire-bonded to the IC chip and around the position where the IC chip is mounted. Therefore, these through holes can be used for various purposes as shown below.

例えば、これら貫通孔を利用して、前記ICチップと基
板上の電極群とをワイヤボンディングする際の位置決め
、つまりポンディングワイヤを供給するキャピラリ(ノ
ズル)の位置決めがなされ、また、これら貫通孔に、基
板を支持する硬質材の枠体を取り付けることによって、
FPC基板とICチップを封止した樹脂との境界面に発
生する歪を枠体に転移させ、これによって、FPC基板
と樹脂との境界面のクラックを防止でき、かつ、前記基
板自体の変形をも防ぐことができる。
For example, these through holes are used to position the IC chip and the electrode group on the substrate when wire bonding, that is, to position the capillary (nozzle) that supplies the bonding wire. , by attaching a rigid frame to support the board,
The strain generated at the interface between the FPC board and the resin encapsulating the IC chip is transferred to the frame, thereby preventing cracks at the interface between the FPC board and the resin and preventing deformation of the board itself. can also be prevented.

また更に、これら貫通孔を介して、基板の両面から一対
のモールド部品を連結し、これによって、前記ICチッ
プを例えば中央に位置した状態で気密封止することがで
きる等、これら貫通孔を種々の用途に利用することがで
きるという効果が得られる。
Furthermore, these through holes can be used in various ways, such as connecting a pair of molded parts from both sides of the substrate through these through holes, thereby making it possible to hermetically seal the IC chip, for example, in a centrally located state. The effect is that it can be used for various purposes.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図〜第6図は本発明の実施例を示す図であって、第
1図は第2図の正断面図、第2図は平面図、第3図及び
第4図はガイド枠を取り付ける際の正断面図と斜視図、
第5図は第3図及び第4図に示すガイド枠をFPC基板
に取り付けた状態の正断面図、第6図はFPC基板にパ
ッケージ部品を取り付ける際の正断面図、$71!I−
@9図は従来の問題点を説明するための正断面図である
。 3・・・・・・回路電極(3A〜3D・旧・・電極群)
、4・・・・・・FPC基板く基板)、5・・・・・弓
Cチップ、15・・・・・・貫通孔、16・・・・・・
ICチップの実装位置、17・・・・・・ガイド枠(枠
体)、17A・・・・・・脚部、18・・・・・・熱硬
化性樹脂(樹脂)、2o・21・・・・・・モールド部
品。
1 to 6 are diagrams showing embodiments of the present invention, in which FIG. 1 is a front sectional view of FIG. 2, FIG. 2 is a plan view, and FIGS. 3 and 4 show a guide frame. Front sectional view and perspective view when installing,
Fig. 5 is a front sectional view of the guide frame shown in Figs. 3 and 4 attached to the FPC board, and Fig. 6 is a front sectional view of the package component being attached to the FPC board. $71! I-
@9 Figure is a front sectional view for explaining the conventional problems. 3...Circuit electrodes (3A to 3D, old...electrode group)
, 4... FPC board), 5... Bow C chip, 15... Through hole, 16...
IC chip mounting position, 17...Guide frame (frame body), 17A...Legs, 18...Thermosetting resin (resin), 2o, 21... ...Mold parts.

Claims (3)

【特許請求の範囲】[Claims] (1)ICチップ(5)が基板(4)に実装されるフレ
キシブルプリント配線板において、 前記基板におけるICチップの実装位置(16)の周囲
には、該ICチップにワイヤボンディングされる複数の
電極群(3A〜3D)が外方に延びるように設けられ、 これら電極群の間にあり、かつ、ICチップの実装位置
の周囲には、前記基板を厚さ方向に貫通する貫通孔(1
5)が形成されていることを特徴とするフレキシブルプ
リント配線板。
(1) In a flexible printed wiring board in which an IC chip (5) is mounted on a substrate (4), a plurality of electrodes are wire-bonded to the IC chip around the mounting position (16) of the IC chip on the substrate. groups (3A to 3D) are provided to extend outward, and between these electrode groups and around the mounting position of the IC chip, there are through holes (1) that penetrate the substrate in the thickness direction.
5) A flexible printed wiring board comprising:
(2)前記貫通孔には枠体(17)の脚部(17A)が
挿入接着され、また、該枠体の内部には、ワイヤボンデ
ィングされたICチップを封止する熱硬化性樹脂(18
)が注入されることを特徴とする特許請求の範囲第1項
記載のフレキシブルプリント配線板。
(2) The legs (17A) of the frame (17) are inserted and bonded into the through holes, and the thermosetting resin (18) seals the wire-bonded IC chip inside the frame.
) is injected into the flexible printed wiring board according to claim 1.
(3)前記基板には、前記貫通孔を通じてICチップを
気密封止するモールド部品(20・21)が一体に取り
付けられることを特徴とする特許請求の範囲第1項記載
のフレキシブルプリント配線板。
(3) The flexible printed wiring board according to claim 1, wherein mold parts (20, 21) for hermetically sealing the IC chip through the through hole are integrally attached to the substrate.
JP62320303A 1987-12-18 1987-12-18 Flexible printed wiring board Pending JPH01161840A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62320303A JPH01161840A (en) 1987-12-18 1987-12-18 Flexible printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62320303A JPH01161840A (en) 1987-12-18 1987-12-18 Flexible printed wiring board

Publications (1)

Publication Number Publication Date
JPH01161840A true JPH01161840A (en) 1989-06-26

Family

ID=18119991

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62320303A Pending JPH01161840A (en) 1987-12-18 1987-12-18 Flexible printed wiring board

Country Status (1)

Country Link
JP (1) JPH01161840A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5386342A (en) * 1992-01-30 1995-01-31 Lsi Logic Corporation Rigid backplane formed from a moisture resistant insulative material used to protect a semiconductor device
US5557252A (en) * 1993-05-13 1996-09-17 Mitsubishi Denki Kabushiki Kaisha Thick film circuit board and method of manufacturing the same
US5831836A (en) * 1992-01-30 1998-11-03 Lsi Logic Power plane for semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5386342A (en) * 1992-01-30 1995-01-31 Lsi Logic Corporation Rigid backplane formed from a moisture resistant insulative material used to protect a semiconductor device
US5831836A (en) * 1992-01-30 1998-11-03 Lsi Logic Power plane for semiconductor device
US5557252A (en) * 1993-05-13 1996-09-17 Mitsubishi Denki Kabushiki Kaisha Thick film circuit board and method of manufacturing the same

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