JPH01143351A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To form a transfer transistor having high storage capacity and high reliability by strengthening breakdown strength and flatness of a gate electrode, a bit line and a storage electrode. CONSTITUTION:An Si substrate 11 is selectively locally oxidized to form a field oxide film 12, and N<+> type impurity diffused layers 13, 14 are formed by thermal ion diffusing as the source, drain of a transfer transistor T1. A storage electrode 22a formed on a polysilicon film containing impurity ions of a desired thickness is heat treated thereby to form a dielectric film 23. SiO2 films 15a, 16, 19a, 20 or Si3N4 film 20 are formed as thick insulating films on the sidewalls of gate electrodes WL3, WL4 and a bit line BL1. Thus, even if the electrode 22a is stereoscopically laminated as a result of miniaturization, the breakdown strength and flatness of the electrodes WL3, WL4 and the line BL1 can be strengthened.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a semiconductor memory device and a method for manufacturing the same, particularly a highly integrated, high-performance dynamic random access memory (DR).
AM) Regarding the structure of the cell and its formation method, strengthen the insulation and flatten the sidewalls of the gate electrode and bit line, increase the area of the storage electrodes of the memory cell by stacking them in the same plane, and increase the storage capacity. The device is a semiconductor memory having a transfer transistor and a bit line consisting of an impurity diffusion layer, a gate electrode, and a storage capacitor formed on the semiconductor substrate, consisting of a storage electrode, a dielectric film, and a counter electrode formed on the semiconductor substrate. In the device, the insulating film on the side wall of the gate electrode or the bit line has an insulating structure with a thickness thicker than the insulating film on the upper part of the gate electrode and the bit line, and the manufacturing method thereof is applied to a semiconductor substrate in a field. forming an insulating film, an impurity diffusion layer, and a gate electrode; forming a first insulating film on the semiconductor substrate; and anisotropically etching the semiconductor substrate on which the first insulating film is formed. , leaving a first insulating film on the sidewalls of the gate electrode, forming a second insulating film on the semiconductor substrate on which the first insulating film remains, and then selectively forming the second insulating film. removing the impurity diffusion layer to expose the impurity diffusion layer and providing an opening; and forming a bit line by selectively forming a desired first conductive film on the semiconductor substrate provided with the opening. , forming a third insulating film on the semiconductor substrate on which the bit line is formed; and anisotropically etching the semiconductor substrate on which the third insulating film is formed to form a third insulating film on the sidewall of the bit line. a step of leaving a film; a step of forming a fourth insulating film on the entire surface of the semiconductor substrate with the third insulating film remaining; and selectively removing the fourth insulating film and the second insulating film. The method includes the steps of exposing the impurity diffusion layer and providing an opening, and selectively forming a second conductor film on the semiconductor substrate provided with the opening.

[Industrial application field]

The present invention relates to a semiconductor memory word jl and a method for manufacturing the same, and more particularly, to a structure of a highly integrated, high-performance dynamic random access memory (DRAM) cell and a method for forming the same.

[Conventional technology]

FIG. 3 is an explanatory diagram of a conventional DRAM cell.

FIG. 2(a) is an electrical circuit diagram of a DRAM cell.

In the figure, T is a transfer transistor composed of a MOS transistor or the like that transfers data (charge), C is a storage capacitor that accumulates charge, WL is a word line, and BL is a bit line. Note that 6 is a storage electrode, 7 is a dielectric film, and 8 is a counter electrode.

FIG. 2B is a cross-sectional view showing the DRAM cell structure. In the figure, 1 is an St substrate such as a P-type epitaxial layer, 2 is
is a field oxide film (
3.4 is an impurity diffusion layer formed by diffusing As'' ions, etc., and is the source or drain of the transfer transistor T. 5 is an insulating film that insulates the word line WL. , CVD oxide film (SiJn film), etc.

Note that a portion A indicated by a broken line circle in FIG. 2B is a thin film portion where an insulating film becomes thinner and its dielectric strength decreases as semiconductor elements become smaller and more highly integrated, causing short circuits and malfunctions. Reference numeral 6 denotes an electrode formed by doping a poly-Si film with impurity ions, and is a storage electrode constituting a storage capacitor C.

7 is a dielectric film formed of an insulating film such as a SiO□ film or a Si3N4 film. Reference numeral 8 denotes an electrode formed by doping impurity ions into a poly-Si film, and is a counter electrode constituting the storage capacitor C. 9 is an insulating film that insulates the counter electrode 8, and is a PSG film or the like.

10 is a contact hole for bit line Bl-.

Note that WL is a gate electrode of a transfer transistor T formed of a poly-Si film or the like, and is a word line. Further, BL is a bit line formed of a poly-Si film or a polycide film doped with impurities.

[Problem that the invention seeks to solve]

However, according to the prior art, as the degree of integration of semiconductor memory devices increases and semiconductor elements become smaller, the area of a DRAM memory cell becomes smaller and smaller. This causes the following problems.

(1) Storage capacitance C of memory cell depending on storage electrode area
becomes less.

(2) As the storage capacitance C decreases, soft errors due to α-ray incidence increase.

(3) The aspect ratio of the bit line BL contact hole becomes large, making pattern formation difficult.

(4) The distance between the separated portions of the bit lines BL is narrow.

(5) There is less margin for positioning the bit line BL and word line WL.

(6) The dielectric strength of the word line WL and bit line BL decreases, causing malfunctions and short circuits.

The present invention was created in view of the problems of the conventional example, and aims to strengthen and flatten the insulation of the side walls of gate electrodes and bit lines, and three-dimensionally increase the area of storage electrodes of memory cells within the same plane. An object of the present invention is to provide a semiconductor memory device and a method for manufacturing the same that make it possible to increase storage capacity.

(Means for Solving the Problems) A semiconductor memory device and a method for manufacturing the same according to an embodiment of the present invention, as shown in FIGS. 1 to 4, include an impurity diffusion layer 13. 14, gate electrode WL3,
A transfer transistor T1 consisting of WL and a bit line BL,
, a storage electrode 22a and a dielectric film 2 formed on the top thereof.
In the semiconductor memory device, the insulating films 15a, 16, 19a, 20 on the side walls of the gate electrodes WL3, WL or the bit line BL are connected to the gate electrodes WL3, WL4 and Bit line BL.

It is characterized by having an insulating structure with a film thickness thicker than the insulating film 16.20 on the upper part of the field insulating film 16.20.
2, impurity diffusion layers 13 and 14, and gate electrodes WL3 and WL
4, forming a first insulating film 15 on the semiconductor substrate 11, and anisotropically etching the semiconductor substrate 11 on which the first insulating film 15 is formed to form the gate electrode. WLff, WL4
forming a second insulating film 16 on the semiconductor substrate 11 on which the first insulating film 15a remains, and then selectively removing the second insulating film 16; a step of removing the impurity diffusion layer 4 to expose the impurity diffusion layer 4 and providing an opening 17; and a step of selectively forming a desired first conductive film 18 on the semiconductor substrate 11 provided with the opening 17; a step of forming a third insulating film 19 on the semiconductor substrate 11 on which the bit line BL is formed; and an anisotropic process on the semiconductor substrate 11 on which the third insulating film 19 is formed The bit line B L is etched.

forming a fourth insulating film 20 on the entire surface of the semiconductor substrate 11 with the third insulating film 19a remaining;
selectively removing the impurity diffusion layer 13 and the second insulating film 16 to expose the impurity diffusion layer 13 and providing an opening 21;
The above object is achieved.

[For production]

According to the semiconductor memory device of the present invention, a thick insulating film is provided on the side walls of the gate electrode and bit line. This makes it possible to further strengthen the dielectric strength and flatness of the gate electrodes and bit lines compared to the prior art even if the storage electrodes are stacked three-dimensionally due to miniaturization.

Further, according to the manufacturing method of the present invention, in the step of insulating the previously formed gate electrodes and bit lines, the first insulating film and the third insulating film are
The insulating film is used to strengthen the insulation on the side walls and to alleviate vertical steps. Therefore, the first and third insulating films are left on the side walls of the gate electrode and bit line by anisotropically etching the first and third insulating films. Therefore, it is possible to make the insulating film of the gate electrode and bit line thick and have a smooth cross section.

This makes it possible to easily form the storage electrode in a subsequent process.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1.2 is an explanatory diagram of a semiconductor memory device and its manufacturing method according to an embodiment of the present invention, and FIG. 1 shows a structural diagram of a DRAM cell according to an embodiment of the present invention.

Figures (a) and (b) are DRAM cell (D cross-sectional views,
The same figure (C) is the top view. In addition, the same figure (a) is a sectional view taken along the arrow AA' in the same figure (c), and the same figure (b) is the 13-B arrow sectional view taken in the same figure (C).

In the figure, 11 is a Si substrate such as an n-type or p-type epitaxial layer, 12 is a field oxide film formed by selectively oxidizing the St substrate 11, and 13.14 is a film formed by thermally diffusing impurity ions such as As'' ions. This is an n' impurity diffusion layer formed by the same method, and is the source and drain of the transfer transistor T1.WL3 and WL are gate electrodes formed of a poly-Si film or the like, and are word lines in the DRAM cell.

16.15a, 20 are word lines (gate electrodes) WL,
, WL4, and an insulating film such as SiO□ film or 5iJ4III. In particular, a 5i02 film 15a is provided on the side wall of each electrode to strengthen the insulation protection of the wiring and to alleviate vertical steps.

In addition, 16.19a and 20 are insulating films for insulating the bit line BL, and similarly to the word lines WLS and WL, a Sing film 19a is provided on the side wall of the bit line BL to strengthen its insulation protection and eliminate vertical steps. It's relaxing. This constitutes the transfer transistor T1.

Note that 22a is a storage electrode formed on a poly-Si film containing impurity ions with a desired thickness. 23 is a dielectric film, which is formed by heat-treating the storage electrode 22a. Further, 24 is a counter electrode formed of a poly-Si film containing impurity ions, and together with the storage electrode 22a and the dielectric film 23, forms a storage capacitor C0.

In addition, in the same figure (C), WL3, WL,
is a word line (gate electrode), and BL shown by a dashed-dotted line is a bit line. Further, 22a shown by a two-dot chain line is a storage electrode, 17 is a bit line contact hole, and 21 is a storage electrode contact hole. These constitute a DRAM cell.

In this way, the SiO□ film L5a is formed as a thick insulating film on the side walls of the gate electrodes WL3 and WL4 and the bit line BL.
16.19a, 20 or Si3N4 film 20 is provided. As a result, even if the storage electrodes 22a are stacked three-dimensionally due to miniaturization, the gate electrodes WL3, WL4 and the bit line BL
It becomes possible to further strengthen the dielectric strength and planarization degree of I compared to the conventional method.

FIG. 2 is a diagram showing the formation process of a DRAM cell according to an embodiment of the present invention, and FIGS.
A forming process according to a cross section taken along the line A-A' in a plan view of the RAM cell is shown, and (a2) to (L) of the same figure similarly show a forming process according to a cross-sectional view taken along the line B-B'.

In the figure, first, S of the p-type or n-type epitaxial layer, etc.
The i-substrate 11 is thermally oxidized by selective LOCOS method or the like to form a field oxide film 12, and then a poly-Si film or the like is selectively patterned on the field oxide film 12 to form gate electrodes WL, WL4. Note that the gate electrode WL
a, WL4 becomes a word line in the DRAM cell.

Next, desired impurity ions such as As'' ions are implanted into the Si substrate 11. After that, heat treatment is performed to form n+ impurity diffusion layers 13.14. It becomes a source and a drain ((al) and (a2) in the same figure).

Next, five gate electrodes WL3 and WL4 are deposited on the O3iO□ film 15 to a thickness of about 1000 ((b1) in the same figure).
z)).

After that, the SiO□ film 1 is etched by anisotropic etching such as the tE method.
The SiO□ film 15a is left on the side walls of the gate electrodes WL3 and WL4 by etching the 5-layer film. Note that CF, 102, for example, is used as the etching gas ((c1) and (c2) in the same figure).
).

Next, the gate electrode WL with the SiO□ film 15a left on the side wall
3. WL4 is insulated on the 16 O3iO□ films to a thickness of about 1000, and then an opening is formed on the 16 SiO□ film by anisotropic etching such as 6E method using a resist film (not shown) as a mask. form 17. Note that the opening 17 becomes a bit line contact ball ((d1), (dZ
)).

Further, a poly-Si film 1 containing O3 pure ions with a film thickness of about 1000 is applied to the entire surface of the Si substrate 11 in which the opening 17 is provided.
8 is formed by a low pressure CVD method or the like, and patterned by an RIE method or the like using a resist film (not shown) as a mask.

Note that the patterned poly-Si film 18 becomes the bit line BL in the transfer transistor T1 ((e1) in the same figure).
, (ez)).

Next, an O3iO□ film 19 with a thickness of about 1000 layers is deposited on the entire surface of the bit line BL by CVD or the like (see (f) in the same figure).
l), (rz)).

After that, SiO□ was formed by anisotropic etching such as RIE method.
The film 19 is dry etched to leave the SiO□ film 19a on the sidewalls of the bit lines BL. Note that CF, 10□ is used as the etching gas ((g1), (gz) in the same figure).
).

Next, the bit line BL with the 5iOz film 19a left on the sidewall
' is insulated by an O3iO7 film or Si3N film 20 with a thickness of about 1000 ((hl) and (hZ) in the same figure).

Furthermore, using a resist film (not shown) as a mask, 5i02
Films 16 and 20 are selectively removed to form n゛ impurity diffusion layer 1.
3 is exposed and an opening 21 is provided. Note that the opening 21 becomes a storage electrode contact hole ((i1) and (L) in the same figure).
)).

Next, a poly-Si film 22 containing impurity ions is formed to a desired thickness on the entire surface of the Si substrate 11 provided with the opening 21, and then the poly-Si film 22 is subjected to RIE using a resist film (not shown) as a mask. Patterning is performed by anisotropic etching such as etching. Note that the storage electrode 22a is formed by patterning the bo'JSJjJ22. In addition, CC1 and IO are used as etching gas (see figure (jl)).
, (L)).

After the formation steps shown in (j1) and (j2) in the figure, the storage electrode 22a is heat-treated in the same manner as in the past to form a dielectric film 23 such as a SiO2 film, and a dielectric film 23 containing impurity ions is further formed as the counter electrode 24. A poly-Si film is formed on the entire surface of the dielectric film 23. As a result, a RAM cell as shown in FIGS. 1(a) and 1(b) can be manufactured.

In this way, the previously formed gate electrodes WL3, W
In the insulation process of La and bit line BL, 5i02
The film 15 and the SiO□ film 19 are used to strengthen the insulation of the side walls. Therefore, by anisotropically etching the SiO□ film 15.19 by RIE method or the like, it is possible to leave the 5iOz film 15a and the Sing film 19a on the side walls of the gate electrodes WL3, WL4 and the bit line BL. can. Therefore, the gate electrodes WL, , WL.

It becomes possible to make the insulating film of the bit line BL thick and to have a smooth cross section.

This makes it possible to provide favorable conditions for processes such as anisotropic etching when forming storage electrodes in subsequent steps.

(Effects of the Invention) As described above, according to the present invention, the dielectric strength and degree of planarization between the gate electrode, bit line, and storage electrode can be further strengthened compared to the prior art.

This makes it possible to combine the storage electrodes with a three-dimensional stacked structure with the conventional two to
It becomes possible to form a transfer transistor with storage capacity about three times as large and highly reliable.

Therefore, it becomes possible to manufacture highly integrated and ultra-fine semiconductor devices such as DRAM cells.

[Brief explanation of the drawing]

FIG. 1 is a structural diagram of a DRAM cell according to an embodiment of the present invention, FIG. 2 is a formation process diagram of a DRAM cell according to an embodiment of the present invention, and FIG. 3 is an explanatory diagram of a DRAM cell according to a conventional example. . (Explanation of symbols) T, T,... Transfer transistor, C, C,... Storage capacitor, 1.11... Si substrate (semiconductor substrate), 2.12...
- Field oxide film (SiOx film), 3.13...Drain (impurity diffusion layer), 4.14...Source (impurity diffusion layer), 5, 15. 15 a-3iOz film (first insulating film), 6.22a... Storage electrode, 7.23... Dielectric film, 8.24... Counter electrode, 9... PSG film, 10. ...Bit line contact hole, 16...5i
02 film (second insulating film), 17... opening (bit line contact ball), 18... poly-Si film (first conductor film), 19, 19 a-3iOz film (third insulating film), 20...SiO□ film or 5i3Na film (fourth
(insulating film), 21... opening (storage electrode contact hole), 22... poly-Si film (second conductor film), w
L, WL, ~WL4...Word line (gate electrode) BL
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Claims (2)

[Claims] (1) Impurity diffusion layers (13, 1
4), a transfer transistor (T_1) consisting of gate electrodes (WL_3, WL_4), a bit line (BL_1), a storage electrode (22a) formed on the top thereof, and a dielectric film (2).
3) and a storage capacitor (C_1) consisting of a counter electrode (24)
In a semiconductor memory device having the gate electrode (WL_3, WL_4) or the bit line (
Insulating films (15a, 16, 19a, 2) on the side walls of BL_1)
0) has an insulating structure with a film thickness thicker than the insulating films (16, 20) above the gate electrodes (WL_3, WL_4) and the bit line (BL_1). (2) Field insulating film (12) on the semiconductor substrate (11)
), impurity diffusion layers (13, 14), and gate electrode (WL_
3. WL_4) and the step of forming the semiconductor substrate (
forming a first insulating film (15) on the semiconductor substrate (11) on which the first insulating film (15) is formed;
) is anisotropically etched to form the gate electrode (WL_3
, WL_4), a step of leaving the first insulating film (15a) on the side wall of the semiconductor substrate (15a), and leaving the first insulating film (15a) on the sidewall of the semiconductor substrate (15a).
A second insulating film (16) is formed on the impurity diffusion layer (1), and then the second insulating film (16) is selectively removed.
4) exposing and providing an opening (17); selectively forming a desired first conductor film (18) on the semiconductor substrate (11) provided with the opening (17); A step of forming a bit line (BL_1) and a step of forming the bit line (BL_1).
) on the semiconductor substrate (11) on which the third insulating film (19
) and anisotropically etching the semiconductor substrate (11) on which the third insulating film (19) is formed to form a third insulating film (19a) on the sidewall of the bit line (BL_1).
a step of leaving the third insulating film (19a) on the semiconductor substrate (1);
1) forming a fourth insulating film (20) on the entire surface of the impurity diffusion layer; selectively removing the fourth insulating film (20) and the second insulating film (16); (13) and providing an opening (21); and a step of selectively forming a second conductor film (22) on the semiconductor substrate (11) provided with the opening (21). A method of manufacturing a semiconductor memory device, comprising: