JPH0113143B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for joint use of hardware by a plurality of microprocessors, which simultaneously accesses one piece of hardware connected to the plurality of microprocessors.

(b) Technical background In order for multiple microprocessors to access one hardware at the same time, a microprocessor (hereinafter abbreviated as MPU) with priority usage rights is required.
The other MPUs are temporarily suspended and the corresponding hardware is accessed during this time, but in this case, a certain procedure must be followed to temporarily suspend the other MPUs.

In addition, even after access to the relevant hardware is completed, other users may take certain steps to release the temporary suspension again.
This will release the MPU from suspension.

In devices where one piece of hardware is frequently accessed simultaneously by multiple microprocessors, the above steps are taken each time, which is disadvantageous in terms of operational efficiency, and it is important to implement a more efficient shared usage method. It is requested that

(c) Prior Art The prior art will be explained by taking a printer device as an example and referring to the drawings.

FIG. 1 shows a schematic diagram of a conventional printer device.
The character MPU 4 in the figure is an MPU that controls the character information buffer section 1, and the graphic MPU 5 is an MPU that controls the graphic information buffer section 3.

In addition, the Japanese character pattern generator 6 is for characters.
This is shared by the MPU 4 and the graphics MPU 5.
However, it is assumed that the character MPU 4 has the priority right to use the Japanese character pattern generator 6.

Now, when trying to create an instruction manual containing figures in Japanese, the explanatory text part of the information transferred from the main computer (not shown) is sent to the text information buffer section 1, and the figure part (figure (including explanatory text) is extracted to the graphic information buffer section 3.

The character MPU 4 accesses the Japanese character pattern generator 6 so that the information regarding the explanatory text can be processed by the printer section 3, reads out the Japanese character pattern, and outputs it to the printer section 3.

On the other hand, the figure MPU 5 accesses a dictionary related to figure processing (not shown) to create a figure according to the input information, and generates Japanese text to be used within the figure by accessing a Japanese character pattern generator 6 to create a figure based on the input information. Create a sentence.

In the above-mentioned conventional example, since the character MPU 4 has priority usage rights for the Japanese character pattern generator 6, while the character MPU 4 is using the Japanese character pattern generator 6, the graphic MPU 5 You will be unable to access it and will have to wait.

Therefore, in order for the character MPU 4 to access the Japanese character pattern generator 6, the procedure for accessing the Japanese character pattern generator 6 and the graphic
Procedure for temporarily suspending access from MPU5,
After access is completed, you will need to follow the reverse procedure for accessing.

(d) Problems with the conventional example In the case of the conventional example described above, if the usage rate of Japanese in the figure is large and the number of accesses to the Japanese character pattern generator 6 is large, the MPUs 4 and 5 generate Japanese character patterns. The operating efficiency when the generator 6 is shared will be significantly reduced.

(e) Purpose of the invention The present invention provides a number of new and
The purpose is to provide a method for jointly using hardware using MPUs.
The purpose of this project is to allocate the right to use hardware in a time-divided manner and realize a method for jointly using hardware to further improve the operating efficiency of the entire device.

(f) Structure of the Invention In order to achieve the object, the present invention creates a reference clock signal and a timing signal obtained by dividing one cycle of the reference frequency signal into multiple parts using a reference frequency signal generated by a frequency oscillation circuit. a timing generation circuit, a plurality of clock signals for generating clock signals corresponding to each of the plurality of microprocessors by inputting a reference clock signal, a first timing signal among the timing signals, and a predetermined timing signal corresponding to the half cycle; When multiple microprocessors access the hardware at the same time via a line drive circuit that sends a predetermined signal to a common path, a reference clock signal is sent to the multiple flip-flop circuits at the first timing. When multiple microprocessors simultaneously start accessing the hardware using the generated clock signal, one flip-flop circuit inputs the first and predetermined timing signals and receives the address output from the other flip-flop circuit. The record signal is converted and sent to the common path for address transfer so that the corresponding microprocessor can access the hardware, and the address record signal sent from the other flip-flop circuit to the common path for address transfer is transmitted by the line drive circuit. When the output of the address record signal from one flip-flop circuit stops, the blocking of the address record signal sent from the other flip-flop circuit to the common path for address transfer is released, and the address record signal from the corresponding microprocessor is blocked. By configuring the hardware so that it can be accessed, it is possible to achieve a method of jointly using the hardware by multiple MPUs.

(g) Embodiments of the Invention The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram of a printer device which is an embodiment of the device according to the present invention, and FIG. 3 is an operational diagram of FIG. 2. Note that the same reference numerals indicate the same objects throughout the figures.

The embodiment of the present invention uses a plurality of microprocessors, the MPU 4 for characters and the MPU 4 for graphics explained in FIG.
This is a case where the MPU 5 is used and the Japanese character pattern generator 6, which is also explained in FIG. 1, is used as the hardware.

The character MPU 4, the graphic MPU 5, and the Japanese character pattern generator 6 are connected by a common path consisting of an address bus d and a data bus e.

In addition to the above-mentioned functional blocks, the present embodiment shown in FIG. abbreviated) 13, 16, inversion circuit 1
4. It is equipped with an AND circuit 15.

Also, the symbols a, a', b, b', BE, in FIG.
C, C1 to C4, CL, T, T1 to T8 are the second
The respective signals in the figure are shown.

In FIG. 2, the symbol a is the address decode signal of the MPU 4, the symbol a' is the access time of the Japanese character pattern generator 6 by the MPU 4, and the symbol b is the address decode signal of the MPU 4.
Address decode signal of MPU5, code b′ is MPU
5, the access time of the Japanese character pattern generator 6 is indicated by the symbol BE, which is a bus enable signal and is a signal obtained by ANDing the address decode signal b and the clock signal C4 (shown in FIG. 3).

Furthermore, symbols C1 and C2 are the output signals of the FF circuit 13 and clock signals of the MPU 4, and symbols C3 and C4 are the output signals of the FF circuit 13.
The output signal of the FF circuit 16 is the clock signal of the MPU 5, the symbol CL is the output signal of the timing generation circuit 12 and is a reference clock signal, the symbols T1 to T8 are the output timing signals of the timing generation circuit 12, and the symbol F.
F13 is the output signal of FF circuit 13, code F.F16 is
The output signals of the FF circuit 16 are shown respectively.

In this embodiment, the MPU 4 controls the character information buffer section 1, the MPU 5 controls the graphic information buffer section 2, the Japanese character pattern generator 6 records Japanese character patterns, and the address decoding circuit 7 detects the address decode signal a that accesses the Japanese character pattern generator 6 of the MPU 4 and outputs it to the address bus d, and the address decode circuit 8 outputs the address decode signal b that accesses the Japanese character pattern generator 6 of the MPU 5. The bus driver circuit 9 prevents the signal sent to the MPU 4 from affecting the MPU 5, and outputs the address decode signal b taken out from the address decode circuit 8 onto the address bus d. The bus driver circuit 10 is a drive circuit for sending data based on the AND condition with the BE, and the bus driver circuit 10 prevents the influence on the MPU 5 when transmitting/receiving information between the MPU 4 and the Japanese character pattern generator 6, and also prevents the MPU 5 and the Japanese character pattern generator 6 from influencing the MPU 5. This is a drive circuit for transmitting and receiving information to and from the generator 6. The frequency oscillation circuit 11 generates a reference frequency signal, and the timing generation circuit 12 connects the frequency oscillation circuit 11.
The FF circuit 13 generates timing signals T1 to T8 obtained by dividing the reference clock signal CL and the reference frequency signal into 8 parts according to the reference frequency from the timing generation circuit 12, and the FF circuit 13 uses the reference clock signal CL and the timing signal T1, T
5 and input clock signals C1 and C for MPU4.
2, the NOT circuit 14 outputs a NOT signal of the address decode signal a to the AND circuit 15, and the AND circuit 15
are the output signal of the inverter 14 and the timing signal T5
The timing signal T5 is output to the FF circuit 16 only when the AND conditions match, and the FF circuit 16 outputs the reference clock signal CL from the timing generation circuit 12 and the timing signals T1, T.
5, the clock signal C3 for MPU5,
Create C4.

In this embodiment, MPU4 is given priority over MPU5, and MPU4 and MPU5 operate synchronously using the same clock signal CL.

Furthermore, the FF circuits 13 and 16 receive the timing signal T1.
and is reset by the timing signal T5, and the outputs of the FF circuits 13 and 16 at this time are
MPU4, MPU5 clock signals C1, C2, C
3, given as C4.

The operation of this embodiment will be explained below, mainly referring to the operation diagram shown in FIG.

Now, the Japanese character pattern generator 6 is connected to the MPU 4.
When MPU5 accesses at the same time, address decode signal a from MPU4 and address decode signal b from MPU5 are sent to address decode circuits 7 and 8.
are detected respectively.

At this time, the FF circuit 16 receives the timing signal T5, which is a reset signal, by the address decode signal a.
Since the input of the clock signal C3 is stopped, its output signal, the clock signal C3, remains in the rising state (the third
(shown in the figure) continues.

As a result, the address decode signal b is suppressed by the bus drive circuit 9 because the signal BE which is the logical product of the address decode signal b and the clock signal C4 is not output.

On the other hand, the MPU 4 accesses the Japanese character pattern generator 6 using the address decode signal a (while the clock signal C2 is being output), and when the access is completed, the output of the address decode signal a stops.

During this time, one machine cycle (C1 and C3 rise and fall synchronously, but C1 and C
In this embodiment, one cycle of 3 is called one machine cycle). Therefore, the timing at which the MPU 5 accesses the Japanese character pattern generator 6 is at timing T5 of the next machine cycle.

As described above, the Japanese character pattern generator 6 is accessed by the MPU 4 which has priority in the first machine cycle, but can be accessed by the MPU 5 in the next machine cycle.

(h) Effects of the Invention According to the present invention as described above, it is possible to provide a method for joint use of hardware by a plurality of MPUs, which can improve the operating efficiency of the entire device.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a conventional printer device, FIG. 2 is a block diagram of a printer device that is an embodiment of the device according to the present invention, and FIG. 3 is an operational diagram of FIG. 2. In the figure, 1 is a text information buffer section, 2 is a graphic information buffer section, 3 is a printer section, and 4 is for text.
MPU, 5 is MPU for graphics, 6 is Japanese character pattern generator, 7 and 8 are address decoding circuits, 9,
10 is a bus driver circuit, 11 is a frequency oscillation circuit, 12 is a timing generation circuit, 13 and 16 are F.
14 shows an F circuit, 14 shows a NOT circuit, and 15 shows an AND circuit.

Claims (1)

[Claims] 1. Shared by a plurality of microprocessors 4, 5,
Hardware 6 connected to a common path consisting of a common path e for information transfer and a common path d for address transfer
is a method in which the plurality of microprocessors 4 and 5 jointly use the reference clock signal CL and one cycle of the reference frequency signal by a reference frequency signal generated by the frequency oscillation circuit 11. a timing generation circuit 12 that generates the obtained timing signals T1 to T8; and a timing generation circuit 12 that generates the reference clock signal CL and a first timing signal T1 of the timing signals T1 to T8.
and a predetermined timing signal T5 corresponding to a half cycle, and a plurality of flip-flop circuits 13 and 16 which generate clock signals corresponding to the plurality of microprocessors 4 and 5, respectively, are provided, and the common path The hardware 6 is connected via line drive circuits 9 and 10 that send predetermined signals to the
When the plurality of microprocessors 4 and 5 access at the same time, the reference clock signal is applied to the plurality of flip-flop circuits 13 and 16 at the first timing T1.
When CL is set and a plurality of microprocessors 4 and 5 simultaneously start accessing the hardware 6 using the generated clock signal, one of the flip-flop circuits 13
and predetermined timing signals T1 and T5 are inputted to convert the address record signal a outputted from the one flip-flop circuit 13 and send it to the address transfer common path d, thereby transferring data from the corresponding microprocessor 4 to the address record signal a. hardware 6
At the same time, the address record signal b sent from the other flip-flop circuit 16 to the address transfer common path d is blocked by the line drive circuit 9, and the address record signal a output from the one flip-flop circuit 13 is blocked. When the output stops, the blocking of the address record signal b sent from the other flip-flop circuit 16 to the address transfer common path d is released, and access to the hardware 6 from the corresponding microprocessor 5 is disabled. A method of jointly using hardware with multiple microprocessors.