JPH01113263A - Recording head driver - Google Patents

Abstract

PURPOSE:To enhance the resolution of driving pulses for driving a recording head and enable multi-gradational recording and higher accuracy of heat accumulation correction without enhancing the signal transmission speed of a device circuit, by varying the timing for giving an enabling signal for supplying recording data to the recording head. CONSTITUTION:A recording signal (b) transmitted serially, for example, a four- pixel amount of a recording signal in the state of being split into four parts is latched by the leading edge of a latch signal (c). An enabling signal (d), which is a gate signal, is caused to rise with a delay of 180 deg. behind the phase of the latch signal (c). Therefore, the recording signal (b) transmitted first outputs a pulse duration equal to one half of the period of the latch signal. The recording signal split into N parts for a one-dot amount of data can represent 2N+1 kinds of patterns, as contrasted to the conventional N+1 kinds, so that the resolution of the durations of pulses impressed on a thermal head can be enhanced without varying the transmission speed of signal pulses. Namely, it is possible to increase the number of gradations and to perform highly accurate correction of heat sccumulation, by only varying the timing for the rising of the enabling signal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a recording head driving device, and more specifically, to a recording device using a thermal head or a liquid crystal shutter, it is possible to increase the accuracy of image multi-gradation and heat accumulation correction. The aim is to

(Prior Art) In recent years, recording apparatuses using this type of apparatus have been required to have higher recording speeds, multiple gradations to improve image quality, highly accurate heat accumulation correction, and the like.

In order to achieve these goals, the following processing of large amounts of information is essential. That is, in order to perform multi-gradation of images and highly accurate heat accumulation correction, it is necessary to increase the resolution by, for example, changing the pulse width of the pulse applied to the heating resistor of the thermal head in multiple stages.

[Problems to be Solved by the Invention] However, in the conventional example described above, a large amount of information transmitted serially is converted into parallel information, and the above-mentioned processing must also be performed. For this reason,
For example, it is necessary to increase the signal pulse frequency of a circuit that drives a thermal head, that is, to increase the speed of signal pulse transmission. This has led to the problem that the device circuit must be made faster to drive the head.

Therefore, an object of the present invention is to solve the above-mentioned conventional problems, improve the resolution of the signal that drives the recording head without increasing the speed of the device circuit, and provide a recording medium that can perform multi-gradation and high-precision heat accumulation correction for images. An object of the present invention is to provide a head driving device.

(Means for Solving the Problems) For this purpose, the present invention includes a latch circuit that latches print data for driving a print head at a predetermined timing;
The apparatus includes means for supplying the recording data from the latch circuit to the recording head at a timing different from the latch timing.

[For production]

According to the above configuration, by changing the timing of applying the enable signal for supplying print data to the print head, it is possible to increase the resolution of the drive pulse by making the drive pulse that drives the print head multi-stage. .

〔Example〕

Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings.

FIG. 1 is a block diagram of a thermal head drive circuit showing one embodiment of the present invention. In the figure, 1 is a shift register section consisting of a plurality of shift registers, 2 is a latch section consisting of a plurality of latches, 3 is an output control circuit, and 4 is a heating resistor 5.
5 is a heating resistor, and 6 is an input circuit.

The shift register section l shifts the recording signal input serially through DATA of the input circuit 6 in synchronization with the clock signal a to the register position corresponding to the bit to be recorded by applying a predetermined number of clock signals a. shift. When the recording signal S is set at a predetermined position, the recording signal S is read into the latch circuit corresponding to each shift register of the latch section 2 and latched. This latching is effected by a rising edge of the latch signal C via LATCI+ of the input circuit 6. After sending the recording signal S to the latch section 2, the shift register I repeats the above operation in order to continuously transfer the next recording signal.

On the other hand, the output control circuit 3 has ENA[lLE of the input circuit 6
The driver 4 drives the heat-generating resistor 5 based on the recording signal S taken into the latch section 2 only while the logic of the enable signal d input via the driver is "H". therefore,
The recording signal stored in the latch section 2 is transferred to the shift register 1.
Even when the signal is being transmitted, it can be used as a recording signal for sequentially driving the heating resistor 5.

In this way, when serial data is converted into parallel data and driven, the width of the pulse applied to the heating resistor 5 is changed in order to output a halftone for one dot or to perform heat accumulation correction. There is a need. Therefore, by dividing the recording data for one dot into a plurality of parts, driving is performed by changing the width of the pulse applied to one dot. For this reason,
In order to realize multiple gradations and highly accurate heat storage correction, it is necessary to increase the frequency of the clock signal a1 and the latch signal C, that is, the transmission speed, and increase the number of data divisions. According to this method, the above problem is solved without increasing the transmission speed.

In this embodiment, in order to facilitate understanding, the block diagram in FIG. 1 has a 4-bit configuration, that is, the shift register section 1 has four shift registers, the latch section 2 has four latches, and the latch section 2 has four latches as shown in FIG. Output control circuit 3 is an AND of four
An example consisting of a gate is shown. Therefore, the heating resistor 5 has four heating resistors corresponding to each of the four data D1 to D3, and can record four pixels (dots). It is also assumed that the logic is all positive logic, and the data is divided into four stages.

In addition, at a practical level, a shift register etc. needs to have a configuration of 32 bits or more, and a pulse width of about 12a to Ia. It is clear that the present invention can be practiced even in such cases by expanding the scale.

The thermal head drive control of this embodiment will be explained based on the timing chart shown in FIG. 3 while referring to FIG.

As mentioned above, 4 pixels (4
Recording signal divided into 4 times (expressed in bits) +10
1.1011, 1010, and 1000 are latched at the rising edge of latch signal C. At this point, the enable signal d, which is a gate signal, is 180° in phase with the latch signal C.
Start up late. Therefore, as shown in FIG. 3, the first transmitted recording signal ttot only outputs a pulse width that is half the period of the latch signal, and this width is reduced to 0.5.
shall be. On the other hand, the latter three recording signals output the same pulse width as the period of the latch signal, and this width is assumed to be 1. Therefore, if the enable signal d is raised at the same time as the latch signal C as in the past, the DO signal will be 1+1+1
+1=4. DI is 1 +O+0+O=1. D2 is 0+1
+1+O=2. D3 realizes a pulse width of 1+1+O+O=2, whereas according to this embodiment, DO=0.5
+ 1 + 1 + 1 = 3.5, DI=0.
5 +O+O+0=0.5, D2=O+ 1 +
1 +O=2.0, D3=0.5+++o+o=1
．． s pulse 1] can be realized. In other words, the pulse width that could previously only be expressed in five stages of 0.1.2 and 3.4 can now be expressed as 0.0.5 and 1.1.5 by changing the timing at which the enable signal is raised.
, 2.2.5, and 3°3.5 pulse widths can be achieved.

Conventionally, the number that can be expressed by a recording signal divided into N times after one dot of data is N+1, but according to this embodiment, it is 2.
N+1 expressions are possible, and the resolution of the pulse width applied to the thermal head can be increased without changing the transmission speed of the signal pulse. That is, by simply changing the timing at which the enable signal rises, it is possible to increase the number of gradations and perform highly accurate heat storage correction.

It is clear that the same effect as in the above embodiment can be obtained by lowering the enable signal half the period of the latch signal applied to one dot earlier.

In addition, in a recording device using a liquid crystal shutter, etc., by similarly raising the signal to open the liquid crystal shutter later only at the beginning of the latch signal related to one print, a similar effect can be obtained without speeding up the device circuit operation. The resolution of the drive pulse can be increased.

(Effects of the Invention) As is clear from the above description, by changing the timing of applying an enable signal for supplying print data to the print head, the drive pulse for driving the print head can be multi-staged. It becomes possible to improve the resolution.

As a result, a recording head driving device has been obtained that allows recording images to have multiple gradations and increasing the accuracy of heat accumulation correction without increasing the signal transmission speed of the equipment circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a thermal head drive circuit showing an embodiment of the present invention. FIG. 2 is a block diagram showing details of the shift register, latch circuit output control circuit, and driver shown in FIG. 1. is a timing chart of No. 8 applied to each block shown in FIG. l...Sif (~register section, 2...latch section, 3...output control circuit, 4...driver, 5...heating resistor, 6...input circuit.

Claims (1)

[Claims] A latch circuit that latches print data for driving a print head at a predetermined timing, and means for supplying the print data from the latch circuit to the print head at a timing different from the latch timing. A recording head drive device comprising: