JPH01112745A - Wafer separating method in semiconductor manufacturing device - Google Patents
Wafer separating method in semiconductor manufacturing deviceInfo
- Publication number
- JPH01112745A JPH01112745A JP62269302A JP26930287A JPH01112745A JP H01112745 A JPH01112745 A JP H01112745A JP 62269302 A JP62269302 A JP 62269302A JP 26930287 A JP26930287 A JP 26930287A JP H01112745 A JPH01112745 A JP H01112745A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- wafer
- electrostatic chuck
- power supply
- chuck
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 238000000034 method Methods 0.000 title claims description 18
- 230000003247 decreasing effect Effects 0.000 claims abstract 2
- 239000012212 insulator Substances 0.000 abstract description 6
- 238000000926 separation method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 238000001179 sorption measurement Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Landscapes
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体ウェハのドライエツチングに使用する静電チャッ
クから半導体ウェハを離脱させるとき、静電チャックの
電極の電圧を交番させなからOvにし、チャックの残留
吸着力を減少させるようにした半導体製造装置における
ウェハ離脱方法に関し、
処理の終ったウェハを、容易に、しかもウェハを損なう
ことなく静電チャックから確実に離脱させうる方法を提
供することを目的とし、半導体製造装置の静電チャック
への印加電圧を停止するにおいて、印加電圧の極性を交
番させつつOFFにすること暮特徴とする半導体製造装
置におけるウェハ離脱方法を含み構成する。[Detailed Description of the Invention] [Summary] When removing a semiconductor wafer from an electrostatic chuck used for dry etching of a semiconductor wafer, the voltage of the electrode of the electrostatic chuck is changed from alternating to Ov to reduce the residual adsorption force of the chuck. The purpose of this invention is to provide a method for easily and reliably releasing a processed wafer from an electrostatic chuck without damaging the wafer. The present invention includes a method for removing a wafer in a semiconductor manufacturing apparatus, characterized in that, in stopping the voltage applied to an electrostatic chuck of the apparatus, the polarity of the applied voltage is alternated and turned off.
本発明は、半導体ウェハのドライエツチングに使用する
静電チャックから半導体ウェハを離脱させるとき、静電
チャックの電極の電圧を交番させなからOvにし、チャ
ックの残留吸着力を減少させるようにした半導体製造装
置におけるウェハ離脱方法に関する。The present invention is a semiconductor device in which, when a semiconductor wafer is removed from an electrostatic chuck used for dry etching of a semiconductor wafer, the voltage of the electrode of the electrostatic chuck is changed from alternating to Ov to reduce the residual adsorption force of the chuck. The present invention relates to a wafer detachment method in a manufacturing apparatus.
半導体ウェハ(以下単にウェハという)に対してドライ
エツチングを行うには第4図に示される装置が用いられ
、図中、21は真空に保たれるチャンバ、22はウェハ
、23は静電チャック、24は13.56MHzの電源
25に接続された電極、26は対向電極を示し、電極2
4.26間にプラズマを発生させてウェハ22に対して
ドライエツチングを行う。To perform dry etching on a semiconductor wafer (hereinafter simply referred to as a wafer), an apparatus shown in FIG. 4 is used, in which 21 is a chamber kept in vacuum, 22 is a wafer, 23 is an electrostatic chuck, 24 is an electrode connected to a 13.56 MHz power source 25, 26 is a counter electrode, and electrode 2
During 4.26, plasma is generated to perform dry etching on the wafer 22.
エツチングが終ると、静電チャックの電源を切り、図示
しないモータで上下運動をするピン27でウェハ22を
持ち上げ、そこに図示しないロボットのアームがきてウ
ェハ22をつかんでチャンバ21の外に出し、次いで次
のウェハを図示の位置までもってくる。この操作中、な
んらかの支障がない限り、チャンバ21は真空に保たれ
てん)る。When the etching is finished, the power to the electrostatic chuck is turned off, and the wafer 22 is lifted up by a pin 27 which is moved up and down by a motor (not shown), and a robot arm (not shown) comes and grabs the wafer 22 and takes it out of the chamber 21. The next wafer is then brought to the position shown. During this operation, the chamber 21 is kept in a vacuum unless there is some problem.
このような毎葉式の反応性イオンエツチング(RIB
)中に、プラズマによってウェハが加熱され、レジスト
劣化やエツチングプロファイル劣化を発生させる可能性
があるので、それを防止するために、ウェハを冷却する
。その方法として冷却源と機械的なりランプを組み合わ
せる方法があるが、より高真空で真空チャックまたは静
電チャックを用いる方法も行われ、ウェハへのダメージ
の観点からは静電チャックが優れている。This type of reactive ion etching (RIB)
), the wafer is heated by the plasma and may cause resist deterioration or etching profile deterioration, so to prevent this, the wafer is cooled. One way to do this is to combine a cooling source and a mechanical lamp, but there is also a method using a vacuum chuck or an electrostatic chuck in a higher vacuum, and the electrostatic chuck is superior in terms of damage to the wafer.
静電チャックを詳細に示す第5図を参照すると、静電チ
ャック10は絶縁体10から成るもので、ウェハ16を
吸着する側とは反対側に、+(例えば+IKV)電源1
2に接続された電極13と、−(例えば−I KV)電
源14に接続された電極15が配置されている。Referring to FIG. 5, which shows the electrostatic chuck in detail, the electrostatic chuck 10 is made of an insulator 10, and a + (for example, +IKV) power source 1 is connected to the side opposite to the side that attracts the wafer 16.
An electrode 13 connected to 2 and an electrode 15 connected to a − (for example −I KV) power source 14 are arranged.
第5図を再び参照すると、静電チャック10にはIKν
程度の高電圧を印加し、ウェハに誘起した電荷との間の
Coulombの力でウェハを固定する。なお同図にお
いて、+と−はそれぞれ正と負の電荷を模式的に表す。Referring again to FIG. 5, the electrostatic chuck 10 has an IKν
A relatively high voltage is applied to the wafer, and the wafer is fixed by the Coulomb force between the wafer and the electric charge induced therein. Note that in the figure, + and - schematically represent positive and negative charges, respectively.
ドライエツチングなどの処理を終了して、ウェハを離脱
させるべく第6図の線図に示されるように電源を切って
電源に加わる電圧Voをゼロに落しても、静電チャック
10の電極13.15の上の誘電体(静電チャックは前
述した如く絶縁性材料で作られたものである)の分極に
よる残留電荷によりチャックからウェハが離れず、無理
にとろうとするとウェハを破損する場合がある。なお第
6図で横軸には時間を、縦軸には印加電圧をKVでとる
。Even if the power is turned off and the voltage Vo applied to the power supply is reduced to zero in order to remove the wafer after dry etching or other processing is completed, the electrode 13. The wafer does not separate from the chuck due to the residual charge due to polarization of the dielectric material on top of the chuck (as mentioned above, electrostatic chucks are made of insulating material), and if you try to forcefully remove the wafer, the wafer may be damaged. . In FIG. 6, the horizontal axis represents time, and the vertical axis represents applied voltage in KV.
第4図に戻ると、前記したように電源をOFFにし、次
いでピン27を上方に動かしてウェハを静電チャックか
ら離脱させるのであるが、ウェハが上記した理由で離れ
ないときにピンの力を大にすると、ウェハが破損する。Returning to FIG. 4, as described above, the power is turned OFF, and then the pin 27 is moved upward to release the wafer from the electrostatic chuck. However, when the wafer does not separate from the electrostatic chuck for the reasons described above, the force of the pin is applied. If it is too large, the wafer will be damaged.
そうなると、チャンバの真空を破り、破損したウェハを
除去するだけでな(、ウェハの破損によって発生したウ
ェハの欠けが次工程で次のウェハに付着したり、または
ウェハと静電チャックの間に入ってチャックの吸着力を
弱めたりすることがないように、例えばアルコールを用
いて静電チャックを清拭し、次いでチャンバ内の水分、
空気をパージし、真空引きをしてチャンバ内の真空度を
所定の値に戻さなければならず、それには1〜3時間の
時間が費やされる。In such a case, it is necessary to break the vacuum in the chamber and remove the broken wafer. To avoid weakening the adsorption force of the chuck, wipe the electrostatic chuck with alcohol, for example, and then remove the moisture in the chamber.
The air must be purged and a vacuum drawn to return the vacuum level in the chamber to a predetermined value, which can take 1 to 3 hours.
ピンでウェハがとれないとき、ウェハの破損を発生させ
ないため、真空を破り、ピンセットなどを用いてウェハ
を離脱するときでも、十分に注意してもウェハが破損し
て上記の問題が発生するし、ウェハが破損しなくても真
空を破り、ウェハを離脱し、チャンバ内の空気をパージ
し、もとの真空に戻すにやはり1時間程度の時間が費や
される。When the wafer cannot be removed with the pins, even if you break the vacuum and use tweezers to remove the wafer in order to avoid damaging the wafer, even if you are careful, the wafer will be damaged and the above problem will occur. Even if the wafer is not damaged, it still takes about an hour to break the vacuum, remove the wafer, purge the air in the chamber, and return to the original vacuum.
そこで本発明は、処理の終ったウェハを、容易に、しか
もウェハを損なうことなく静電チャックから確実に離脱
させうる方法を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a method that allows a wafer that has been processed to be easily and reliably removed from an electrostatic chuck without damaging the wafer.
上記問題点は、半導体製造装置の静電チャックへの印加
電圧を停止するにおいて、印加電圧の極性を交番させつ
つOFFにすることを特徴とする半導体製造装置におけ
るウェハ離脱方法によって解決される。The above-mentioned problem is solved by a method for removing a wafer in a semiconductor manufacturing apparatus, which is characterized in that when stopping the voltage applied to the electrostatic chuck of the semiconductor manufacturing apparatus, the polarity of the applied voltage is alternated and turned off.
静電チャックの電極上の電荷は接地すれば直ちに逃がせ
ることができるが、問題は静電チャックを構成する絶縁
体内に誘起された電荷である。絶縁体にある程度の導電
性をもたせることも考えられるが、そうすると電極間の
絶縁性が弱くなるので問題である。The charge on the electrode of an electrostatic chuck can be immediately released by grounding, but the problem is the charge induced in the insulator that makes up the electrostatic chuck. It is possible to make the insulator have some degree of conductivity, but this poses a problem because it weakens the insulation between the electrodes.
そこで本発明は、絶縁体内に誘起された電荷を消去する
ために、電圧を吸着時の電圧VoからいきなりOにする
従来の方法の代りに、第2図に示される如(Voよりも
ピークが小さく、かつ、極性が反対の−v1にし、次い
で+Voより小なる+v2にし次には−v1より小なる
ーv3にし、さらに逐次この方法を繰り返して0ボルト
に近付けることにより誘起電荷を小さくするのである。Therefore, in order to eliminate the charge induced in the insulator, the present invention has developed a method as shown in FIG. Set it to -v1, which is small and has the opposite polarity, then set it to +v2, which is smaller than +Vo, then set it to -v3, which is smaller than -v1, and then repeat this method successively to bring it closer to 0 volts, thereby reducing the induced charge. be.
以下、本発明を図示の実施例により具体的に説明する。 Hereinafter, the present invention will be specifically explained with reference to illustrated embodiments.
第5図に示される配置において、電源12からAには+
l000V、他方の電源14からBには一1000Vが
印加されているとする。ここで、A、Bはそれぞれ電源
12.14から電極13.13と電極15.15へ至る
線の分岐点である0本発明の一実施例においては、この
電圧を切るときに、電源12からAに、−500V 、
250 V 、 −125V 、 62.5Vと印加電
圧を例えば1秒ごとに一1/2倍して印加し、0にもっ
てゆ< (50v以下は切り捨てる)。この変化は第
3図の線図に示され、同図において横軸には時間(1)
を秒でとり、縦軸にはAに加えられる電圧をVでとる。In the arrangement shown in FIG.
It is assumed that 1000V is applied to B from the other power supply 14. Here, A and B are the branching points of the lines from the power supply 12.14 to the electrodes 13.13 and 15.15, respectively.0 In one embodiment of the present invention, when this voltage is cut off, -500V to A,
For example, apply the applied voltages of 250 V, -125 V, and 62.5 V by multiplying them by 1 1/2 every second, and bring them to 0. This change is shown in the diagram in Figure 3, where the horizontal axis represents time (1).
is taken in seconds, and the voltage applied to A is taken in V on the vertical axis.
同様に、Bには前記と正負の符号を逆にした値の電圧を
印加する。Similarly, a voltage having a value with the positive and negative signs opposite to those described above is applied to B.
こうすることによって、静電チャック内に誘起された+
と−の電荷は確実に減少し、Aに加えられる電圧が0の
ときにはこれら電荷はほとんど残留しない状態にあるか
ら、ピンの操作によってウェハは確実に静電チャックか
ら離脱する。By doing this, + induced in the electrostatic chuck
The charges at and - are definitely reduced, and when the voltage applied to A is 0, almost no charges remain, so the wafer can be reliably separated from the electrostatic chuck by operating the pins.
また上記の方法に代えて、Aに加えられる電圧を、10
0OV、 −900V、 800 V、 −700V、
600V 、、、、−100V 、 OVと絶対値を
等差数列的に変えて0にもっていき、Bには正負の符号
の逆にした電圧を印加することもできる。Alternatively, instead of the above method, the voltage applied to A can be set to 10
0OV, -900V, 800V, -700V,
It is also possible to change the absolute value of 600V, .
さらには、前記した印加電圧はパルスで印加しそのパル
ス幅を逐次小さくする方法をとってもよ(、または上記
の2つの方法において電圧をパルスで印加してもよい。Furthermore, the above-mentioned applied voltage may be applied in the form of a pulse and the pulse width may be successively reduced (or the voltage may be applied in the form of a pulse in the above two methods).
上記の方法を実施するには第1図に示す装置を用いる。The apparatus shown in FIG. 1 is used to carry out the above method.
この装置において、分岐点Aには、電源12からと交流
電源17から切換式で電圧が印加されるようになってい
る。In this device, voltage is applied to the branch point A in a switching manner from a power source 12 and an AC power source 17.
静電チャックへの電圧を逐次低下してゼロ(0)にする
には、交流電源の電圧υを
び−UP sin wt
とし、OD間の可変抵抗17の接点をCとすると、Aの
電位真は
’JIA−(QCloo) 17p sin wtとな
る。ここで、Vpは交流電源の振幅、Wは交流電源の角
周波数である。接点Cを例えば図示しないモータで駆動
することにより、 を交番させなから0ボルトにするこ
とができ、図示のものと同じ手段を電源14の側にも設
けられる。In order to gradually reduce the voltage to the electrostatic chuck to zero (0), let the voltage υ of the AC power source be −UP sin wt, and let C be the contact point of the variable resistor 17 between OD, then the potential true of A becomes 'JIA-(QCloo) 17p sin wt. Here, Vp is the amplitude of the AC power supply, and W is the angular frequency of the AC power supply. By driving the contact C, for example, by a motor (not shown), it is possible to reduce the voltage to 0 volts without alternating the voltage, and the same means as shown can be provided on the side of the power supply 14.
以上述べてきたように本発明によれば、静電チャックの
過度の残留吸着力によりウェハが離脱不可能となること
によるダウンタイムが少なくなりエツチングなどに用い
る装置の稼働率が向上し、また無理にウェハを取り出す
ことによるウェハの破損が防止され、コストダウンに有
効である。As described above, according to the present invention, the downtime caused by the wafer becoming impossible to remove due to the excessive residual adsorption force of the electrostatic chuck is reduced, and the operating rate of equipment used for etching etc. is improved. This prevents damage to the wafer due to unloading the wafer, which is effective in reducing costs.
第1図は本発明実施例の図、
第2図は本発明の原理を示す線図、
第3図は本発明方法を示す線図、
第4図はドライ°エツチング装置の断面図、第5図は静
電チャックの断面図、
第6図は従来例方法を示す線図である。
図において、
10は静電チャック、
11は絶縁体、
12と14は電源、
13と15は電極、
16はウェハ、
17は交流電源、
18は可変抵抗
を示す。
特許出願人 富士通株式会社
代理人弁理士 久木元 彰
静電すマツ2の話j1圀
第5 図
にυ
第2図
トキgRtたt禾す線図
第3図Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a diagram showing the principle of the invention, Fig. 3 is a diagram showing the method of the invention, Fig. 4 is a sectional view of the dry etching apparatus, and Fig. 5 is a diagram showing the principle of the invention. The figure is a sectional view of an electrostatic chuck, and FIG. 6 is a diagram showing a conventional method. In the figure, 10 is an electrostatic chuck, 11 is an insulator, 12 and 14 are power supplies, 13 and 15 are electrodes, 16 is a wafer, 17 is an AC power supply, and 18 is a variable resistor. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Akira Kukimoto Story of Electrostatic Sumatsu 2
Claims (4)
電圧を停止するにおいて、 印加電圧の極性を交番させつつOFFにすることを特徴
とする半導体製造装置におけるウェハ離脱方法。(1) A method for removing a wafer in a semiconductor manufacturing device, characterized in that, in stopping the voltage applied to the electrostatic chuck (11) of the semiconductor manufacturing device, the applied voltage is turned off while alternating the polarity.
Fに漸減させる特許請求の範囲第1項記載の方法。(2) OF while gradually lowering the peak height of the alternating voltage.
The method according to claim 1, wherein the method is gradually reduced to F.
圧をOFFにする特許請求の範囲第1項記載の方法。(3) The method according to claim 1, wherein the applied voltage is turned off while successively decreasing the pulse width of the alternating voltage.
る特許請求の範囲第1項記載の方法。(4) The method according to claim 1, in which the peak height is successively lowered by using pulsed alternating voltage.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62269302A JPH01112745A (en) | 1987-10-27 | 1987-10-27 | Wafer separating method in semiconductor manufacturing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62269302A JPH01112745A (en) | 1987-10-27 | 1987-10-27 | Wafer separating method in semiconductor manufacturing device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01112745A true JPH01112745A (en) | 1989-05-01 |
Family
ID=17470452
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62269302A Pending JPH01112745A (en) | 1987-10-27 | 1987-10-27 | Wafer separating method in semiconductor manufacturing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01112745A (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08250579A (en) * | 1995-03-14 | 1996-09-27 | Mitsubishi Electric Corp | Power source for electrostatic chuck of manufacture of semiconductor and manufacture of the semiconductor |
WO1998000861A1 (en) * | 1996-06-28 | 1998-01-08 | Lam Research Corporation | Methods and apparatuses for clamping and declamping a semiconductor wafer in a wafer processing system |
JPH11297803A (en) * | 1998-04-08 | 1999-10-29 | Hitachi Ltd | Electrostatic adsorption device and separation of material to be adsorbed |
JP2002280438A (en) * | 2001-03-19 | 2002-09-27 | Ulvac Japan Ltd | Vacuum treatment method |
WO2005109489A1 (en) * | 2004-05-07 | 2005-11-17 | Shin-Etsu Engineering Co., Ltd. | Work neutralizing method and apparatus thereof |
JP2009300905A (en) * | 2008-06-17 | 2009-12-24 | Stanley Electric Co Ltd | Substrate laminating method |
JP2011077288A (en) * | 2009-09-30 | 2011-04-14 | Tokyo Electron Ltd | Carrying device |
JP2014107382A (en) * | 2012-11-27 | 2014-06-09 | Fuji Electric Co Ltd | Detachment method of semiconductor substrate |
US9130000B2 (en) | 2008-09-30 | 2015-09-08 | Mitsubishi Heavy Industries | Wafer bonding device and wafer bonding method |
KR20190070299A (en) * | 2017-12-12 | 2019-06-20 | 가부시기가이샤 디스코 | Manufacturing method of device chip and pickup apparatus |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4920800B1 (en) * | 1970-06-16 | 1974-05-27 | ||
JPS6199308A (en) * | 1984-10-19 | 1986-05-17 | Hitachi Metals Ltd | Demagnetizing method |
-
1987
- 1987-10-27 JP JP62269302A patent/JPH01112745A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4920800B1 (en) * | 1970-06-16 | 1974-05-27 | ||
JPS6199308A (en) * | 1984-10-19 | 1986-05-17 | Hitachi Metals Ltd | Demagnetizing method |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08250579A (en) * | 1995-03-14 | 1996-09-27 | Mitsubishi Electric Corp | Power source for electrostatic chuck of manufacture of semiconductor and manufacture of the semiconductor |
WO1998000861A1 (en) * | 1996-06-28 | 1998-01-08 | Lam Research Corporation | Methods and apparatuses for clamping and declamping a semiconductor wafer in a wafer processing system |
EP1376682A1 (en) * | 1996-06-28 | 2004-01-02 | Lam Research Corporation | Methods and apparatuses for clamping and declamping a semiconductor wafer in a wafer processing system |
JPH11297803A (en) * | 1998-04-08 | 1999-10-29 | Hitachi Ltd | Electrostatic adsorption device and separation of material to be adsorbed |
JP4647122B2 (en) * | 2001-03-19 | 2011-03-09 | 株式会社アルバック | Vacuum processing method |
JP2002280438A (en) * | 2001-03-19 | 2002-09-27 | Ulvac Japan Ltd | Vacuum treatment method |
WO2005109489A1 (en) * | 2004-05-07 | 2005-11-17 | Shin-Etsu Engineering Co., Ltd. | Work neutralizing method and apparatus thereof |
JP2009300905A (en) * | 2008-06-17 | 2009-12-24 | Stanley Electric Co Ltd | Substrate laminating method |
US9130000B2 (en) | 2008-09-30 | 2015-09-08 | Mitsubishi Heavy Industries | Wafer bonding device and wafer bonding method |
JP2011077288A (en) * | 2009-09-30 | 2011-04-14 | Tokyo Electron Ltd | Carrying device |
JP2014107382A (en) * | 2012-11-27 | 2014-06-09 | Fuji Electric Co Ltd | Detachment method of semiconductor substrate |
KR20190070299A (en) * | 2017-12-12 | 2019-06-20 | 가부시기가이샤 디스코 | Manufacturing method of device chip and pickup apparatus |
JP2019106435A (en) * | 2017-12-12 | 2019-06-27 | 株式会社ディスコ | Method for manufacturing device chip and pickup device |
CN110034065A (en) * | 2017-12-12 | 2019-07-19 | 株式会社迪思科 | The manufacturing method and pick device of device chip |
CN110034065B (en) * | 2017-12-12 | 2024-01-09 | 株式会社迪思科 | Method for manufacturing device chip and pick-up device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5001594A (en) | Electrostatic handling device | |
JP2867526B2 (en) | Semiconductor manufacturing equipment | |
US20030165044A1 (en) | Electrostatic chuck and method of treating substrate using electrostatic chuck | |
KR980012817A (en) | Apparatus and method for withdrawing a product from an electrostatic chuck | |
JPH01112745A (en) | Wafer separating method in semiconductor manufacturing device | |
WO2012090430A1 (en) | Electrostatic adsorption apparatus | |
CN108242421B (en) | Electrostatic chuck device and electrostatic adsorption method | |
JP6069768B2 (en) | Electrostatic chuck device and control method thereof | |
JP3974475B2 (en) | Electrostatic chuck apparatus and substrate processing method using the apparatus | |
JPH06244270A (en) | Electrostatic attraction apparatus | |
JPH0685045A (en) | Separation of wafer | |
KR0171062B1 (en) | Dry etching apparatus | |
GB2293689A (en) | Electrostatic chuck | |
JPH0722499A (en) | Method and apparatus for manufacturing semiconductor | |
TWI725011B (en) | Apparatus, substrate support, and method for removing particles accumulated on a substrate contact surface during substrate manufacturing processing | |
JPH05275517A (en) | Substrate detaching method | |
JPH05291384A (en) | Electrostatic attraction method | |
JP2503364B2 (en) | Wafer electrostatic chucking device, wafer electrostatic chucking method, wafer separating method, and dry etching method | |
JPH04100257A (en) | Treater provided with electrostatic suction mechanism and removal of residual charge in the electrostatic suction mechanism | |
KR20030020072A (en) | Unipolar electro-static chuck | |
KR20100001609A (en) | Wafer chucking and dechucking apparatus | |
JPH11111826A (en) | Method for separating sample in electrostatic chuck | |
JPH04117188A (en) | Electrostatic attracting device and separating method for substrate | |
JP2001267094A (en) | Static eliminator and static elimination method | |
US9142438B2 (en) | Techniques for clamping and declamping a substrate |