JPH01111342A - Package for integrated circuit - Google Patents

Abstract

PURPOSE:To increase the number of external leads which can be used for signal use by a method wherein one or more external leads are connected to a single power-supply wiring part and two or more inner-lead connection wiring parts to be used to impress an identical power supply are connected to the single power-supply wiring part in the extreme neighborhood of individual bonding parts. CONSTITUTION:External leads 101, 107, 108, 114 are connected to a wiring part 149 for power supply use via individual connection points 115, 121, 122, 128; these are connected to the wiring part 149 for power supply use via connection points 143-146 in the extreme neighborhood of bonding parts of internal- lead connection lines 129, 135, 136, 142. Accordingly, while a power supply is applied from the outside by using the required minimum external leads 101, 107, 106, 114 out of limited external leads 101-114 on a package, it is possible to supply the power supply to an integrated circuit chip from the package by using the necessary number of prepared internal leads 129, 135, 136, 142. By this setup, many external leads can be used for signal use.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit package, and more particularly to a wiring connection form between an external lead for power supply and an internal lead.

[Conventional technology]

In conventional integrated circuit packages, the internal leads and external leads basically have a one-to-one correspondence, and they are connected by an internal lead connection line that includes the internal lead portion itself. In some integrated circuit packages, in order to reduce the current density of the bonding wire, the pad for bonding on the chip side of the integrated circuit and the internal leads of the integrated circuit package are each divided into 2 to 3 pieces and placed consecutively. However, these internal lead connection lines are short-circuited within a very narrow area and connected to the external lead, and can essentially be considered as a single internal lead. FIG. 3 is a wiring connection plan view showing connections between internal leads and external leads of a conventional integrated circuit package. FIG. 3(a) is a plan view of the first wiring layer, showing external lead wiring. FIG. 3(b) is a plan view of the second wiring layer,
Internal lead connection wires are shown. The wiring connection form is point symmetrical with respect to the center of the package, and only half of the wiring connection area is shown in the figure. In Fig. 3(a), the external lead 3
01 to 314 are connected to internal lead connection lines 329 to 342 shown in FIG. 3(b) via connection points 315 to 328, respectively.

Of the internal lead connection lines 329 to 342, the portion existing in the bonding area 344 is referred to as an internal lead, and wire bonding is performed between this portion and the bonding pad of the integrated circuit chip installed in the chip mounting area 343.

In the case of Fig. 3, external leads 301, 307° 308.3
14 is an external lead for power supply, and connection points 315, 3
The internal lead connecting lines 329, 355°, 336, and 342 connected via 21, 322, and 328 are made larger than other signal internal lead connecting lines in order to reduce the potential drop in the power supply wiring.

[Problems to be solved by the invention] In the conventional integrated circuit package described above, the internal leads and external leads correspond one-to-one, but in recent years, as the circuit scale of integrated circuits has increased and the chip size has also increased, In order to reduce the power supply voltage drop within an integrated circuit chip, power supply pads have been installed at many locations on the integrated circuit chip, especially in devices that consume large currents such as ECL gate arrays. For this reason, the number of internal leads for power supply corresponding to pads has increased, and as a result of one-to-one correspondence, the number of external leads for power supply has also increased. In this case, in integrated circuit devices with a limited number of external leads, there is a disadvantage that the number of external leads that can be used for signals decreases as the number of external leads for power supply increases. If this is attempted, a package with a large number of external leads must be used, which has the drawback of increasing the size of the integrated circuit device.

Although the DC-related reason of potential drop was mentioned above as the necessity for increasing the number of external leads, there are some devices in which the number of external leads is increased in order to reduce the amount of alternating-current potential fluctuation due to changes in the amount of current. The result is the same in this case, but the conventional method has the drawback that the number of external leads for power supply increases, and the number of external leads provided for signals is reduced accordingly.

[Means for solving problems]

, an integrated circuit package having a multilayer wiring structure according to the present invention has a structure in which one or a plurality of external leads are connected to a single power supply wiring that occupies most of the area of the wiring layer;
A plurality of internal lead connection wirings for applying the same power are each connected to the single power wiring in close proximity to the bonding portion.

A plurality of the internal lead connection wirings also have a feature that there is no current path that reaches the external lead without passing through the single power supply wiring.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a plan view of a wiring layer of an integrated circuit package according to an embodiment of the present invention. FIG. 1(a) is a plan view of the first wiring layer, which is a wiring diagram of external leads.
b) shows a plan view of the second wiring layer, which is the internal lead connection line, and FIG. 1(c) shows a plan view of the third wiring layer, which is the power supply wiring installed according to the present invention. . The wiring connection form is point symmetrical with respect to the center of the package, and only half of the wiring connection area is shown in the figure. Figure 1 (a
), the external leads 101 to 114 each connect to the connection point 11.
5 to 128 to internal lead connection lines 129 to 142 shown in FIG. 1(b). Internal lead connection wire 12
9 to 142, the part existing in the bonding area 148 is called an internal lead, and this part and the chip mounting area 14
Wire bonding is performed between the integrated circuit chip and the bonding pad of the integrated circuit chip installed at 7. Figure 1(a)
The external leads 101, 107, 108, and 114 are power supply external leads, and in this case, they are all used to supply the same power.

Using this structure, external leads 101, 107°, 108.
114 are also connected to the power supply wiring 149 in FIG. 1(c) via connection points 115, 121, 122, and 128, respectively. In addition, internal lead connection wires 129, 135, 136
, 142 are connected to power supply wiring 149 via connection points 143 to 146. As a result, the external leads 101, 107°108.
114 is shorted inside the package.

Now, assuming that the impedance of each connection point is 0, the bonding wires connected to the internal lead connection wires 129, 135, 136, and 142 each draw an average steady current of 200 mA, and this current has large transient current changes. shall be taken as a thing. The resistance of one bonding wire is 10
0mΩ.

Connection points 115, 1.21, 122, 128 of internal lead connection wires 129, 135, 136° 142 and connection point 1
The resistance between 43, 144, 145, and 146 is 300 m each.
Ω, external leads 101.107, 108, 114 from connection points 115, 121° 122.128 to external connection parts
resistance of 50 mΩ each, connection points 115, 121, 122
Connecting points 143, 144° 145.
The resistance on the power supply wiring 149 leading to each of 146 is 60m.
If Ω, external lead 101°107.108,11
The amount of potential shift from the external connection part 4 to the bonding wire terminal on the integrated circuit chip side is 90 mV when there is no power supply wiring 149, but becomes 40 mV when there is power supply wiring 149. This difference of 50 mV is of great significance in an ECL circuit in which the value of the output logic level of an integrated circuit is determined by the power supply potential and the allowable range of its absolute value is narrow. The above-mentioned potential difference is discussed in terms of a steady current value, and is a direct current potential shift amount, but the potential fluctuation that occurs when the current changes due to the inductance component of the power supply wiring path also reduces the noise margin for the operation of the integrated circuit. Sometimes malfunctions occur.

Compared to the resistance component, the inductance component differs depending on the shape of the path, but it can be said that it is generally proportional to the resistance component. Therefore, if there is no power supply wiring 149, a potential fluctuation of 90 mV would occur at L□, but due to the presence of the power supply wiring 149, the potential fluctuation will be reduced to approximately 40 mV.

In the embodiment shown in FIG. 1, the number of external leads used for the above-mentioned power supply in the entire package is 8, and the number of external leads used for other purposes is 20, but the same effect can be obtained without using the power supply wiring 149. In order to increase the voltage, it becomes necessary to provide an external lead of 1O for power supply, and the number of external leads for signals is reduced accordingly, which is difficult in practical use.

FIG. 2 is a plan view of a wiring layer of an integrated circuit package according to another embodiment of the present invention. FIG. 2(a) is a plan view of the first wiring layer, which is a wiring diagram of external leads, and FIG. 2(b) is a plan view of the first wiring layer.
2(c) is a plan view of the second wiring layer, which is the internal lead connection line, and FIG. 2(c) is a plan view of the third wiring layer, which is the power supply wiring installed according to the present invention. The wiring connection form is point symmetrical with respect to the center of the package, and only half of the wiring connection area is shown in the figure.

In FIG. 2(a), external leads 201-214 are connected to internal lead connection lines 229-242 shown in FIG. 2(b) via connection points 215-228, respectively. The internal lead connection lines 243 and 244 do not have a connection line directly to the external lead in the second wiring layer. Internal lead connection wire 229
244, the portion existing in the bonding region 250 is referred to as an internal lead. This part and chip mounting area 24
Wire bonding is performed between the bonding pads of the integrated circuit chip installed at 9. Figure 2(a)
The external leads 201 and 208 are power supply external leads, and in this case, they supply the same power.

Using this structure, the external leads 201 and 208 are also connected to the power supply wiring 251 in FIG. 2(c) via connection points 215 and 222, respectively. In addition, the internal lead connection wire 22
9, 236, 243, 244, these are connected to connection points 245, 247, 246, 248.
It is connected to the power supply wiring 251 via. As a result, the external leads 201 and 208 that are short-circuited within the package are half of those shown in the embodiment of FIG. 1, but the internal leads that actually supply power to the integrated circuit chip are The connection wire is the internal lead connection wire 229
, 236, 243, 244, which are the same numbers as in the embodiment of FIG.

Now, assume that the impedance of each connection point is 0,
From the bonding part to the internal lead connection wire 229.236,
Connection point of 243, 244 245° 247. 246, 24
The impedance up to 8 is also 0. It is assumed that the bonding wires connected to the internal lead connections 229, 236, 243, and 244 each draw a steady current of 200 mA, which also has large transient current changes. The resistance of one bonding wire is 100 mΩ, and the connection points 215 and 222 of the internal lead connection wires 229 and 236 and the connection point 2
The resistance between 45 and 247 is 300 mΩ each, and the connection point is 215.
, 222 to the external connection point 201, 2
08 is 50 mΩ each, and the resistance on the power supply wiring 251 from all of the connection points 215, 222 to each of the connection points 245, 246, 247, and 248 is 65 mΩ. Therefore, the potential shift i to the end of the bonding wire on the integrated circuit chip side is approximately 52 mV. Furthermore, the internal lead connection wire 243
, 244, the potential shift amount becomes approximately 42 mV. This value can be said to be effective under the same conditions as the embodiment shown in FIG. If there is no power supply wiring 251 in FIG. 2, this potential shift amount will be as much as 180 mV.

These values are DC potential shift amounts, but as in the example of FIG. The amount of potential fluctuation is approximately 52 mV.

The embodiment shown in FIG. 2 differs from the embodiment shown in FIG. 1 in that internal lead connection wires 243 and 244, which are not connected to external leads, are added inside the package through the second wiring layer. In the embodiment shown in Figure 1, the number of external leads for the corresponding power supply was 8 in the whole package, and the number of external leads used for other purposes was 20, whereas in the second embodiment, the number of external leads for the corresponding power supply was 8. The number of external leads for the entire package is 4, and the number of external leads used for other purposes is 24.
and is increasing.

〔Effect of the invention〕

As explained above, the present invention connects a single power supply wiring from a wire or a plurality of external leads to a single power supply wiring laid out occupying most of one wiring layer in a package, and connects this power supply to an integrated circuit. By connecting the single power supply wiring to the plurality of internal lead connection lines for supplying power to the chip, it is possible to connect the power supply from the outside using the minimum necessary number of external leads among the limited number of external leads on the package. It is possible to supply power from the package to the integrated circuit chip through the internal leads provided as many times as necessary, and as a result,
This has the effect that more external leads can be provided for signals.

In the above explanation, only one type of external power supply has been explained, but in recent years integrated circuit devices have also appeared with a mixture of positive and negative power supplies, and some have come to use six types of external power supplies. If eight external leads are used for each of the six types of power supplies as in the conventional method, only 152 external leads remain that can be used for signals even in a package having 200 external leads. However, by using the present invention, it is possible to supply multiple power supplies within the package by using two external leads for each power supply, and via a single power supply wiring on a separate line layer for each power supply. If internal leads are installed, out of a total of 200 external leads,
It is also possible to use 188 bins for signals.

The present invention is extremely effective in making effective use of the limited number of external leads and improving the performance of integrated circuit devices, and this effect is even more useful for integrated circuit packages that use a large number of power supply types.

[Brief explanation of the drawing]

FIG. 1 shows the wiring connection inside the package according to the first embodiment of the present invention, FIG. 1(a) is a plan view of the first wiring layer, and FIG. 1(b) is a plan view of the second wiring layer. Plan view of wiring layer, Figure 1 (
c) is a plan view of the third wiring layer, FIG. 2 shows another embodiment of the present invention, FIG. 2(a) is a plan view of the first wiring layer, and FIG. ) is a plan view of the second wiring layer, and Figure 2 (
3(c) is a plan view of the third wiring layer, FIG. 3(a) is a plan view of the first wiring layer, FIG. b) is a plan view of the second wiring layer. 101-114, 201-214, 301-314...
...External lead, 115~128°143~146
,215~228,245~248.315~328・
...Connection point, 129-142.229-244,
329-342...Internal lead connection wire, 147
, 249, 343... Chip mounting area, 148
, 250. ．． 344...Bonding area, 1
49,251... Power supply wiring. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] 1. In an integrated circuit package having a multilayer wiring structure, at least one external lead is connected to a single power supply wiring laid out occupying most area of one wiring layer, 1. A package for an integrated circuit, characterized in that a plurality of internal lead connection wirings for applying the same power supply are each connected to the single power supply wiring in close proximity to a bonding portion. 2. The integrated circuit package according to claim 1, wherein a plurality of the internal lead connection wirings have no current path that reaches the external lead without passing through the single power supply wiring.