JPH01103016A - Semiconductor integrated circuit for voltage comparison - Google Patents

Abstract

PURPOSE:To eliminate the need of an external timing signal by generating a comparator control use timing signal and a latching circuit use strobe pulse signal by using a built-in ring oscillator. CONSTITUTION:An offset compensation type voltage comparator 10 compares an input signal 1 and a reference telegraph signal 2, and outputs its result by a digital value. The output digital value is latched by a D-type flip-flop 20, and the output which has been to offset compensation is outputted to a terminal 9. A ring oscillator 30 is constituted of plural inverter circuits, and output three signals having a prescribed delay. A first signal 4 is supplied as an offset control use pulse voltage to the comparator 10. Also, a second signal 5 having a prescribed delay against said first signal, and a third signal 6 which has been inverted by an inverter 50 are brought to AND operation by an AND circuit 40, and become a strobe signal 8 to the D-type flip-flop 20. In such a way, the offset compensation type voltage comparator which necessitates no external clock, and also, has a large operation margin can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an offset-compensated voltage comparison semiconductor integrated circuit used in a device that converts an analog signal voltage into an ital signal voltage.

(Prior Art) In recent years, so-called A/D converters that convert analog signal voltages into digital signal voltages are required to have increasingly higher precision. A high-precision A/D converter requires a voltage comparator circuit with high resolution, but the resolution is inhibited by the input offset voltage of the voltage comparator circuit. Therefore, it is necessary to reduce the input offset voltage.

As a method for reducing the input offset voltage, in semiconductor-integrated voltage comparison circuits, it is necessary to improve the manufacturing process and make the characteristics of the integrated device uniform by devising techniques, such as MOSFE.
If it uses T, it will reduce gate threshold voltage vT, transconductance gm, and tonnage Ila, and if it uses bipone transistor, it will improve current amplification factor h'fe, pace emitter barrier voltage Vbe, etc. Although a method of reducing manufacturing variations is used, another method is to acknowledge the existence of such manufacturing variations and reduce the input offset voltage by devising a circuit. That is, it is an offset compensation type voltage comparison circuit.

Conventionally, this type of offset-compensated voltage comparison circuit is comprised of a circuit that compares and amplifies a reference voltage and an input signal voltage, and a storage circuit that stores and holds the compared and amplified signal voltage. Comparison and amplification circuit (hereinafter referred to as voltage comparison circuit)
A clock signal is applied to the device to reduce the offset voltage, the offset voltage is absorbed during the standby period, and the input signal voltage is compared and amplified with the reference voltage during the operation period, and this output voltage is applied to the next storage circuit (hereafter referred to as (referred to as a latch circuit)
However, a different type of clock signal different from the clock signal is used in the latch circuit. For a detailed explanation of such an offset-compensated voltage comparison circuit, see 19
A publication published in February 1985, ``I Nis Nis She'' Sea-1985-Tysisist Off Technical Conflict Pavers'' (l5SCC1985DIGEST OF
TECHNICAL PAPER 8').

FIG. 4 shows a schematic diagram of a conventional offset-compensated voltage comparison semiconductor integrated circuit. The offset-compensated voltage comparator circuit 100 typically includes a high-sensitivity amplifier and a capacitor that absorbs offset voltage. An input signal voltage is applied from a terminal 101 to the voltage comparison circuit 100, and a reference voltage for comparison is applied from a terminal 102. The pulse generation circuit 300 outputs the voltage to the voltage comparison circuit 100 . An offset control pulse voltage is applied through the lead wire 106. When the offset control pulse voltage is at a low level, the voltage comparator circuit 100 is normally in a standby state, and the offset voltage of the high-sensitivity amplifier is charged in the capacitor, and when the control pulse voltage reaches a high level, the input signal voltage and the reference voltage are The difference voltage is amplified, and at this time, the offset voltage charged in the capacitor is subtracted and the amplified result is output from the lead wire 105. The output voltage from lead 105 is latched by latch circuit 200, which is latched by a strobe pulse voltage generated from pulse generation circuit 300 and applied by lead 107.

The strobe pulse voltage is generated by the pulse generation circuit 300 based on external clock pulse voltages inputted from multiple terminals 103. The offset control clock pulse voltage applied to the offset compensation type voltage comparison circuit 100 via the lead wire 106 is also generated by the pulse generation circuit 300 based on the external clock pulse voltage input from the terminal 103.

(Problems to be Solved by the Invention) In such a conventional offset-compensated voltage comparison semiconductor integrated circuit, it is necessary to apply a clock pulse voltage from the outside via the terminal 103, and in addition, the pulse generation circuit 30
There is a drawback that the period and duty of the external clock pulse voltage must be accurately managed so that the offset control clock pulse voltage and the strobe-pulse voltage are appropriately generated from zero.

SUMMARY OF THE INVENTION The present invention aims to improve the above-mentioned drawbacks, and aims to provide an offset-compensated voltage comparison semiconductor integrated circuit that does not require an external clock signal and has a large operating margin.

(Means for Solving the Problems) The features of the present invention for achieving the above object include a comparison circuit that is driven by a first clock signal and compares an input signal with a reference potential and outputs the result as a digital value; It has a D-type foot-flop that latches the comparison result with a second clock signal and provides an offset-compensated output, and a plurality of inverter circuits connected in a ring shape, and a predetermined delay from the output of each inverter circuit. a ring oscillator capable of outputting a signal having a signal having a value of 1, a means for making one output of the ring oscillator the first clock signal, and a logic operation means for providing the second clock from another output of the ring oscillator. It is in.

(Operation) In the above configuration, the ring oscillator can output a plurality of delayed signals with slightly different timings.

Therefore, by processing the output of the ring oscillator with a combinational logic circuit, all the clock signals necessary for the comparator circuit can be stably obtained, and no external timing signal is required.

The above objective is thus achieved.

(Embodiment) FIG. 1 shows an embodiment of a voltage comparison semiconductor integrated circuit according to the present invention. A pulse voltage for offset control is supplied from the ring oscillator 30 to the offset compensation type voltage comparator circuit 10 via the lead wire 4, and a pulse voltage delayed in time from the pulse voltage for offset control is supplied via the lead wire 5. A further delayed pulse voltage is applied to the AND circuit 5 via the lead wire 6 to the inverter 50 . ring oscillator 30
A detailed circuit diagram is shown in Figure 2. In this figure, terminal 4°5.6 corresponds to lead wire 4,5.6 in FIG.

The ring oscillation circuit is a circuit in which an odd number of stages of inverter circuits are connected in a ring shape, and as can be seen from Fig. 2, the pulse voltage from terminal 5 is The voltage is delayed by two inverter stages, and the pulse voltage from terminal 6 is further delayed by inverter 2.
It's delayed by a few steps. If the pulse voltage from terminal 5 is taken as strobe pulse voltage 1, and the pulse voltage from terminal 5 is taken as strobe pulse voltage 2, the relationship between them will be as shown in FIG. In FIG. 3, τ indicates the delay time. In addition,
The ring oscillation circuit is configured such that the periods of these pulse voltages are sufficiently longer than the operating speeds of the offset-compensated voltage comparison circuit 10 and the D-type flip-flop circuit 20. The output from the inverter circuit 50 is input to the AND circuit 40 via the lead wire 7, and the output is input to the AND circuit 40 via the lead wire 8.
is applied to the D-type flip-flop circuit 20 as a strobe pulse voltage. Here, the AND circuit 40
The inverter circuit 50 also has a sufficiently high speed compared to the pulse period. Therefore, most of the time delay is determined by the ring oscillation circuit, and delays in other logic circuit parts can be ignored. The relationship between the offset control pulse voltage and the strobe-pulse voltage is as shown in FIG. Lead wire 8
Since the data is applied to the D-type flip-flop circuit 20 via the D-type flip-flop circuit 20, the data is latched and outputted from the output terminal 9.

In FIG. 1, one of the features of the present invention is that the external pulse input terminal 103 in FIG. 4 does not exist.
.

(Effects of the Invention) As can be understood from the above explanation, in the voltage comparison semiconductor integrated circuit according to the present invention, there is no need to apply an external clock signal, and the delayed pulse voltage is generated by the built-in ring oscillation circuit. The pulse voltage for offset control and the strobe pulse voltage are created using it.
The time delay relationship between them can be maintained accurately, and as a result, a latch operation with a large operating margin can be performed. The offset voltage is stored in the offset voltage, and the offset voltage is not particularly limited during the operation period.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of a voltage comparison semiconductor integrated circuit according to the present invention, FIG. 2 shows a ring oscillation circuit, FIG. 3 shows an operating waveform diagram of the circuit of FIG. 1, and FIG. 4 shows an example of a conventional circuit. 1; input terminal, 2; comparison voltage input terminal, 10;
Voltage comparison circuit, 20; D-type flip-flop, 30; ring oscillation circuit, 40; AND circuit, 50; inverter circuit.

Claims (1)

[Claims] A comparison circuit that is driven by a first clock signal and compares an input signal with a reference potential and outputs the result as a digital value; and an offset-compensated output that latches the comparison result by a second clock signal. A D-type flip-flop that provides a D-type flip-flop, a ring oscillator that has a plurality of inverter circuits connected in a ring shape and is capable of outputting a signal with a predetermined delay from the output of each inverter circuit, and A voltage comparison semiconductor integrated circuit comprising: means for providing the first clock signal; and logic operation means for providing the second clock from another output of a ring oscillator. (2) Claim 1, characterized in that the logical operation means is means for providing a logical product of the second output of the ring oscillator and the third output of the ring oscillator via an inverter circuit. The voltage comparison semiconductor integrated circuit described.