JPH01109838A - De-stack system jitter suppressing circuit - Google Patents

Abstract

PURPOSE:To attain the reduction of a bit and phase matching confirming time and the reduction of a device output jitter quantity at line changeover by selecting an output signal of a low pass circuit of a phase comparator circuit when synchronization is taken and selecting a control signal of the phase comparator circuit when the synchronization is not taken. CONSTITUTION:With a hit less switching A started, a de-stack system jitter suppression circuit of a standby transmission line controls a voltage controlled oscillator circuit 3 by a phase comparator circuit output signal 101 (signal component including a broad band component) itself. Thus, the time required for comparing active/standby line signals is reduced and high speed performance is maintained. Moreover, after the synchronization is established, the voltage controlled oscillation circuit 3 is controlled by a low signal component 102 obtained from a phase comparator circuit output signal 101 through a low pass filter circuit 4 to keep the jitter characteristic to an excellent value.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a destacking type jitter suppression circuit, and in particular,
The present invention is applied to a destack-based jitter suppression circuit suitable for use in a (1+N) hitless line switching device (N≧1) in wireless digital transmission.

[Conventional technology] Conventionally, in line switching equipment for wireless digital transmission, due to restrictions on equipment output jitter standards, it has been necessary to keep the jitter passband (noise bandwidth) in the destack-based jitter suppression circuit as low as possible to maintain good jitter characteristics. was.

FIG. 2 is a block diagram of a conventional destack-based jitter suppression circuit, and FIG. 3 is a block diagram of a (1+N) Hill I/less line switching device to which the destack-based jitter suppression circuit is applied.

First, the operation of the (1+N) hitless line switching device shown in FIG. 3 will be explained.

In the figure, reference numeral 11 denotes a transmission end switching circuit, which switches the signal input to the multiplexing circuit 12.

13 is a line monitoring circuit that monitors whether there is an abnormality in the line; 14
15 is a demultiplexing circuit that separates necessary information signals from multiplexed signals; 15 is a hitless switching circuit that performs hitless switching from the working line to the protection line; 16 is a pilot signal generation circuit that generates a pilot signal for the protection line; and 17 is a This is a pilot signal detection circuit that detects the pilot signal of the protection line.

Reference numerals 18 and 19 are line switching control circuits at the sending end and receiving end, respectively, which perform various controls when switching lines.

A general switching sequence for hitless switching in the above configuration is performed as follows.

On the receiving end, when the line monitoring circuit 13 detects a fault A in the working line, the line monitoring circuit 13 for the protection line checks whether there is a fault B in the protection line, and roughly calculates the signal from the output of the pilot signal detection circuit 17. Confirmation of usage status of backup line C
Do this. As a result, when the protection line is available, the sending end side starts parallel operation at the sending end.

Next, on the receiving end side, the failed working line transmission signal 203 and the protection line transmission signal 204 are compared, and after it is confirmed that the bits and signal phases match, the switching circuit 15 performs switching (hitless switching) E. . This completes the relief of the faulty line.

The destacking jitter suppression circuit shown in FIG. 2 is included in the separation circuit 14 installed upstream of the hitless switching circuit 15 in FIG.

Next, in FIG. 2, 1 is a storage circuit for restoring a transmission signal, 2 is a phase comparison circuit, 3 is a voltage controlled oscillation circuit, and 4 is a low-pass circuit. Then, the voltage controlled oscillation circuit 3 is controlled by the output of the phase comparator circuit 2 passed through the low-pass circuit 4, and the phase of the output 106 of the voltage controlled oscillation circuit 3 and the phase of the write clock 105 input to the memory circuit l are adjusted. Match.

By the way, in the hitless switching sequence in the (1+N) hitless line switching device shown in FIG. 3, when an abnormality occurs in the working line, the hitless switching operation A is activated and the sending end parallel operation is performed. Then, the input of the destack-based jitter suppression circuit in the protection line transmission line separation circuit 14 changes from the pilot signal 202 that transmits the protection line during normal operation to the transmission signal 201 that is the information signal that should originally be transmitted.

However, in the destack-based jitter suppression circuit, the jitter passband (noise bandwidth) is kept as low as possible by the low-pass circuit 4 in order to maintain good device-to-device characteristics. That is, the low frequency signal component 10 of the phase comparison circuit output signal 101
2 controls the voltage controlled oscillation circuit 3.

However, when the voltage controlled oscillator circuit 3 is controlled by this low frequency signal component 102, the phase response of the voltage controlled oscillator circuit output signal 106 to changes in the input lO5 becomes very slow, and the transmission signal 204 is restored and the hitless switching circuit 15 It took a considerable amount of time to supply the

Therefore, in the conventional destack type jitter suppression circuit, it takes a considerable amount of time to compare the working and protection line signals during the hitless switching sequence, and the high speed of the hitless switching sequence is lost.

[Problems to be solved] The conventional destacking type jitter suppression circuit described above has (1+
N) When applied to a hitless line switching system, the response time during line switching becomes extremely long.

For this reason, there is a problem in that it takes a long time to check the bit and phase matching between the working and protection lines, which is essential for hitless switching, and the high speed required for the hitless switching sequence is lost.

The present invention has been made in view of the above-mentioned problems, and it shortens the time of bit and phase matching confirmation between working and protection lines during hitless line switching in a (1+N) system configuration of a wireless digital transmission system, and shortens the time of closing when checking the bit and phase match between the working and protection lines, and the device output. The object of the present invention is to provide a destack-based jitter suppression circuit that can simultaneously reduce the amount of jitter.

[Means for Solving Problems] In order to achieve the above object, the destack type jitter suppression circuit of the present invention compares the phase of the input clock signal and the oscillation output of the voltage controlled oscillation circuit with the voltage controlled oscillation circuit, and calculates the voltage A phase comparison circuit that outputs a control signal that controls the controlled oscillation circuit in a negative feedback manner and matches the phase of the oscillation output with the phase of the input clock signal; a low-pass circuit that selects either the control signal of the phase comparator circuit or the output signal of the low-pass circuit to input the signal to the voltage-controlled oscillator circuit; Monitor the synchronization state between the signal and the oscillation output of the voltage controlled oscillation circuit,
a synchronization state monitoring circuit that causes the switching circuit to select the output signal of the low-pass circuit when synchronization is achieved, and selects the control signal of the phase comparison circuit when synchronization is not achieved; The configuration includes a storage circuit that inputs a clock signal and the oscillation output of the voltage-controlled oscillation circuit, and stores and reads input data.

[Example] Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 1 is a block diagram of a destack-based jitter suppression circuit according to an embodiment of the present invention. Note that parts common to or corresponding to those of the conventional example are denoted by the same reference numerals.

In the figure, reference numeral 5 denotes a switching circuit which, under the control of the synchronization state monitoring circuit 6, switches the output of the phase comparator circuit 2 between those that have passed through the low-pass circuit 4 and those that have not.
Either one is input to the voltage control circuit 3. The synchronization state monitoring circuit 6 also receives the output signal 1 of the voltage controlled oscillation circuit 3.
06 and the write a-lock signal 105 of the memory circuit I is monitored, and the switching circuit 5 is controlled according to the synchronization state.

That is, output signal 106 and write clock signal 10
The output of the switching circuit 5 is controlled to select the phase comparison circuit output signal 101 until the synchronization with the phase comparison circuit 5 is established, and the switching circuit 5 is returned to its original state at the same time as the synchronization is established.

In the above configuration, at the same time that the hitless switching operation A is activated, the sending end parallel control is performed as in the conventional example.

However, at this time, the destack-based jitter suppression circuit of the protection line transmission line controls the voltage controlled oscillation circuit 3 using the phase comparison circuit output signal 101 (signal component including a wide range component) itself. That is, the switching circuit 5 is controlled by the output signal 107 of the synchronization state monitoring circuit 6 so as to be able to quickly respond to input changes from the pilot signal 202 to the transmission signal 201. That is, the voltage controlled oscillation circuit 3 is controlled by the phase comparison circuit output signal 101 itself including the wide-range signal component.

As a result, the protection line transmission path changes from the pilot signal 202 to the transmission signal 201 due to the sending end parallel side i1D, but the phase of the output signal 106 of the voltage controlled oscillator circuit 3 with respect to this change (that is, the change in the write clock signal 105) The response will be very fast. Therefore, it becomes possible to quickly restore the transmission signal 204 and supply it to the hitless switching circuit 15, and furthermore, the time required to compare the working and protection line signals is reduced, and high speed is maintained.

Further, after synchronization is established, the voltage controlled oscillation circuit 3 is controlled by the low-pass signal component 102 obtained from the phase comparison circuit output signal 101 through the low-pass circuit 4 to maintain good jitter characteristics.

In this way, in this embodiment, (1
+N) In the destack type jitter suppression circuit of the protection line transmission line in the hitless line switching system (N13), there is a system that controls the voltage controlled oscillator circuit with the reduced signal component of the phase comparison circuit output signal, and a wide range signal component of the phase comparison output signal. and a system for controlling the voltage controlled oscillation circuit with signal components including the input clock signal and the output signal of the voltage controlled oscillation circuit, and a synchronization state monitoring circuit monitors the synchronization state of the input clock signal and the output signal of the voltage control oscillation circuit, and the switching circuit is controlled by the output signal. One of these two systems is selected under control.

[Effects of the Invention] As described above, the present invention has the effect of providing a destack-based jitter suppression circuit that maintains good jitter characteristics and also has a high-speed hitless switching sequence.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a destack-based jitter suppression circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional destack-based jitter suppression circuit, and FIG. 3 is a destack-based jitter suppression circuit shown in FIGS. 1 and 2. FIG. 2 is a system configuration diagram of a (1+N) hitless line switching device in which the circuit is used. l: Memory circuit 2: Phase comparison circuit 3: Voltage controlled oscillation circuit 4 = Low pass circuit 5: Switching circuit 6: Synchronization state monitoring circuit

Claims (1)

[Claims] A voltage controlled oscillation circuit compares the phase of the input clock signal and the oscillation output of the voltage controlled oscillation circuit to output a control signal that controls the voltage controlled oscillation circuit in a negative feedback manner, and outputs a control signal that controls the voltage controlled oscillation circuit in a negative feedback manner, and the phase of the oscillation output is input to the input clock signal. A phase comparison circuit that matches the phase of the clock signal, a low-pass circuit that inputs the control signal of this phase comparison circuit and passes only the low-frequency component, and A switching circuit selects one of the output signals and inputs it to the voltage controlled oscillation circuit, and monitors the synchronization state of the input clock signal and the oscillation output of the voltage controlled oscillation circuit, and , a synchronization state monitoring circuit that selects the output signal of the low-pass circuit when the synchronization is established, and selects the control signal of the phase comparison circuit when the synchronization is not achieved; and the input clock signal and the voltage control circuit. What is claimed is: 1. A destack-based jitter suppression circuit comprising: a storage circuit that receives an oscillation output from an oscillation circuit and stores and reads input data.