JPH0982976A - Thin-film transistor, manufacture thereof and liquid-crystal display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin-film transistor having excellent characteristics and high yield and manufacture thereof, and to provide a liquid-crystal display, which has superior and uniform characteristics even on a large-sized picture plane and in which a flicker and burning are reduced. SOLUTION: This transistor has a process, in which a light-shielding high resistance layer 103 is formed onto a transparent insulating substrate 101 and patterned, a process, in which a conductor layer is formed on the upper side of the light-shielding high resistance layer and patterned to a gate electrode 104, a process, in which a gate insulating layer 105 and a conductor layer 106 are shaped successively on the upper side of the gate electrode and these each layer is patterned, a process, in which a contact layer 107 and the conductor layer are formed in succession from the upper side of the semiconductor layer and a process, in which the contact layer and the conductor layer on the side upper than the semiconductor layer are removed and a source electrode 108 and a drain electrode 109 are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method of manufacturing the same, and more particularly to a liquid crystal display device having the thin film transistor.

[0002]

2. Description of the Related Art A thin film transistor is an electronic device used in a large amount in a wide range of industrial fields, and a liquid crystal display device is one of its main fields.

In a conventional thin film transistor, SiOx is first formed as an undercoat layer on a transparent insulating substrate such as a glass substrate. A refractory metal layer such as Cr or Mo-Ta alloy is patterned thereon to form a gate electrode, an auxiliary capacitance electrode, and a gate extraction electrode. This gate electrode is SiNx or Si
It is covered with Ox or a gate insulating film having a laminated structure of these, an a-Si layer is formed as an active layer in a region corresponding to the gate electrode on the insulating film, and a SiNx layer is further laminated as a protective layer of the active layer. And is patterned into a predetermined shape. Further, an n ⁺ a-Si layer is laminated and patterned as an ohmic contact layer with the active layer.

Then, the transparent conductive film layer such as ITO which becomes the pixel electrode is patterned into a predetermined shape. Further, the gate insulating film on the gate electrode extraction electrode and the like is removed by etching. A source electrode and a drain electrode are formed on this in a predetermined pattern to complete ΤFΤ. Furthermore, Si
A protective layer such as Nx is laminated and patterned. Further, a polyimide film is deposited and the array substrate is completed through a rubbing process. A liquid crystal layer is injected between this and a counter substrate made of a transparent conductive film such as ITO and a color filter to complete a liquid crystal display device.

However, in the liquid crystal display device using the thin film transistor as described above, it is necessary to form the source electrode and the drain electrode even on the channel protective layer. Therefore, there is a problem that the parasitic capacitance between the gate and the source becomes large and flicker or burn-in occurs.

On the other hand, the following thin film transistor has been proposed (Japanese Patent Publication No. 62-239579).

FIG. 12 shows one of such thin film transistors.
It is a figure showing an example. That is, the gate electrode 1202 is deposited on the undercoat film 1201 formed on the insulating substrate in a convex cross-section and patterned, and then the gate insulating layer 12 is formed.
03, semiconductor layer 1204, highly doped semiconductor layer 120
5 is deposited. After that, a conductive film is deposited by a bias sputtering method so that its upper surface becomes flat, and isotropic etching is performed to expose the semiconductor layer above the convex portion of the gate electrode, and the source / drain electrode 1206 is patterned. It is a formed thin film transistor.

This thin film transistor is characterized by high yield because it can be self-aligned without using a resist. However, in this thin film transistor, since the convex type gate electrode is used, the gate electrode becomes thick, which is a disadvantageous structure for reducing the capacitance between the gate and the source.
This is because, for example, since the gate electrode is formed in a convex shape, the gate electrode is made into a two-layer metal layer structure to widen the area of the lower metal layer, and a metal layer having a smaller area is stacked on it. Therefore, the metal layer on the lower side in particular overlaps the source electrode largely.

Further, in an etch back method such as isotropic etching, there is a large variation in the etching rate, and it is difficult to form the characteristics of the thin film transistor uniformly, especially when applied to a large liquid crystal display device. was there.

As described above, the liquid crystal display device using the conventional thin film transistor has a problem that flicker and burn-in are likely to occur because the self-alignment between the source / drain electrode and the gate electrode is incomplete. In addition, the method using lift-off has a problem that the self-alignment is possible, but the yield is low. Further, in a thin film transistor having a gate electrode having a convex metal double-layer structure, there is a problem in that the gate-source capacitance is large and flicker or burn-in is likely to occur.

[0011]

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a thin film transistor having a high yield and excellent characteristics.

It is an object of the present invention to provide a thin film transistor having excellent characteristics that the parasitic capacitance between the source and the gate is small.

It is another object of the present invention to provide a method of manufacturing a thin film transistor having a high yield and uniform characteristics.

It is another object of the present invention to provide a liquid crystal display device having a thin film transistor which has excellent characteristics and is uniform even on a large screen, and which has less flicker and burn-in.

[0015]

A thin film transistor of the present invention comprises a light-shielding high resistance layer of a predetermined shape formed on a transparent insulating substrate, a gate electrode formed on the light-shielding high resistance film, A gate insulating layer formed from above the gate electrode, and a semiconductor layer formed on the gate insulating layer,
It is characterized by comprising a plurality of contact layers formed in a predetermined region on the semiconductor layer and a source electrode and a drain electrode formed on the contact layer.

These semiconductor layers, contact layers, sources,
The drain electrodes may be formed in self-alignment with each other.

Further, the light-shielding high resistance layer provided in the thin film transistor of the present invention may be made of SiGe. Further, the light shielding high resistance layer may be formed by forming a substrate protection film on a transparent insulating substrate and then forming the substrate protection film thereon. Further, the light-shielding high resistance layer and the end surface of the gate electrode may be formed in a tapered shape.

The gate insulating layer is, for example, SiOx or SiNx.
Alternatively, it may be formed by a laminated structure of these.

The method of manufacturing the thin film transistor of the present invention is
Forming a light-shielding high-resistance layer on a transparent insulating substrate and patterning it into a predetermined shape; forming a conductor layer on the upper side of this light-shielding high-resistance layer and patterning it into a gate electrode of a predetermined shape; A step of sequentially forming a gate insulating layer and a semiconductor layer on the upper side of the gate electrode and patterning each of these layers into a predetermined shape; a step of sequentially forming a contact layer and a conductor layer from the upper side of the formed semiconductor layer; And a step of removing the contact layer and the source / drain electrodes formed in Step 1.

Further, a channel protective layer is formed on the semiconductor layer, a contact layer and a conductor layer are sequentially formed thereon, and the contact layer and the source / drain electrodes formed above the channel protective layer are removed. You may

Further, the step of removing the contact layer and the conductor layer formed above the semiconductor layer may use a chemical mechanical polishing method.

The liquid crystal display device of the present invention comprises a high-resistance light-shielding layer of a predetermined shape formed on a transparent insulating substrate, a gate electrode formed on the light-shielding high-resistance film, and an upper side of the gate electrode. A gate insulating layer formed, a semiconductor layer formed on the gate insulating layer, a plurality of contact layers formed in predetermined regions on the semiconductor layer, and a source electrode and a drain electrode formed on the contact layer. And a thin film transistor.

These semiconductor layers, contact layers, sources,
The drain electrodes may be formed in self-alignment with each other.

That is, the thin film transistor of the present invention is characterized in that a light-shielding high resistance layer is adopted as a gate electrode supporting layer for supporting the gate electrode.

As a result, the parasitic capacitance between the source and gate electrodes is reduced. In particular, a substrate or a substrate protective layer,
In a thin film transistor in which a semiconductor layer, a contact layer, and a source / drain electrode are formed in a self-aligned manner by using a step with respect to a gate electrode, a margin for forming in a self-aligned manner is increased without increasing parasitic capacitance.

At the same time, by adopting a light-shielding film as the gate electrode support layer, light irradiation to the channel region is blocked,
Leakage current is reduced.

The method of manufacturing a thin film transistor according to the present invention is characterized by including the step of forming the light-shielding high resistance layer which is the above-mentioned gate electrode supporting layer, and
It is characterized in that a chemical mechanical polishing method is used when the semiconductor layer, the contact layer, and the source / drain electrodes are formed in a self-aligned manner by using the step between the substrate or the substrate protection layer and the gate electrode.

That is, in the present invention, first, the gate electrode portion is made to have a two-layer structure of a light-shielding high resistance layer and a conductor layer, and a transparent insulating substrate or a substrate protection layer formed thereon and a light-shielding high resistance layer, and It utilizes the step difference from the conductor layer. A gate insulating layer formed on the gate electrode, a semiconductor layer formed on the gate insulating layer, a contact layer formed on the semiconductor layer, and a conductor layer formed on the contact layer;
By sequentially flattening the previous conductor layer, contact region layer, and semiconductor layer using sputter etching, chemical mechanical polishing, etc., the previous conductor layer and contact layer are separated in conformity with the gate electrode pattern, A matched thin film transistor is formed. In particular, since the opaque high-resistance layer is used as the lower layer in the two-layer structure of the light-shielding high-resistance layer and the gate electrode, even if the gate electrode is a convex type, the parasitic capacitance between the gate and the source does not increase without increasing the light leakage current. The capacity can be reduced. Further, by supporting the gate electrode with the light-shielding high-resistance film, the margin for self-aligned formation becomes large.

Further, the etching rate can be made uniform by using the chemical mechanical polishing method. Therefore, the characteristics of a large number of thin film transistors on the TFT array are made uniform and the yield is improved. Especially when applied to a large-sized liquid crystal display device, both display quality and productivity are improved.

In the case of depositing SiGe, for example, the light-shielding high-resistance layer is patterned by forming a resist and then forming, for example, C.
The plasma etching method may be performed using F ₄ gas. At this time, if O2 gas is added to CF4 gas and introduced, it becomes easy to taper the end face.

Further, it may be processed by chemical leaching with hydrofluoric acid, hydrogen peroxide or acetic acid.

As a chemical mechanical polishing method for forming the semiconductor layer, the contact layer, and the source / drain electrodes in a self-aligned manner, for example, KOH,
It is also possible to use colloidal Si as an abrasive and melt-polish with urethane.

In the liquid crystal display device of the present invention,
By providing the thin film transistor having excellent characteristics as described above, flicker and image sticking are reduced, and display characteristics are uniform over the entire screen. Also, the yield is improved.

[0034]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view schematically showing an example of the thin film transistor of the present invention.

A substrate protection layer 10 is formed on the transparent insulating substrate 101.
2 is formed, a light shielding high resistance film 103 which is a gate electrode supporting layer is formed on the substrate protection layer 102, and a gate electrode 104 is formed on the light shielding high resistance film.
The light-shielding high resistance film 103 may be formed in a predetermined shape by depositing SiGe, for example. The gate electrode 104 may also be formed in a predetermined shape by depositing a metal layer having a low resistance and a high melting point, such as a Mo—Ta alloy.

A gate insulating layer 105 is formed from above the gate electrode 104, and a semiconductor layer 106 is formed on the gate insulating layer 105. A contact layer 107 having a predetermined shape for ohmic contact is formed on the semiconductor layer 106.
Is formed, and the source electrode 1 is formed on the contact layer 107.
08 and the drain electrode 109 are formed.

The gate insulating layer is, for example, SiOx or SiNx.
The film may be formed to have a single-layer structure, or may be formed to have a laminated structure of a SiOx layer and a SiNx layer. The semiconductor layer 106 is an amorphous silicon film (a-Si film)
May be used, or a non-single crystal silicon film (p-Si film) or the like may be used as necessary.

The contact layer 107 is, for example, n ⁺ a-Si.
May be formed into a film, and the source electrode 108 electrode,
The drain electrode 109 is, for example, M as in the gate electrode 104.
Alternatively, a metal such as o or Al may be formed by a sputtering method.

FIG. 2 is a diagram schematically showing an example in which the thin film transistor of the present invention is used as a pixel switching element of a liquid crystal display device.

In the thin film transistor illustrated in FIG. 2, the auxiliary capacitance section 120 is also formed in exactly the same manner as the thin film transistor illustrated in FIG. 121 is a pixel electrode.

The thin film transistor of the present invention can reduce the parasitic capacitance between the source and gate electrodes by such a structure. In particular, in a thin film transistor in which a semiconductor layer, a contact layer, and a source / drain electrode are formed in a self-aligned manner by using a step between a substrate or a substrate protective layer and a gate electrode, the self-alignment can be performed without increasing the parasitic capacitance. A large margin can be secured when forming, a more uniform characteristic of the thin film transistor is realized, and at the same time, productivity is improved.

Further, by adopting a light-shielding film as the gate electrode supporting layer, it is possible to block the light irradiation to the channel region and suppress the leak current.

FIG. 3 is a sectional view schematically showing an example of the manufacturing process of the thin film transistor of the present invention. FIG. 4 is a plan view of the thin film transistor of this embodiment.

First, a SiOx substrate protective layer 202 is deposited on a transparent insulating substrate 201 such as a glass substrate by sputtering or CVD.

Next, the light-shielding high-resistance film 2 is formed on the substrate protective layer.
Form 03. The light-shielding high resistance film 203 is formed by depositing SiGe by, for example, a plasma CVD method to form a resist,
For example, it may be patterned into a predetermined shape by a plasma etching method using CF ₄ gas. Also, CF ₄
If O ₂ gas is added to the gas and introduced, it becomes easy to taper the end face. In addition, hydrofluoric acid, hydrogen peroxide,
You may make it process by a chemical leaching method with acetic acid.

A gate electrode 204 is formed on the patterned light-shielding high resistance film 203. The gate electrode is, for example, M
A metal layer having a low resistance and a high melting point, such as an o-Ta alloy, may be deposited, a resist may be deposited on the metal layer and patterned, and the resist may be used as a mask for etching.

Further, the patterning of the light-shielding high resistance film 203 and the gate electrode 204 may be formed by one photolithography process. That is, the light-blocking high-resistance film 203 and the metal layer to be the gate electrode 204 may be sequentially deposited, and may be successively etched and patterned.

In this way, the light-shielding high-resistance film 203,
The gate electrode 204, the auxiliary capacitance electrode 205, and the gate extraction electrode 206 are formed, and the resist is peeled off (FIG.
(A)).

Next, it is continuously 300 nm by the CVD method or the like.
A gate insulating layer 207, an a-Si semiconductor layer 208 having a thickness of 300 nm, and an n ⁺ a-Si contact layer 209 having a thickness of 50 nm are formed. The film thickness of each layer may be designed as necessary. The gate insulating layer may be formed of SiOx, SiNx, or a laminated structure of these.

If the gate insulating layer 207, the semiconductor layer 208, and the contact layer 209 are sequentially deposited, after the dilute F treatment,
The metal layer 210 such as Mo and Al is sputtered to 400
nm.

Further, a resist is formed and patterned, and the resist is used as a mask to form the metal layer 210, n ⁺ a-S.
i contact layer 209, a-Si semiconductor layer 208, Si
Nx gate insulating layer 207b, SiOx gate insulating layer 20
7a is sequentially etched to form an island pattern and a signal line pattern, and the resist is peeled off (see FIG. 3B).

An insulating layer 211 is deposited on the formed island-shaped pattern and signal line pattern. As the insulating layer 211, SOG (spin on glass) may be used, for example (see FIG. 3C).

Further, the insulating layer 211 is flattened from the upper portion over the entire substrate by a chemical mechanical polishing method, sputter etching or the like. In this chemical mechanical polishing step, colloidal Si may be used as an abrasive in KOH, and may be polished with urethane (see FIG. 3D).

By this etching, in the thin film transistor portion, the signal line metal layer and the n ⁺ a-Si contact layer 209 are projected due to the step due to the light-shielding high resistance film 203 and the gate electrode 204, so that the signal line metal layer, n ⁺ a-
Si contact layer 209 and a-Si semiconductor layer 20
8 are sequentially etched. By this flattening process, the signal line metal layer and the n ⁺ a-Si contact layer 209 are formed on the a-Si.
The semiconductor layer 208 is removed until it is exposed. Through these steps, the semiconductor layer 208, the contact layer 209, and the source / drain electrodes 210 are formed in a self-aligned manner.

Next, a pixel electrode 212 consisting of an ITO layer is deposited to a thickness of 100 nm by a sputtering method or the like, and a resist is deposited and patterned thereon, and the ITO layer 212 is patterned using the resist as a mask to form a pixel electrode and signal line pattern. And further patterned ΙTO layer 2
12 and n ⁺ a-Si contact layer 209 and a-Si
The insulating layer 21 is formed using the semiconductor layer 208 and the metal layer 210 as a mask.
1 is etched to pattern the pixel electrode, and at the same time, the gate electrode lead-out portion or the auxiliary capacitance electrode lead-out portion is exposed (see FIG. 3E).

In particular, it is important for the ITO layer to form a two-layer structure with the signal line metal layer. If this signal line does not have a two-layer structure, the gate line has a total step difference of the metal layer 210 and the insulating layer 211 in this array, so that the signal line metal layer is connected at the cross portion 213 of the gate line and the signal line. Instead, they are connected by the second ITO layer 212. The insulating layer 211 may be peeled off before forming the ITO layer. In this case, the gate electrode lead-out portion 214 or the auxiliary capacitance electrode lead-out portion is exposed simultaneously with the patterning of the ITO layer 212.

After that, a polyimide film is deposited and an orientation process is performed to complete the array substrate. In this structure, the array substrate can be formed by performing the photolithography process three times or four times.

Further, this is combined with a counter substrate, and liquid crystal is injected and sealed to complete a liquid crystal display device.

FIG. 5 is a sectional view schematically showing a method of manufacturing a thin film transistor according to the present invention, and FIG. 6 is a partial diagram of FIG. FIG. 7 is a plan view schematically showing the thin film transistor manufactured in this example.

First, a SiOx substrate protective layer 302 is deposited on a transparent insulating substrate 301 such as a glass substrate by sputtering or CVD.

Next, a light-shielding high resistance film 303 is formed on the substrate protection layer 302 (see FIG. 5A). The light-shielding high resistance film 303 may be formed by depositing SiGe by, for example, a plasma CVD method, forming a resist, and patterning the resist into a predetermined shape by, for example, CF ₄ gas by a plasma etching method. Further, if O ₂ gas is added to CF ₄ gas and introduced, it becomes easy to taper the end face. Further, it may be processed by a chemical leaching method with hydrofluoric acid, hydrogen peroxide or acetic acid.

A gate electrode 304 is formed on the patterned light-shielding high-resistance film 303, and at the same time, electrodes are formed on the auxiliary capacitance section, the signal line / gate line cross section, and the gate line extraction section (see FIG. 5B). .

The electrodes may be formed by depositing a metal layer having a low resistance and a high melting point, such as a Mo-Ta alloy, depositing a resist on the metal layer, patterning the metal layer, and etching using the resist as a mask.

In this way, the light-shielding high-resistance film 303,
The gate electrode 304, the auxiliary capacitance electrode 305, and the gate extraction electrode 306 are formed, and the resist is peeled off.

By the above steps, a step is generated in the thin film transistor portion, and the step can be effectively used as described later,
In other regions, the step difference of the gate line becomes smaller, so that the disconnection of the signal line at the cross portion with the signal line can be prevented.
By using the light-shielding high-resistance film 304 as the gate electrode support layer, the leak current between the gate electrode and the source / drain electrodes to be formed later can be reduced, and the parasitic capacitance between the source / drain electrodes and the gate electrode can be reduced. Can also be smaller.

Next, a SiNx gate insulating layer 307 is deposited to a thickness of about 100 nm to 200 nm by, for example, the CVD method,
Further, a metal layer 30 such as Mo is formed by a sputtering method or the like.
No. 8 is deposited to a thickness of 50 nm, and n ^{+ a}
After the Si contact layer 309 is made to have a thickness of 50 nm and subjected to a dilute F treatment, a resist is deposited and patterned, and the n ⁺ a-Si contact layer 309 and the metal layer 308 are patterned using the resist as a mask. Then, the resist is peeled off.

Next, an ITO layer 310 is deposited to a thickness of 100 nm by a sputtering method or the like, a resist is further deposited and patterned, and the ITO layer 310 is patterned using the resist as a mask to form a pixel electrode and an auxiliary capacitor upper electrode.

Next, a resist is deposited and patterned to remove the upper portion of the gate electrode extraction portion 311 by etching,
The gate extraction electrode 306 is exposed. Then, the resist is peeled off (see FIG. 5C).

Next, an insulating layer 312 such as SOG is deposited on the entire substrate (see FIG. 5D). Then, the entire substrate is flatly etched from above by a chemical mechanical polishing method or sputter etching. At this time, in the thin film transistor portion, since the light-shielding high resistance film 303 is formed below the gate electrode 304, the gate electrode 3
04 only on the insulating layer 307, the metal layer 308, n ⁺ a-
The Si layer 309 projects in a convex shape, and these portions are selectively etched. n + a-Si generally has high hardness and is hard to be polished, but the n ⁺ a-Si layer 30
A metal layer 308 having a low hardness is provided under 9 to facilitate polishing. Therefore, the insulating layer 312, n ⁺
The a-Si layer 309, the metal layer 308, the SiNx insulating layer 3
It is removed until 07 is exposed (see FIG. 6E). After this step, the SOG insulating layer 312 is peeled off.

Next, a metal layer of Mo, Al, etc. is deposited to a thickness of 400 nm by a sputtering method or the like, and a resist is further deposited.
The patterned metal layer is patterned by using the resist as a mask, and the resist is peeled off to form the signal line 313.

Next, after a dilute F treatment, an a-Si semiconductor layer 314 of 300 nm and a SiX insulating layer 315 of 50 nm are deposited by the CVD method or the like, and a metal layer 316 of Cr or the like serving as a light shielding layer is further deposited (FIG. 6 (f)).

Then, a resist is deposited on these deposited films and patterned, and the metal layer 31 is formed using the resist as a mask.
6 is patterned to form a light shielding layer, and the a-Si semiconductor layer 314 is further patterned to form an a-Si island pattern (see FIG. 6G).

Next, the insulating layer 31 such as SiNx is formed by the CVD method or the like.
7 is deposited to 200 nm. Then, a resist is deposited and patterned, and the insulating layer 317 is used with the resist as a mask.
Pattern. As a result, the gate electrode lead-out portion and the signal line electrode lead-out portion are exposed. Then, the resist is peeled off (see FIG. 6E).

After that, a polyimide film is deposited and an orientation process is performed to complete the array substrate 319.

Further, the array substrate 319 and the counter substrate 320 on which the counter electrode is formed are combined and the liquid crystal 321 is injected and sealed to complete the liquid crystal display device.

FIG. 8 shows an example of the liquid crystal display device manufactured as described above.

FIG. 9 is a sectional view schematically showing a method of manufacturing a thin film transistor according to the present invention, and FIG. 10 is a partial diagram of FIG. 11 is a plan view schematically showing the thin film transistor of the present invention manufactured in this example.

First, a SiOx substrate protective layer 402 is deposited on a transparent insulating substrate 401 such as a glass substrate by sputtering or CVD.

Next, a light-shielding high resistance film 403 is formed on the substrate protection layer 402 (see FIG. 9A). The light-shielding high resistance film 403 may be formed by depositing SiGe by, for example, a plasma CVD method, forming a resist, and patterning it into a predetermined shape by, for example, a CF ₄ gas by a plasma etching method. Further, if O ₂ gas is added to CF ₄ gas and introduced, it becomes easy to taper the end face. Further, it may be processed by a chemical leaching method with hydrofluoric acid, hydrogen peroxide or acetic acid.

A gate electrode 404 is formed on the patterned light-shielding high-resistance film 403, and at the same time, electrodes are formed on the auxiliary capacitance section, the signal line / gate line cross section, and the gate line extraction section (see FIG. 9B). .

The electrodes may be formed by depositing a metal layer having a low resistance and a high melting point, such as a Mo-Ta alloy, depositing a resist on the metal layer, patterning the metal layer, and etching using the resist as a mask.

In this way, the light-shielding high-resistance film 403,
The gate electrode 404, the auxiliary capacitance electrode 405, and the gate extraction electrode 406 are formed, and the resist is peeled off.

The steps described above cause a step in the thin film transistor portion, and the step can be effectively utilized as described later.
In other regions, the step difference of the gate line becomes smaller, so that the disconnection of the signal line at the cross portion with the signal line can be prevented.
By using the light-shielding high-resistance film 404 as the gate electrode support layer, the leak current between the gate electrode and the source / drain electrodes to be formed later can be reduced, and the parasitic capacitance between the source / drain electrodes and the gate electrode can be reduced. Can also be smaller.

Next, the gate insulating layers 405 and 30 having a thickness of 300 nm are continuously formed, for example, by the CVD method without breaking the vacuum.
0 nm a-Si semiconductor layer 407, 50 nm n ⁺ a-
The Si contact layer 408 is formed. Further, after the dilute F treatment, a 50 nm Io layer 409 is formed by, for example, a sputtering method and annealed to form a silicide. As the gate insulating film, a SiOx layer or a SiNx layer may be formed, or a laminated structure of these may be formed.

Further, a resist is deposited and patterned, and using the resist as a mask, the Mo layer 409, n ⁺ a-S
The i layer 408, the a-Si layer 407, and the SiNx gate insulating layer 406 are sequentially etched to form an island pattern.
The resist is peeled off (see FIG. 9C).

Next, an I / O layer 410 is deposited to a thickness of 100 nm by a sputtering method or the like, a resist is deposited and patterned thereon, and the ITO layer 410 is patterned using the resist as a mask. Forming the upper electrode of.

Next, a resist is deposited and patterned by mask exposure, the SiOx layer 405 above the gate electrode extraction portion is etched using the resist as a mask, and the resist is peeled off to expose the gate electrode extraction portion 411. (See FIG. 9D).

Next, after peeling off the Mo layer 409,
A metal layer 412 of, for example, Mo or Al is formed by a sputtering method or the like.
Is deposited to 400 nm. Then, a resist is deposited and patterned thereon, the metal layer 412 is patterned using the resist as a mask, and the resist is peeled off to form a signal line electrode and a gate electrode extracting electrode.

Further, an insulating layer 413 is deposited on this.
An SOG layer may be used as the insulating layer 413 (see FIG. 9F).

Further, the insulating layer 413 is etched from above on the entire substrate by a chemical mechanical polishing method, sputter etching or the like. By this etching, the light-shielding high resistance film 40 is formed in the thin film transistor portion.
3 and the step formed by the gate electrode 404, the signal line metal layer 4
12 and the n ⁺ a-Si layer 408 are projected, the signal line metal layer 412, the n ⁺ a-Si layer 408, and the a-S
The i layer 407 is sequentially etched. Therefore, by this etching, the signal line metal layer 412 and the n ⁺ a-Si layer are a-
The Si layer 407 is removed until it is exposed. At this time, the step difference between the light-shielding high-resistance film 403 and the gate electrode 404 increases the etching margin, improving the productivity (see FIG. 9G).

Next, an insulating layer 414 is deposited, a resist is further deposited and patterned, the insulating layer 414 and the insulating layer 413 are etched using the resist as a mask, the resist is peeled off, and the signal line lead-out portion 415 is exposed. To do. Further, when polyimide is used as the insulating layer 414,
The alignment film may be formed by rubbing the insulating layer. When the insulating layer 414 is not polyimide, polyimide may be deposited on the insulating layer 14 and rubbed to form the alignment film.
(See FIG. 9H) Since the insulating layer 414 is on the planarized insulating layer 413, the entire substrate is planarized. Therefore, since the alignment film is flat on the entire screen, disclination can be prevented when the liquid crystal is aligned.

A counter substrate composed of a color filter layer and an ITO layer was combined with this substrate, and liquid crystal was injected between them.
The liquid crystal display device is completed by sealing.

[0094]

As described above, the thin film transistor of the present invention has the laminated structure of the light-shielding high resistance film and the gate electrode to reduce the parasitic capacitance between the source and the gate without increasing the leak current. You can

Further, the thin film transistor of the present invention is provided with a laminated structure of a light-shielding high resistance film and a gate electrode, so that a large margin can be taken when the semiconductor layer, the channel region, and the source / drain electrodes are formed in a self-aligned manner. It is possible to improve productivity.

According to the method of manufacturing a thin film transistor of the present invention, a thin film transistor having uniform characteristics can be formed over the entire substrate, and the characteristics and productivity of the thin film transistor can be improved.

Further, in the liquid crystal display device of the present invention, the entire array substrate is formed uniformly, and display characteristics with excellent characteristics can be obtained even in a large area. Further, flicker and image sticking can be reduced, and at the same time, productivity can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing a thin film transistor of the present invention.

FIG. 2 is a sectional view schematically showing a thin film transistor of the present invention.

FIG. 3 is a cross-sectional view schematically showing a method of manufacturing the thin film transistor of the invention.

FIG. 4 is a plan view schematically showing a thin film transistor of the present invention.

FIG. 5 is a cross-sectional view schematically showing a method of manufacturing a thin film transistor of the present invention.

FIG. 6 is a division diagram of FIG.

FIG. 7 is a plan view schematically showing a thin film transistor of the present invention.

FIG. 8 is a sectional view schematically showing an example of a liquid crystal display device of the present invention.

FIG. 9 is a sectional view schematically showing a method of manufacturing a thin film transistor of the present invention.

FIG. 10 is a division diagram of FIG. 9.

FIG. 11 is a plan view schematically showing a thin film transistor of the present invention.

FIG. 12 is a sectional view schematically showing an example of a conventional thin film transistor.

[Explanation of symbols]

101 ... Transparent insulating substrate, 102 ... Substrate protective layer 103 ... Light-shielding high resistance film, 104 ... Gate electrode, 1
05 ... Gate insulating layer 106 ... Semiconductor layer, 107 ... Contact layer, 108
...... Source electrode 109 ...... Drain electrode 120 ...... Auxiliary capacitance part 12
1 ... Pixel electrode 201 ... Transparent insulating substrate, 202 ... Substrate protective layer, 2
03 ... Light-shielding high-resistance film 204 ... Gate electrode, 205 ... Auxiliary capacitance electrode 206 ... Gate extraction electrode, 207 ... Gate insulating layer, 208 ... Semiconductor layer 209 ... Contact layer, 210 ... Source Drain electrode, 211 ... Insulating layer 212 ... Pixel electrode 301 ... Transparent insulating substrate, 302 ... Substrate protective layer, 3
03 ... Light-shielding high resistance film 304 ... Gate electrode, 305 ... Auxiliary capacitance electrode 306 ... Gate extraction electrode, 307 ... Gate insulating layer, 308 ... Metal layer 309 ... Contact layer, 310 ... ITO layer 311 ... Gate electrode extraction part, 312 ... Insulating layer (SOG) 313 ... Signal line, 314 ... Semiconductor layer, 315 ... Insulating layer, 316 ... Metal layer 317 ... Insulating layer, 320 ... Counter substrate , 321 ... liquid crystal 401 ... transparent insulating substrate, 402 ... substrate protective layer, 4
03 ... Light-shielding high-resistance film 404 ... Gate electrode, 405 ... Auxiliary capacitance electrode 406 ... Gate extraction electrode, 407 ... Semiconductor layer,
408 ... Contact layer 409 ... Mo layer, 410 ... ITO layer, 411 ... Gate electrode extraction part 412 ... Metal layer, 413 ... Insulating layer (SOG), 41
4 ... Insulating layer 415 ... Signal line extraction part 1101 ... Substrate protective layer 1102 ... Gate electrode, 1
103 ... Gate insulating layer 1104 ... Semiconductor layer, 1105 ... Contact layer 1106 ... Source / drain electrodes

Claims (5)

[Claims] 1. A light-shielding high resistance layer formed on a transparent insulating substrate, a gate electrode formed on the light-shielding high resistance film, and a gate insulating layer formed from above the gate electrode, A semiconductor layer formed on the gate insulating layer, a plurality of contact layers formed in a predetermined region on the semiconductor layer, and a source electrode and a drain electrode formed on the contact layer. And a thin film transistor. 2. The thin film transistor according to claim 1, wherein the light-shielding high-resistance layer is SiGe. 3. A step of forming a light-shielding high-resistance layer on a transparent insulating substrate and patterning it; a step of forming a conductor layer on the upper side of the light-shielding high-resistance layer and patterning it on a gate electrode; A step of sequentially forming a gate insulating layer and a semiconductor layer on the electrode and patterning each of these layers; a step of sequentially forming a contact layer and a conductor layer from the upper side of the semiconductor layer; and a step of being formed above the semiconductor layer. And a step of removing the contact layer and the source / drain electrodes. 4. The method of manufacturing a thin film transistor according to claim 3, wherein the step of removing the contact layer and the conductor layer formed above the semiconductor layer uses a chemical mechanical polishing method. 5. A light-shielding high resistance layer formed in a predetermined shape on a transparent insulating substrate, a gate electrode formed on the light-shielding high resistance film, and a gate formed from above the gate electrode. An insulating layer, a semiconductor layer formed on the gate insulating layer, a plurality of contact layers formed on the semiconductor layer, and a thin film transistor including a source electrode and a drain electrode formed on the contact layer. A liquid crystal display device characterized by the above.