JPH0982904A - Dynamic type storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DRAM which can reduce the area per unit cell and the failure due to imperfect bit line contact. SOLUTION: This dynamic storage device is formed via the following; an active area for an MOS transistor which is formed on a semiconductor substrate 10, a word line WL which is formed on a channel region via a gate insulating film 20 and has a gate electrode part G, a bit line BL which is formed in contact with a drain region, and interlayer insulating films 21, 22 on the first bit line and the word line. The device is provided with a capacitor electrode 6 which is formed in contact with a source region, a capacitor plate electrode 8 which is formed on the capacitor electrode via a capacitor insulating film 24 and has almost the same plane form as the capacitor electrode, and a second bit line/BL which is formed in contact with the upper surface of the capacitor plate electrode and makes a complementary pair with the first bit line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly to a structure of a bit line plate memory cell (BIP cell) in a dynamic memory and a forming method thereof.

[0002]

2. Description of the Related Art FIG. 8 shows an equivalent circuit of a one-transistor / one-capacitor memory cell (DRAM cell) of a dynamic random access memory (DRAM). In FIG. 8, Tr is an N-channel MOS transistor for charge transfer gate, and Cs is a capacitor for charge storage. The drain of the transistor Tr is connected to the bit line BL, the gate thereof is connected to the word line WL, the source thereof is connected to one end of the capacitor Cs, and the other end (plate electrode) of the capacitor Cs is usually a predetermined voltage VPL. Fixed to.

At the time of writing to the DRAM cell, a voltage is applied to the word line WL for a certain period of time, and the transistor Tr is turned on during that period, so that the bit line BL is
The electric charge from is stored in the capacitor Cs. Further, when reading data from the DRAM cell, a voltage is applied to the word line WL for a certain period, and the transistor T
By turning on r, the accumulated charge of the capacitor Cs is discharged to the bit line BL.

Such a read method of the DRAM cell uses only the charge on one end side of the cell capacitor Cs. On the other hand, a method has been proposed in which charges at both ends of the cell capacitor Cs are effectively used when reading cell data, and a method using a bit line plate type memory cell (hereinafter referred to as a BIP cell) is proposed as an example. Will be explained.

In the BIP cell, as shown in FIG. 9, a 1-transistor / 1-capacitor type DRAM cell is connected between complementary bit line pairs, that is, one end of the transistor Tr is one bit line BL or /. Connected to BL,
One end of the capacitor Cs is connected to the other bit line / BL or BL forming a complementary pair with respect to the above bit line. L. Arzubi, WDLoehlein, IBM Technical Di
sclosure Bulltein, vol 23, Nov. 1980, pp2331-2332
Is disclosed in.

FIG. 9 shows a part of a cell array in a DRAM using the array of BIP cells and a part of peripheral circuits connected thereto. Here, MC is a BIP cell, WL is a word line, BL and / BL are bit line pairs, VBL is a bit line precharge voltage, / EQL is a bit line precharge signal, PR is a bit line precharge circuit, and SA. Is a sense amplifier, CSL is a column selection signal, CQ is a column switch, and DQ and / DQ are data line pairs commonly connected to a plurality of columns. As the sense amplifier, for example, a latch type sense amplifier including a PMOS sense amplifier and an NMOS sense amplifier is used, and SAP is P
MOS sense amplifier drive control signal, / SAN is NMOS
This is a sense amplifier drive control signal.

FIGS. 10 (a) and 10 (b) are timing waveform charts showing the results of simulation for an example of the read operation of "1" data and "0" data of the BIP cell, respectively. Here, the cell capacitor Cs
Is assumed to be 10 fF, and each capacitance value CBL of the bit lines BL and / BL is 200 fF, and the voltage of the storage node of the cell (the connection point between the transistor Tr and the capacitor Cs) is represented by Vc. There is.

Next, referring to FIGS. 9 and 10,
An example of the read operation of the BIP cell will be briefly described. After the bit line pair BL, / BL has been set to the voltage VBL by the precharge circuit PR, the selected word line WL
When the voltage rises, the transistor Tr of the cell connected to it turns on, the storage node N of the cell and one bit line (BL or / BL) are connected via this transistor Tr, and the storage of the cell The potential of the one bit line (BL or / BL) changes according to the data.

In this case, the storage node N of the cell is connected to the other bit line (/ BL or B via the cell capacitor Cs).
L), the other bit line (/ BL
Or BL is one of the bit lines (BL or /)
The potential changes in the opposite direction to (BL).

As described above, the potential difference generated between the bit line pair BL, / BL according to the data of the BIP cell is differentially amplified and latched by the sense amplifier SA, and further the data is passed through the selected column selection switch CQ. Line pair DQ, /
Read to DQ.

In the above operation, the bit line pair B
Signal voltage Vsig (BIP), which is the potential difference between L and / BL
Becomes as shown in the following equation (1) depending on the voltage Vc charged as data in the storage node N of the cell. The larger this value, the more stable the operation of the DRAM.

Vsig (BIP) = (Vc−VBL) ² · Cs / (CBL + 2 · Cs) (1) Effective use of charges at both ends of the cell capacitor Cs when reading data from such a BIP cell Therefore, it is known that Vsig (BIP) is about twice as large as that of a DRAM in which the voltage of the plate electrode on one end side of the cell capacitor Cs is fixed.

Further, when the data of the BIP cell is read as described above, the voltage of the bit line pair BL, / BL is again changed to the voltage VBL by the precharge circuit PR after the sense amplifier SA operates and the cell data is read. At the time of initialization, the voltage Vc stored as data in the storage node N of the cell is amplified by charge coupling with the bit line pair (BL or / BL) connected to the cell capacitor Cs.

Due to this effect, the amount of charges emitted from the BIP cell to the bit line at the next read of cell data can be increased, that is, the signal voltage Vsig (BIP) shown in the above equation (1) can be increased. Therefore, the stable operation of the DRAM can be obtained.

Further, even if the word line voltage is not boosted, the data can be written in the memory node of the cell without lowering the threshold value of the cell transistor Tr. It is possible to suppress the deterioration of breakdown voltage characteristics and to reduce the thickness of the gate insulating film.

By the way, the above-mentioned document (IBM Technical
Disclosure Bulltein, vol 23, Nov. 1980, pp2331-23
32) discloses a cell structure of a BIP cell based on a 64K (km) DRAM, which is directly applied to a BIP cell based on a G (giga) bit class MOS type DRAM cell in recent years. Has the following problems.

FIG. 11 shows a bit line prefabricated DRAM cell in which a bit line is formed before the cell capacitor of the BIP cell when a large capacity DRAM is realized by adopting the cell structure of the conventional BIP cell. FIG. 2 schematically shows a part of a plane pattern (4 rows × 2 columns) of a memory cell array that can be considered when adopted.

12 (a) and 12 (b) respectively show a schematic sectional structure including an SDG region along the line AA in FIG. 11 and a sectional structure including a cell capacitor along the line BB in FIG. Is shown in. Further, FIG. 12C shows an equivalent circuit of FIG.

In FIGS. 11 and 12A to 12C, a plurality of element regions (activation regions) SDG formed on the surface layer portion of the semiconductor substrate (for example, a silicon substrate) or on the semiconductor layer are each word. It has a predetermined length and a width F in one direction diagonally intersecting the line forming direction and the bit line forming direction orthogonal to the line forming direction, and is formed in a matrix arrangement on the surface layer portion of the semiconductor substrate when viewed in plan. There is. In this case, the element region interval in the direction orthogonal to the length direction of the element region SDG is equal to the width F of the element region.

Each of the element regions SDG is a MOS transistor Tr of one BIP cell in the region from the center to one end side.
A first drain / channel / source region is formed, and another BI is formed in the region from the central portion to the other end side.
Second drain for P cell MOS transistor Tr
A channel / source region is formed, and the central portion is a drain region common to the two MOS transistors.

The gate insulating film 20 is formed on each central portion (channel region) of the plurality of MOS transistors in the same row.
A word line WL having a width F (indicated by a symbol G in FIG. 12A for the gate electrode portion of the MOS transistor) is formed so as to pass through each of the above central portions. In this case, the word lines WL groups are formed in parallel at equal intervals F.

A first interlayer insulating film 2 is formed on the word line WL group.
1, a lower bit line (BL or / BL) group having a width F is formed in a direction orthogonal to the formation direction of the word line WL group, and each bit line BL is a plurality of columns in the same column. It is formed so as to contact the impurity diffusion region (drain region) 23 at the center of each of the individual element regions SDG. In this case, two BIP cells are connected to one bit line contact portion BC.

Further, at both ends of the device region SDG, cell capacitors Cs having a stack structure for each BIP cell are provided.
Charge storage part (capacitor electrode 6, cell storage node)
And the capacitor electrode 6 is formed so as to cover the gate electrode G of the BIP cell.

That is, the second interlayer insulating film 22 is formed on the bit line BL group on the lower layer side. In the second interlayer insulating film 22, one end side impurity diffusion region (source region) of the cell transistor is formed. ) 23, a contact hole is opened correspondingly. Then, after the conductive plug is embedded in the contact hole and the conductive film is formed on the second interlayer insulating film 22, the conductive film is formed by BIP.
The capacitor electrode 6 is formed by patterning into a predetermined rectangular shape so as to cover above the gate electrode of the cell.

Then, a capacitor plate electrode is formed on the capacitor electrode 6 through the capacitor insulating film 24 and in a direction orthogonal to the formation direction of the word lines WL group, that is, in a direction parallel to the bit line on the lower layer side. An upper layer bit line (/ BL or BL) group which is also used is formed.

In FIG. 11, bit line / BL on the upper layer side
The mutual distance Ls is the minimum processing interval determined by the accuracy of the photolithography process in the manufacturing process. By the way, when forming an array of BIP cells as described above, there may be a deviation in pattern alignment between the charge storage portion (capacitor electrode) and the upper bit line due to variations (fluctuations) in the manufacturing process. If a part of the capacitor electrode 6 is exposed due to the deviation of the pattern alignment, the capacitance value of the cell capacitor is reduced by the exposed area. Therefore, it is necessary to have a sufficient pattern alignment margin La between the capacitor electrode 6 and the capacitor plate electrode / BL, which hinders the miniaturization of the device by that much, which is disadvantageous in further integration of the DRAM. .

[0027]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and even when the pattern alignment between the capacitor electrode of the BIP cell and the bit electrode on the upper layer side is deviated, the cell capacitor is formed. The dynamic memory and its manufacturing method capable of reducing the area per unit cell because it is not necessary to give a margin for the above pattern matching because the capacitance value of the cell remains constant and high integration of the cell capacitor is possible. The purpose is to provide.

[0028]

A dynamic memory according to the present invention is formed in a surface layer portion of a semiconductor substrate or in a semiconductor layer in a direction oblique to a word line forming direction and a bit line forming direction orthogonal to the word line forming direction in plan view. And MOS
An active region having a drain-channel-source region forming a straight line forming a transistor; a first bit line formed so as to contact the drain region of the MOS transistor; and a channel region of the MOS transistor. A word line having a gate electrode portion formed via a gate insulating film and a source region of the MOS transistor are formed so as to be in contact with each other, and an interlayer insulating film is provided on the first bit line and the word line, and A capacitor electrode formed to have a predetermined pattern, a capacitor plate electrode formed on the capacitor electrode via a capacitor insulating film, and having a substantially same planar shape as the capacitor electrode; Is formed in contact with the surface and with respect to the first bit line Characterized by comprising a second bit line that forms a complementary pair.

Further, the dynamic memory of the present invention is
Two drain channels that are formed in a surface layer portion of the semiconductor substrate or in a semiconductor layer in a direction that obliquely intersects the word line formation direction and the bit line formation direction orthogonal to the word line formation direction and that form MOS transistors, respectively. An active region having a source region formed in a straight line and having a common drain region in the central portion, a cell array region in which a plurality of the active regions are formed in a matrix arrangement, and the cell array region in the same row. A plurality of word lines formed in a direction parallel to each other, each having a gate electrode portion formed on a channel region of each MOS transistor in a plurality of active regions via a gate insulating film, and the cell array region. Parallel lines formed to contact a common drain region in a plurality of active regions in the same column A plurality of first bit lines formed on the first bit line, an interlayer insulating film formed on the first bit line and the word line, and a portion of the interlayer insulating film corresponding to the source region are opened. A conductive plug buried in the contact hole and in contact with the source region; a capacitor electrode electrically connected to the conductive plug and having a predetermined pattern on the interlayer insulating film; A capacitor plate electrode formed on the capacitor electrode via a capacitor insulating film and having substantially the same planar shape as the capacitor electrode, and an upper surface of a plurality of capacitor plate electrodes in the same column of the cell array region, respectively, A second bit line formed in a direction parallel to the first bit line and formed in a direction parallel to each other. And wherein the Rukoto.

According to the method of manufacturing a dynamic memory of the present invention, the word line forming direction and the bit line forming direction orthogonal to the word line forming direction in the surface layer portion or the semiconductor layer of the semiconductor substrate are respectively obliquely intersected with each other. MO
Two drain channels that make up the S-transistor
Forming a cell array region by arranging a plurality of active regions having a source region formed in a straight line and having a common drain region in a central portion to form a cell array region; Forming a plurality of word lines having gate electrode portions formed on the channel region of each MOS transistor in the active region of the MOS transistor in a direction parallel to each other, and forming a first interlayer on the word line. A step of forming an insulating film and a plurality of first bit lines contacting a common drain region in a plurality of active regions in the same column of the cell array region are parallel to each other on the first interlayer insulating film. Direction, a step of forming a second interlayer insulating film on the first bit line and the first interlayer insulating film, and a step of forming the second interlayer A step of forming a contact hole in a portion of the edge film and the first interlayer insulating film corresponding to the source region, and filling a conductive plug in the opened contact hole to contact the source region. A step of sequentially forming a first conductive film for forming a capacitor electrode, an insulating film for forming a capacitor insulating film, and a second conductive film for forming a capacitor plate electrode on the second interlayer insulating film, A cell capacitor forming step of patterning the second conductive film, the insulating film, and the first conductive film using a photolithography technique and an anisotropic etching technique, and a plurality of capacitors in the same column of the cell array region. Forming second bit lines in contact with the upper surface of the plate electrode and in directions parallel to the first bit lines and parallel to each other. Characterized by comprising a degree.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION In the DRAM of the present invention, B
A capacitor plate electrode is formed on the capacitor electrode of each IP cell so as to have substantially the same size at the same plane position as the capacitor electrode via a capacitor insulating film, and the capacitor plate of a plurality of BIP cells in the same column. A bit line group on the upper layer side is formed so as to be in electrical contact with and continuous with the electrodes.

According to such a structure, when the array of BIP cells as described above is formed, the pattern alignment between the capacitor electrode and the bit line on the upper layer side is deviated due to the variation (fluctuation) in the manufacturing process. However, since the capacitance value of the cell capacitor remains constant, there is no need to provide a margin for the above pattern alignment, and high integration of the cell capacitor is possible, so the area per unit cell can be reduced. become.

Further, in the method of manufacturing a DRAM of the present invention, after the formation on the first bit line, the second interlayer insulating film is formed and the conductive plug contacting the source region of the MOS transistor is buried. Thereafter, a first conductive film for forming a capacitor electrode, an insulating film for forming a capacitor insulating film, and a second conductive film for forming a capacitor plate electrode are sequentially formed on the second interlayer insulating film, and photolithography is performed. The second conductive film, the insulating film, and the first conductive film are patterned by using the technique and the anisotropic etching technique.

At this time, since the capacitor plate electrode, the capacitor insulating film, and the capacitor electrode electrically connected to the conductive plug are formed by self-alignment, it is possible to obtain the capacitor plate electrode having substantially the same planar shape as the capacitor electrode.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a large-capacity D realized by adopting the cell structure of the BIP cell according to the embodiment of the present invention.
FIG. 10 schematically shows a part of a plane pattern of a part (4 rows × 2 columns) of the memory cell array in the RAM as shown in FIG. 9, for example.

Here, a bit line prefabrication type DRAM in which the bit line is fabricated before the cell capacitor of the BIP cell.
The example which adopted the cell is shown. 2 and 3 respectively schematically show the cross-sectional structure including the SDG region along the line AA in FIG. 1 and the cross-sectional structure including the cell capacitor along the line BB in FIG. 1, respectively.

The structure shown in FIGS. 1 to 3 is (1) BI as compared with the structures shown in FIGS. 11 and 12A and 12B.
(2) Capacitor plate electrodes of a plurality of BIP cells in the same column, in which a capacitor plate electrode is formed on the capacitor electrode for each P cell so as to have substantially the same planar shape as the capacitor electrode via a capacitor insulating film. Since the bit lines on the upper layer side are formed so as to be in electrical contact with and continuous with each other, the other points are the same.
12A and 12B, the same reference numerals are given.

That is, in FIG. 1 to FIG. 3, a plurality of element regions (activation regions) SDG formed on the surface layer portion of the semiconductor substrate (eg, silicon substrate) or on the semiconductor layer are
Each has a predetermined length and width in one direction diagonally intersecting the word line formation direction and the bit line formation direction orthogonal to the word line formation direction, and is formed in a matrix arrangement on the surface layer of the semiconductor substrate when viewed in plan. ing. Reference numeral 11 is an element isolation region.

In each of the element regions SDG, a first drain / channel / source region that constitutes a MOS transistor of one BIP cell is formed in a region on one end side from the central portion, and the central region and the other end are formed. Another B in the side area
A second drain / channel / source region that constitutes the MOS transistor of the IP cell is formed, and the central portion is a drain region common to the two MOS transistors.

The gate insulating film 20 is formed on each central portion (channel region) of the plurality of MOS transistors in the same row.
A word line WL having a width F (the gate electrode portion of the MOS transistor is shown by a symbol G in FIG. 2) having a width F is formed so as to pass through each of the above central portions. In this case, the word lines WL groups are formed in parallel at equal intervals F.

Further, the insulating film 2 is formed on the word line WL group.
1, a lower bit line (BL or / BL) group having a width F is formed in a direction orthogonal to the formation direction of the word line WL group, and each bit line BL is a plurality of columns in the same column. It is formed so as to contact the impurity diffusion region (drain region) 23 at the center of each of the individual element regions SDG.

Further, cell capacitors Cs having a stack structure for each BIP cell are provided at both ends of the device region SDG.
Charge storage part (capacitor electrode 6, cell storage node)
Are connected, and the capacitor electrode 6 is formed so as to cover above the gate electrode of the BIP cell.

That is, the interlayer insulating film 21 is formed on the bit line BL group on the lower layer side, and the interlayer insulating film 21 is formed.
A contact hole is formed in the impurity diffusion region (source region) 23 at one end of the cell transistor. Then, a conductive plug 5 is buried in the contact hole, a conductive film is formed on the interlayer insulating film 21, and then the conductive film is patterned into a predetermined square so as to cover above the gate electrode of the BIP cell to form a capacitor electrode. It is 6.

The capacitor electrode 6 is formed on the capacitor electrode of each BIP cell through the capacitor insulating film 24.
Capacitor plate electrode 8 is formed to have substantially the same planar shape as.

Then, the capacitor plate electrodes 8 of a plurality of BIP cells in the same column are electrically contacted and continuous, and in the direction orthogonal to the forming direction of the word lines WL group, that is, the lower layer side. Group of bit lines (/ BL or BL) on the upper layer side is formed in a direction parallel to the bit lines of. Note that, in FIG. 1, the distance Ls between the bit lines / BL on the upper layer side is the minimum processing interval determined by the lithography accuracy in the manufacturing process.

In the DRAM of the above-described embodiment, the capacitor plate electrode 8 is formed on the capacitor electrode 6 of each BIP cell so as to have substantially the same plane shape as the capacitor electrode via the capacitor insulating film 24, and the same. Bit line / BL groups on the upper layer side are formed on the capacitor plate electrodes 8 of the plurality of BIP cells in the column so as to be electrically connected and continuous.

According to such a structure, when the array of BIP cells as described above is formed, the pattern alignment between the capacitor electrode 6 and the bit line / BL on the upper layer side is deviated due to variations (fluctuations) in the manufacturing process. Even if it occurs, the capacitance value of the cell capacitor remains constant, there is no need to provide the above-mentioned pattern alignment margin (La in the conventional example), and high integration of the cell capacitor becomes possible. It is possible to reduce the area of.

4 and 5 show B shown in FIGS. 1 to 3.
4 shows a part of a wafer cross section in an example of a manufacturing process of an IP cell. Next, referring to FIG. 4 and FIG.
The manufacturing process of the P cell will be described.

First, as shown in FIG.
An array of BIP cell MOS transistors is formed on the silicon substrate 10 by the same process as the RAM cell forming process. Here, 11 is an element isolation region selectively formed in the substrate surface layer portion, and 23 is a drain / source formed of an impurity diffusion layer having a conductivity type opposite to that of the substrate formed in the element formation region in the substrate surface layer portion selectively. A region, 20 is a gate insulating film for a MOS transistor formed on the surface of the substrate on the drain-source channel region, G is a gate electrode for the MOS transistor formed on the gate insulating film 20 (one of the word lines WL). Section).

Next, a first layer is formed on the substrate including the gate electrode G.
An interlayer insulating film 21 is formed, and a bit line contact hole is formed in the first interlayer insulating film corresponding to the drain region. Further, a conductive film is buried in the contact hole for the bit line, a conductive film is formed on the first interlayer insulating film 21, and this is patterned to form the bit line BL on the lower layer side.

Next, the second interlayer insulating film 22 is formed on the substrate including the bit lines on the lower layer side, and the second interlayer insulating film 23 and the first interlayer insulating film 21 corresponding to the source regions are used for capacitor plugs. Contact holes are formed. further,
A conductive plug (tungsten or conductive polysilicon) 5 is embedded in the contact hole for the capacitor plug.

At this time, in order to prevent diffusion from the conductive plug 5 to the impurity diffusion layer 23 for the source region, a Ti / TiN laminated layer as a barrier metal 71 is previously formed on the inner wall of the contact hole so as to cover the conductive plug 5. A film is formed. Further, when the conductive plug 5 is embedded, the conductive plug forming conductive film and the barrier metal forming conductive film deposited on the second interlayer insulating film 22 are removed and the second interlayer insulating film 22 is removed. CMP (Chemical Mechanical Polishing) technique is used to sufficiently planarize the surface.

Next, as shown in FIG. 4B, the second
The capacitor electrode 6 is formed on the entire surface of the substrate including the interlayer insulating film 22.
A first conductive film for forming, an insulating film for forming the capacitor insulating film 24, and a second conductive film for forming the capacitor plate electrode 8 are sequentially formed.

At this time, the insulating film for forming the capacitor insulating film 24 is more suitable as the film thickness is thinner and the dielectric constant is higher in order to secure a required capacitance value and to achieve a stable operation of the BIP cell. , 5 when using the same SiO ₂ film as the conventional one
nm is the limit. If the film thickness of the SiO ₂ film is smaller than this, the current flowing through the SiO ₂ film increases and the cell data is destroyed.

Therefore, as an alternative to the SiO ₂ film, for example, a TaO ₅ film, a laminated film of Si ₃ N ₄ and a SiO ₂ film, or the like has been proposed. These are ₂ to 4 nm in terms of SiO ₂ film. The film thickness of the degree is obtained. At this time, conductive polysilicon or tungsten is used as the conductive film for forming the capacitor electrode 6 and the conductive film for forming the capacitor plate electrode 8.

[0056] Further, as an alternative to the SiO ₂ film, referred to as BST film (Ba, Sr) Using TiO ₃ film, a film thickness of about 0.47nm in terms of SiO ₂ film that Tokuraru There was a report. At this time, platinum is used as the conductive film for forming the capacitor electrode and the conductive film for forming the capacitor plate electrode.

Next, as shown in FIG. 4C, after forming a resist on the second conductive film for forming the capacitor plate electrode 8, a normal photolithography technique is used to form the capacitor electrode 8 A resist pattern 75 is formed by patterning into a shape (rectangular shape). Then, using the resist pattern 75 as a mask, the second conductive film, the insulating film, and the first conductive film are anisotropically etched by the PVD method.
The conductive film is sequentially patterned in a rectangular shape to obtain the capacitor plate electrode 8, the capacitor insulating film 24, and the capacitor electrode 6. At this time, the capacitor plate electrode 8 and the capacitor electrode 6 are formed in substantially the same planar shape by self-alignment.

Next, the processing edge of the capacitor plate electrode 8, the capacitor insulating film 24, and the pattern edge of the capacitor electrode 6 due to anisotropic etching is alleviated, and the electrical insulation withstand voltage of the capacitor insulating film 24 is lowered or a minute amount. In order to suppress current leakage, FIG.
As shown in (d), a thin insulating film 79 may be formed so as to cover the surfaces of the capacitor plate electrode 8, the capacitor insulating film 24, and the capacitor electrode 6.

The thin insulating film 79 is, for example, TEOS (tetraethoxysilane) formed by plasma CVD method.
SiO ₂ film by decomposition of S or S by thermal oxidation method
An iO ₂ film is formed. It is sufficient that the thickness of the thin insulating film 79 is not more than twice the thickness of the capacitor insulating film 24.

Next, as shown in FIG. 5A, a SiO ₂ film 77 is formed on the entire surface of the substrate including the thin insulating film 79 by a bias ECR plasma CVD method. Next, as shown in FIG. 5B, the surface of the SiO ₂ film 77 is covered with C
It is flattened by the MP method. At this time, the upper surface of the capacitor plate electrode 8 is exposed.

Next, as shown in FIG.
A conductive film (for example, an alloy film of Al and Cu) is formed on the entire surface of the substrate including the O ₂ film 77, a resist pattern 78 is formed thereon, and the alloy film is patterned using the resist pattern 78 as a mask. Then, the bit line / BL on the upper layer side is formed.

In the DRAM of the above embodiment, B
A capacitor insulating film 2 is formed on the capacitor electrode 6 for each IP cell.
The capacitor plate electrode 8 is formed so as to have substantially the same size at the same plane position as that of the capacitor electrode via the electrode 4, and is in electrical contact with the capacitor plate electrodes 8 of a plurality of BIP cells in the same row. The bit line / BL group on the upper layer side is formed so as to be continuously connected.

With such a structure, when the array of BIP cells is formed, the manufacturing process varies (fluctuations).
Therefore, even if the pattern alignment between the capacitor electrode 6 and the bit line / BL on the upper layer side is deviated, the capacitance value of the cell capacitor remains constant. Therefore, it is not necessary to provide a margin for pattern alignment, and the interval between the capacitor plate electrodes 8 of the BIP cells adjacent to each other along the word line direction can be set to the minimum processing line width Ls of lithography, and the cell capacitor can be highly integrated. This is advantageous in reducing the area per unit cell (miniaturizing the cell).

FIG. 6A schematically shows a plane pattern of a modified form of the BIP cell shown in FIG. FIG. 6B schematically shows a sectional structure including a cell capacitor taken along the line AA in FIG.

FIG. 7 schematically shows a sectional structure including a cell capacitor in a main part of the manufacturing process of the BIP cell shown in FIG. 6B. Compared with the BIP cell shown in FIGS. 1 to 3, the BIP cell according to the modified embodiment has at least a side surface of the capacitor plate electrode 8 which is tapered in the forward direction (downward expansion) when the cell capacitor is processed. (It should be noted that the processing technique of the forward taper for the polysilicon electrode is known.) Since the other points are the same, the same reference numerals as those in FIGS. 1 to 3 are given.

According to this structure, the same effect as that of the BIP cell shown in FIGS. 1 to 3 can be obtained, and since the capacitor plate electrode 8 has a forward taper, the upper layer side can be obtained. When the bit line / BL is formed, the pattern alignment shift occurs in the word line direction, and the BIP of the adjacent column
Even when they are close to the capacitor plate electrode of the cell, short circuit between them is less likely to occur, and the pattern alignment margin at the time of processing the upper bit line can be increased.

The SDG region of the BIP cell of the present invention is not limited to the case of being directly formed on the semiconductor substrate as in the above-described embodiment, but may be on the semiconductor layer on the SOI (silicon on insulator) substrate. You may form in.

[0068]

As described above, according to the present invention, the BIP
Even if the pattern alignment between the cell capacitor electrode and the bit electrode on the upper layer side is deviated, the capacitance value of the cell capacitor remains constant, and it is not necessary to provide a margin for the above pattern alignment. It is possible to provide a dynamic memory that can be integrated and can reduce the area per unit cell, and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is a diagram showing a planar pattern of a part of a cell array in a DRAM according to an embodiment of the present invention.

FIG. 2 is a diagram showing a sectional structure of a part of a cell array in the DRAM according to the embodiment of the present invention.

FIG. 3 is a diagram showing a sectional structure of a part of a cell array in the DRAM according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a part of a wafer cross section in a manufacturing process according to an example of a method for manufacturing the BIP cell shown in FIGS. 1 to 3;

5 is a cross-sectional view showing a part of a wafer cross section in a step that follows the step of FIG.

FIG. 6 is a diagram showing a plane pattern and a cross-sectional structure of a modified form of the BIP cell shown in FIGS. 1 to 3;

FIG. 7 is a sectional view showing a part of the manufacturing process of the BIP cell shown in FIG. 6;

FIG. 8: One-transistor / one-capacitor type DRAM
The figure which shows the equivalent circuit of a cell.

FIG. 9 is a view showing an equivalent circuit of a part of a memory cell array and its peripheral circuit in a DRAM using a conventional BIP cell.

10 is a timing waveform chart showing a result of simulation for an example of a read operation of "1" data and "0" data of the BIP cell in FIG.

FIG. 11: Large-capacity DR using a conventional BIP cell
The figure which shows the plane pattern of a part of memory cell array in AM.

FIG. 12: Large-capacity DR using a conventional BIP cell
The figure which shows the cross-section of a part of memory cell array in AM, and an equivalent circuit.

13 is an enlarged view showing the plane pattern of FIG.

[Explanation of symbols]

 5 ... Conductive plug, 6 ... Capacitor electrode, 8 ... Capacitor plate electrode, 10 ... Semiconductor substrate, 11 ... Element isolation region, 20 ... Gate insulating film, 21, 22 ... Interlayer insulating film, 23 ... Impurity diffusion region, 24 ... Capacitor insulating film, 71 ... Barrier metal, 77 ... Insulating film, 79 ... Gate electrode protecting insulating film, SDG ... Active region, BL, / BL ... Bit line pair, WL ... Word line, G ... Gate electrode part, BC ... Bit line contact area.

Claims (7)

[Claims] 1. A surface layer portion of a semiconductor substrate or a semiconductor layer is formed obliquely with respect to a word line formation direction and a bit line formation direction orthogonal thereto in plan view,
An active region in which a drain / channel / source region forming an OS transistor is linearly formed, a first bit line formed so as to contact the drain region of the MOS transistor, and a channel region of the MOS transistor. A word line having a gate electrode portion formed via a gate insulating film, and a predetermined pattern on the first bit line and on the word line via an interlayer insulating film, in the source region of the MOS transistor. A capacitor electrode formed so as to make contact, a capacitor plate electrode formed on the capacitor electrode via a capacitor insulating film, and having a substantially same planar shape as the capacitor electrode, and an upper surface of the capacitor plate electrode. And forming a complementary pair with respect to the first bit line. Dynamic memory, characterized in that it comprises a bit line. 2. A surface layer portion of a semiconductor substrate or a semiconductor layer is formed in a direction obliquely intersecting a word line formation direction and a bit line formation direction orthogonal to the word line formation direction when seen in a plan view, each of which constitutes a MOS transistor. Drain, channel and source regions are formed linearly,
An active region having a common drain region in the center, a cell array region in which a plurality of the active regions are formed in a matrix, and MOS transistors in a plurality of active regions in the same row of the cell array region. A plurality of word lines each having a gate electrode portion formed on a channel region via a gate insulating film and formed in parallel directions, and a plurality of active regions in the same column of the cell array region are common to each other. A plurality of first electrodes formed in contact with the drain region of the
A bit line, an interlayer insulating film formed on the first bit line and the word line, and a contact hole formed in a portion of the interlayer insulating film corresponding to the source region, A conductive plug in contact with the source region, a capacitor electrode formed to have a predetermined pattern on the interlayer insulating film so as to be electrically connected to the conductive plug, and a capacitor insulating film on the capacitor electrode. And a capacitor plate electrode having a substantially same planar shape as that of the capacitor electrode and an upper surface of a plurality of capacitor plate electrodes in the same column of the cell array region, respectively, and contacting the first bit line with respect to the first bit line. A plurality of second bit lines that are formed in parallel with each other and that are formed in parallel with each other. Dynamic memory, characterized. 3. The dynamic memory according to claim 2, wherein a side surface of the capacitor plate electrode is tapered in a forward direction. 4. A first bit line and a second bit line formed in the same column in the cell array region form a complementary pair and are connected to one differential sense amplifier. The dynamic memory according to any one of claims 1 to 3, wherein the dynamic memory is provided. 5. The dynamic memory according to claim 1, wherein the capacitor electrode is formed on the interlayer insulating film so as to cover above the gate electrode portion. . 6. Two drains forming a MOS transistor respectively in a surface layer portion of a semiconductor substrate or in a semiconductor layer in a direction obliquely intersecting a word line formation direction and a bit line formation direction orthogonal thereto in plan view.・
Forming a cell array region by arranging a plurality of active regions having a channel region and a source region formed in a straight line and having a common drain region in a central portion in a matrix form; Forming a plurality of word lines having gate electrode portions formed on the channel regions of the respective MOS transistors in a plurality of active regions via a gate insulating film in directions parallel to each other; And forming a plurality of first bit lines contacting a common drain region in a plurality of active regions of the same column of the cell array region on the first interlayer insulating film. Forming in a parallel direction, forming a second interlayer insulating film on the first bit line and on the first interlayer insulating film, A step of forming a contact hole in a portion of the second interlayer insulating film and the first interlayer insulating film corresponding to the source region, and filling a conductive plug in the opened contact hole, A step of contacting the source region, and a first step for forming a capacitor electrode on the second interlayer insulating film.
Sequentially forming a conductive film for forming a capacitor insulating film, a second conductive film for forming a capacitor plate electrode, and the second conductive film using a photolithography technique and an anisotropic etching technique. Forming a cell capacitor by patterning the insulating film and the first conductive film, and contacting the upper surfaces of a plurality of capacitor plate electrodes in the same column of the cell array region and parallel to the first bit line. And forming the second bit lines in directions parallel to each other in different directions. 7. The method for manufacturing a dynamic memory according to claim 6, wherein in the cell capacitor forming step, a side surface of the second conductive film is tapered in a forward direction.