JPH0974397A - Cross connection circuit and terminal station equipment using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cross connection circuit and a terminal station equipment using it for reducing signal propagation delay, reducing a memory amount required for cross connection, reducing a circuit scale and preventing information omission by contention from being generated even in an ATM equipment or the like. SOLUTION: STM-1 input signals IN#1-IN#n are passed through STM-1 reception parts 1-1 to 1-n, demultiplexed into AU-3 data in 1:3 demultiplex circuits 9-1 to 9-n are converted to packets in packet assembly circuits 10-1 to 10-n. The packets are distributed to packet disassembly circuits 13-1 to 13-m corresponding to the address of a transmission destination decided by a control part 12 beforehand by a switching part 11. Then, data are extracted by the inverse method of packet making and assembled into an STM-1 frame structure in a 3:1 multiplex circuit and STM-1 output signals OUT#1 to OUT#m are outputted through STM-1 transmission parts 3-1 to 3-m.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a terminal device for transmitting / receiving a transmission line code signal having a main frame structure of Mr rows × Mc columns. In addition, the present invention relates to a SDH (Sync
hronous Digital Hierarchy) Multiple STM-N (Synchronous Transport Module Level-)
N; N is a value corresponding to the signal speed, and is 0, 1, 4, 1
Input signal (which takes any value of 6 or 64) is exchanged in units of AU-3 or AU-4 (Administrative Unit level-3 or 4) and converted into a plurality of STM-N output signals. This is related to the technology for changing the road or the technology for adding and dropping.

[0002]

ITU-T (International Telecommunication Union Telecommunication Standardization Sector) Recommendation G. 707, G.C. 708, G.C.
In the SDH frame defined by 709, the AU is composed of a management byte and an information byte VC (Vitural Container). In the area of the information byte VC,
A predetermined unit of low-speed information is multiplexed and packed. As mentioned above, AU includes AU-3 units and AU-4.
Although there is a unit, in the following description, the AU-3 unit will be described as an example.

According to the conventional route switching process of the information byte VC, one or two frames of information are written in a predetermined memory in accordance with the input signal of the STM-N frame, and the route switching control signal is sent. According to the above, the data in the unit of the information byte VC is read from the memory and mapped to the designated AU position of the STM-N frame signal to be transmitted.

[0004]

Therefore, the conventional device has the following problems. (1) When the number of input / output signal lines to be cross-connected increases, the amount of memory for frame storage increases corresponding to each number of input / output lines, and the device scale increases. Also, since a memory for frame accumulation is interposed, in a transmission network in which a plurality of such cross-connect terminal devices are provided, a delay occurs each time a signal passes through the terminal devices,
The signal propagation delay time becomes large.

(2) For cross-connecting, a switch matrix in which a time switch and a space switch are combined is required, and it is necessary to have a structure in which competition (collision) does not occur in the switch matrix. . The present invention has been made in view of the above points, and an object thereof is to reduce the signal propagation delay, reduce the memory amount required for cross-connecting, and reduce the circuit scale, and to randomly select an unspecified number of signals. Input to ATM (Asynchrono
us Tranfer Mode; ITU-TI. It is to provide a cross-connect circuit that does not cause information loss due to contention even in an (asynchronous transfer mode) device defined by H.432, and a terminal device using the same.

[0006]

In order to solve the above problems, the invention according to claim 1 defines a subframe represented by Sr rows × Sc columns with a predetermined number of bits as a unit, and the subframe. A cross-connect circuit for switching the management information bytes of a Cm column to be managed, the packet generating means converting the subframe and the management information byte for managing the subframe into packet data of a predetermined length. And a line control means for performing control for giving an address to the packet data, and an address giving means for writing the address designated by the line control means into an address portion of the packet data generated by the packet generating means. And, based on the address given to the packet data, distribute the packet data to the corresponding output terminals. Packet switch means, packet decomposing means for removing the address part from the packet data distributed by the packet switch means, and extracting the information part of the packet data, and management required for generating the subframe. Information is added to the information portion to reproduce a subframe, and the subframe generating means is provided.

According to the invention of claim 2, in the invention of claim 1, the packet data is ITU.
-TI. It is characterized by using an ATM cell defined by H.432. According to a third aspect of the present invention, in the first aspect of the invention, Sr rows × (Sc + Cm), which is a combination of the subframe of the Sr rows × Sc columns and the management information bytes of the Cm columns corresponding to the subframes. ) Column frame structure is converted into a packet having a length of (Sc + Cm).

Further, the invention according to claim 4 has a main frame having a bit arrangement expressed by Mr rows × Mc columns with a predetermined number of bits as a unit, and a specific Cm column of the main frame is managed. The main frame received by the terminal station device having an information byte group and transmitting and receiving a transmission line code containing a plurality of subframes represented by Sr rows × Sc columns in a portion excluding the management information byte group. From the signal, the frame demultiplexing unit that demultiplexes the subframe and the management information byte that manages the subframe as one unit, the subframe generated by the frame demultiplexing unit, and the management information byte that manages the subframe are included. The cross-connect circuit according to any one of claims 1 to 3 for switching routes, and the sub-connect output from the cross-connect circuit. Frame multiplexing means for generating a mainframe based on a frame, and changing the route of input n mainframe signals into m mainframe output signals in subframe units. I am trying.

According to a fifth aspect of the invention, in the invention of the fourth aspect, the main frame is ITU.
-T Recommendation G. 707, G.C. 708, G.C. It is characterized by using the SDH frame defined in 709.

[0010]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, in the case of N = 1 of STM-N, that is, STM.
In the case of -1, it will be explained. FIG. 1 is a block diagram showing the configuration of the terminal device according to the embodiment. As shown in the left side of FIG.
TM-1 input signals IN # 1 to IN # n are input, and finally m STM-1 output signals OUT shown on the right side of the drawing are output.
# 1 to OUT # m are output.

This terminal device includes STM-1 receiving units 1-1 to 1-1.
1-n, data HW exchange unit 2, STM-1 transmission unit 3-1 to 3
-m is roughly divided. STM-1 receivers 1-1 to 1-n, STM
-1 Transmitters 3-1 to 3-m, 1: 3 separation circuits 9-1 to 9-n, and packet assembly circuit 1 in the data HW exchange unit 2
0-1 to 10-n, packet disassembling circuits 13-1 to 13-m, 3:
The 1-multiplexing circuits 14-1 to 14-m (each of which will be described in detail later)
Each has the same configuration. Therefore, in the following description of the configuration, the STM-1 receiving section 1-1, S
TM-1 transmitter 3-1, 1: 3 separation circuit 9-1, packet assembly circuit 10-1, packet disassembly circuit 13-1, 3: 1
Only the multiplexing circuit 14-1 will be described.

First, the STM-1 receiving section 1-1 comprises an input buffer circuit 4-1, a frame synchronizing circuit 5-1 and an SOH (section overhead) terminating section 6-1. Also, SO
The H termination unit 6-1 is composed of a descramble / B1 byte detection circuit 7-1 and a pointer processing / error detection circuit 8-1.

The input buffer circuit 4-1 buffers and outputs the STM input signal IN # 1. Frame synchronization circuit 5
-1 detects a frame synchronization signal from the output signal of the input buffer circuit 4-1 to establish frame synchronization. The descramble / B1 byte detection circuit 7-1 detects the output of the frame synchronization circuit 5-1 and detects the B1 byte included in the SOH portion of the STM-1 frame shown in FIG. 2 (details will be described below). And so on. The pointer processing / error detection circuit 8-1 uses the clock CK to transfer the output of the descrambling / B1 byte detection circuit 7-1 to the data signal of the internal clock and the pointer processing, STM.
-1 Code error detection using the B2 byte included in the SOH portion of one frame is performed.

FIG. 2 shows the detailed structure of the STM-1 frame. In this figure, the first 9 of STM-1
The columns are called SOH. Further, an area obtained by removing SOH from the STM-1 frame is called a payload. Furthermore, H
The sequence containing the bytes 1, H2, H3 is called the AU-3 pointer. In addition, the meaning of each byte described in this figure, including the B1 byte and the B2 byte described above, is defined by the international standard. For example, B
One byte is a byte used to monitor a code error between repeaters or between a repeater and a transmission terminal station device, and B2 byte is a byte used to monitor a code error between transmission terminal devices.

Further, FIG. 3 shows an AU-3 and a byte structure of SOH corresponding to the AU-3. In this figure, an area of 2 columns called fixed stuff, an area called VC-3 of 9 rows × 85 columns (87-2 = 85 columns) surrounded by a bold frame, and an AU-3 composed of H1, H2 and H3 The area of the AU-3 is a combination of the area of the pointer and the area of the pointer.
By the way, the area of AU-4 described above is A shown in FIG.
It refers to a part where the area of the U-3 pointer and the payload of 9 rows × 261 bytes are combined.

On the other hand, the 1: 3 separation circuit 9-1 separates the STM-1 frame signal of the format shown in FIG. 2 which is transferred to the internal clock into three AU-3 data signals in byte units. Here, regarding the separation into the AU-3 data signal, since the three AU-3s are mapped every 3 bytes on the STM-1 frame as shown in FIG. In the state of being taken, it is possible to separate in AU-3 units by using a circuit that extracts data for every 3 bytes for each row.

When separating the data in units of AU-3 from STM-1, S except H1, H2 and H3 is used.
Control of a counter circuit or the like is required to identify and separate the OH region. Therefore, in order to simplify the circuit, a circuit configuration that always separates every 3 bytes can be considered. In addition,
In the state of low speed operation after separating every 3 bytes, in-device monitoring information such as parity is added to the SOH byte portion other than the area of the AU-3 pointer to eliminate code errors during transfer in the device. It is also possible to detect.

On the other hand, Packet Assembly
The bly) circuit 10-1 converts the output of the 1: 3 separation circuit 9-1 into fixed-length packet data. Here, as the packet data, (1) a method of using an ATM 53-byte cell, which is currently being studied by ITU, and (2)
Considering that the AU-3 data has a matrix structure of 9 rows × 90 columns (Sr rows × Sc columns), a method using a packet with a length of 90 bytes as a unit can be considered.

First, the above method (1) using the ATM cell structure will be described. Note that FIG. 4 is a reference for this method. As is well known, 5 ATM cells
48 bytes out of 3 bytes are used for transfer of information signal,
The other 5 bytes are used as management bytes. Therefore,
According to this method, the AU-3 data is transferred to the ATM cell 48.
It will be placed in the byte area.

For this transfer, the clock speed becomes a power of 2 via a speed conversion circuit (not shown) so that the clock speed becomes a power of 2.
Convert U-3 data information to 48 bytes. here,
The clock speed does not necessarily have to be a power of 2, but using a power of 2 has the advantage of simplifying the circuit configuration of the speed conversion circuit. Then, the destination (address) of the packet is written in a predetermined portion in the first 5 bytes of the ATM cell and is input to the switch unit 11 (details will be described later). It is also possible to write the in-device monitoring information in the byte portion other than the first 5-byte address and 48-byte information signal of the ATM cell.

Next, the above method (2) for converting into a packet of the length of one line of AU-3 will be described. Note that FIG. 5 is a reference for this method. In this method, since the length of one line of AU-3 is 90 bytes, it is converted into a packet with this as a unit.
Here, since the data structure is the same before packetization and after packetization, the speed conversion process like the method (1) described above is unnecessary. The first 3 bytes of AU-3 are the management bytes of the SOH, and the bytes other than the in-apparatus monitoring information section written in the 1: 3 separation circuit 9-1 in this part are the destination (address of the packet). ) And in-device monitoring information are written and input to the switch unit 11.

On the other hand, a switch unit (packet distribution unit)
Reference numeral 11 indicates a destination (address) of a destination predetermined by the control unit 12 (details will be described below) and a destination (address) of a packet sent from the packet assembly circuits 10-1 to 10-n. By collating, these packets are distributed to the output terminals of the switch unit 11. In the switch section 11, the left side in the figure is an input terminal and the right side is an output terminal.

The main function of the controller 12 is as follows. First, the STM-1 input signals IN # 1 to IN # n
Based on the AU-3 frame phase for each of the above, the pointer value of the AU-3 data when assembled into the transmission STM-1 frame is calculated, and the STM-1 transmission unit 3-1 to
Point the pointer value to 3-m. Secondly, according to a route setting command designated from the outside of the terminal device, the packet assembly circuit 10-is provided so as to add the destination (address) used by the switch unit 11 to the packetized AU-3 data. Control 1

The Packet De-Assembly circuit 13-1 extracts the packet data sent from the output terminal of the switch section 11 by a method reverse to packetization. That is, when packetized by the method (1) described above, the first 5 bytes of the ATM cell are separated and the information data is extracted from the remaining 48 bytes. Further, a code error of data is detected based on the in-device monitoring information. Further, speed conversion is performed to convert the data into AU-3 data, and the AU-3 frame structure is assembled.

On the other hand, when packetized by the method (2) described above, since the address and the in-device monitoring information are present in the first 3 bytes, the parts other than the address part are directly transmitted to the subsequent stage. Further, since the packet data structure and the AU-3 data structure are the same, the speed conversion becomes unnecessary as described above. Then, the data thus extracted is assembled into an AU-3 frame structure.

Next, the 3: 1 multiplexing circuit 14-1 multiplexes the three pieces of AU-3 frame structure data assembled by the packet decomposing circuit 13-1 in the designated AU-3 in byte units. To assemble the STM-1 frame structure data. Note that the detection of the code error based on the in-device monitoring information performed by the packet disassembling circuit 13-1 can also be performed here.

Next, the SOH inserting section 15-1 is composed of a pointer inserting section 16-1 and a scrambler circuit 17-1. The pointer insertion unit 16-1 is provided with the pointer values obtained by the pointer processing / error detection circuits 8-1 to 8-n on the input side,
The STM frame phase generated at the output side of this device and the frame phase of each AU-3 selected by the switch unit 11 are calculated by the control unit, and the result of STM-generated by the 3: 1 multiplexing circuit 14-1 is shown. H1, H2 in the data of one frame structure
It is written in the portion of H3 as a pointer value. In addition to this, B2 byte calculation in the STM frame is performed.

The scrambler circuit 17-1 scrambles the data output by the pointer insertion unit 16-1 and performs B1 byte processing. The output buffer circuit 18-1 buffers the output signal of the scrambler circuit 17-1 and
−1 Output as the output signal OUT # 1.

Next, the operation of the cross-connect circuit having the above configuration and the terminal equipment using the same will be described. First,
The STM-1 input signal IN # 1 is input to the input buffer circuit 4-1.
After that, frame synchronization is established by the frame synchronization circuit 5-1. Next, the output of the frame synchronization circuit 5-1 is subjected to termination processing such as B1 byte detection and descrambling by the descramble / B1 byte detection circuit 7-1, and subsequently, by the pointer processing / error detection circuit 8-1. , Transfer of data signal to clock in device and pointer processing, B2
Code error detection by bytes is performed.

The processing up to this point is the same as the conventional STM signal termination processing. On the other hand, the control unit 12
Calculates the pointer value of the AU-3 data when assembled into a transmission STM-1 frame based on the AU-3 frame phase of each input signal.

Next, S transferred to the internal clock is changed.
The TM-1 frame signal is separated into three AU-3 data signals by the 1: 3 separation circuit 9-1, and the in-device monitoring information is added to the SOH byte portion other than the AU-3 pointer area. Then, the output of the 1: 3 separation circuit 9-1 is converted into fixed-length packet data by the packet assembly circuit 10-1 and sent to the switch unit 11. At that time, the control unit 12 controls the packet assembly circuit 10-1 so as to add a destination to the packetized AU-3 data.

In the above method (1), the AT
The packet destination is written in the management byte of the M cell, and the AU-3 data is further converted into 48 bytes of the ATM cell. At this time, the in-device monitoring information is written in a portion other than the address portion of the management byte and the 48-byte information signal of the ATM cell. On the other hand, in the method (2) described above, the packet is converted into a packet having the length of one line of AU-3 as a unit. 1: 3 of the management bytes of SOH of AU-3
The destination of the packet and the in-device monitoring information are written in the separation circuit 9-1 in addition to the portion in which the in-device monitoring information is written.

In this way, the STM-1 input signal IN
Also for # 2 to IN # n, the STM-1 input signal IN #
The same processing as that of 1 is performed and the data is input to the switch unit 11. Next, the switch unit 11 collates the destination of the transmission destination determined in advance by the control unit 12 with the destination of the input packet, and distributes these packets to the output terminal of the switch unit 11.

Next, the packet decomposition circuit 13-1 extracts the data from the packet data output from the switch unit 11. That is, according to the above method (1), the management byte of the ATM cell is separated, the information data is extracted from the remaining 48 bytes, and the code error of the data is detected using the in-device monitoring information. After that, speed conversion is performed and the frame structure of AU-3 is assembled. On the other hand, according to the above method (2), data other than the address part included in the first 3 bytes of the packet data is extracted and assembled into the structure of the AU-3 frame, and the in-device monitoring information is used. A data code error is detected.

Next, the data of these AU-3 frame structures are multiplexed in byte units in the designated AU-3 order by the 3: 1 multiplexing circuit 14-1 to form data of the STM-1 frame structure. Can be assembled. In addition to this, a code error is detected using the in-device monitoring information. Further, in the pointer insertion unit 16-1, the pointer value obtained by the pointer processing / error detection circuit on the input side,
The STM frame phase generated on the output side of this device and the frame phase of the AU-3 selected by the switch unit 11 are calculated by the control unit 12, and the resulting values are H1, H2, H.
A pointer value of 3 is written in the data of the above STM-1 frame structure. In addition to this, calculation of B2 bytes is also performed.

Next, the output of the pointer insertion unit 16-1 is scrambled by the scrambler circuit 17-1 and B1 byte processed, and is output from the output buffer circuit 18-1 as the STM-1 output signal OUT # 1. Is output. In this way, the switch unit 11 is switched to the packet disassembling circuit 1.
The packet data distributed to 3-2 to 13-m are also subjected to the same processing as the packet data sent to the packet disassembling circuit 13-1, and the respective STM-1 output signals OUT # 2 to OUT # m are processed. Buffer circuits 18-1 to 18-1
Output from 8-m.

[0037]

As described above, claims 1 to 3 are described.
According to the described invention, the subframe and the management information byte are converted into packet data, the address is given, the packet data is distributed based on the address, and the information part is extracted from the distributed packet data. Since the sub-frame is reproduced by adding the management information, the cross-connect function can be realized in sub-frame units, the signal propagation delay of the circuit can be reduced, and the memory required for the cross-connect can be reduced. The effect that the circuit scale can be reduced by omitting is obtained. Further, since the route setting of the cross-connect is uniquely determined by the line control means in advance, even if it is used for an ATM device or the like in which an unspecified number of signals are randomly input,
The effect that information loss due to competition does not occur can be obtained.

Further, according to the invention described in claims 4 to 5, the subframe and the management information byte are separated from the received mainframe signal, and the cross-connect circuit according to claims 1 to 3 performs the route replacement. Since the main frame is generated from the obtained sub-frames, it is possible to configure a terminal station device having a small signal propagation delay and a small circuit scale when handling an SDH transmission device, particularly a signal having an STM-N frame structure, Further, it is possible to obtain an effect that it is possible to realize a terminal device that does not cause information loss due to competition in an ATM device or the like in which an unspecified number of signals are randomly input.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a terminal device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a frame structure of an STM-1 frame.

FIG. 3 is a diagram showing a structure of an AU-3 and an SOH byte corresponding to the AU-3.

FIG. 4 is a block diagram showing an AU-3 frame according to the present embodiment.
It is a figure explaining the method of mapping to the 53-byte cell of TM.

FIG. 5 is a diagram illustrating a mapping method for mapping a packet having a unit length of one column of AU-3 in the embodiment.

[Explanation of symbols]

1-1 to 1-n ... STM-1 receiving unit, 2 ... Data HW switching unit, 3-1 to 3-m ... STM-1 transmitting unit, 4-1 to 4-n ... Input buffer circuit, 5-1 ~ 5-n ... Frame synchronization circuit, 6-1 ~
6-n ... SOH terminal part, 7-1 to 7-n ... descrambler B
1-byte detection circuit, 8-1 to 8-n ... Pointer processing / error detection circuit, 9-1 to 9-n ... 1: 3 separation circuit, 10-1 to 10-n
... packet assembly circuit, 11 ... switch section, 12 ...
Control unit, 13-1 to 13-m ... Packet decomposition circuit, 14-1 to
14-m ... 3: 1 multiplexing circuit, 15-1 to 15-m ... SOH insertion unit, 16-1 to 16-m ... Pointer insertion unit, 17-1 to 17
-m ... scrambler circuit, 18-1 to 18-m ... output buffer circuit

Claims (5)

[Claims] 1. Sr rows × S in units of a predetermined number of bits
A cross-connect circuit for rerouting a subframe represented by a column c and a management information byte of a Cm column for managing the subframe, the subframe and the management information byte for managing the subframe. To packet data having a predetermined length, line control means for performing control for assigning an address to the packet data, and the packet generation means for generating the address designated by the line control means. Based on the address given to the packet data, which is written in the address portion of the packet data generated by
Packet switch means for allocating the packet data to a corresponding output terminal; packet disassembling means for removing the address part from the packet data allocated by the packet switch means to extract an information part of the packet data; A cross-connect circuit comprising sub-frame generation means for reproducing sub-frames by adding management information required for generating the sub-frames to the information part. 2. The ITU-T is used as the packet data.
I. 4. The cross-connect circuit according to claim 1, wherein an ATM cell defined by H.432 is used. 3. A frame structure of Sr rows × (Sc + Cm) columns, in which a subframe of Sr rows × Sc columns and management information bytes of the Cm columns corresponding to the subframes are combined, has a length of (Sc + Cm). 2. The cross-connect circuit according to claim 1, wherein the cross-connect circuit converts the packet into a packet. 4. Mr row × M in units of a predetermined number of bits
The main frame has a bit array represented by a column c, a specific Cm column of the main frame has a management information byte group, and the portion excluding the management information byte group is Sr.
In a terminal device that transmits and receives a transmission line code accommodating a plurality of subframes represented by rows × Sc columns, the subframe and a management information byte that manages the subframe are combined into one from the received mainframe signal. The frame separating means for separating as a unit, the subframe generated by the frame separating means, and the management information byte for managing the subframe are route-switched, according to any one of claims 1 to 3. And a frame multiplexing means for generating a main frame based on the sub-frames output from the cross-connect circuit. The input n main-frame signals are converted into m main-frame signals. A terminal device characterized in that a route is changed to a frame output signal in units of subframes. 5. The ITU-T as the main frame
Recommendation G. 707, G.C. 708, G.C. The SDH frame defined in 709 is used.
The terminal device described.