JPH0964373A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device which can exclude the influence of a flaw in a gate insulating film generated in a process in which impurity ions are implanted while a part of the gate insulating film is used as a mask. SOLUTION: A gate insulating film 110 is formed by making use of an anodized substance 108 formed on the side face of a gate electrode 107. Then, in a state that the anodized substance 108 has been removed, impurity ions are implanted. Then, a lightly doped region is formed in the region of an active layer 103 corresponding to a region in which the anodized substance 108 has existed. After that, the insulating film on the lightly doped region is removed. Thereby, it is possible to exclude the influence of a flaw generated in the insulating film on the lightly doped region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The invention disclosed in this specification relates to a thin film transistor and a method for manufacturing the thin film transistor. Examples of the usage of this thin film transistor include a thin film integrated circuit and an active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art FIG. 4 shows a process of manufacturing a typical thin film transistor known in the related art. First, a silicon oxide film or a silicon nitride film is formed as the base film 402 on the glass substrate 401. Next, an amorphous silicon film 403 is formed by a plasma CVD method or a low pressure thermal CVD method. Then, heating or laser light irradiation is performed to crystallize the amorphous silicon film to obtain a crystalline silicon film (not shown). (Fig. 4 (A))

Next, the crystalline silicon film is patterned to form an active layer 404 of the thin film transistor. A source region, a drain region, and a channel forming region are later formed in this active layer.

Further, a gate insulating film 405 covering the active layer.
To form A silicon oxide film or a silicon nitride film is generally used as the gate insulating film 405. (FIG. 4 (B))

Next, a gate electrode 406 is formed. The gate electrode is composed of a metal-based material such as aluminum, chromium silicide, or tungsten silicide, or a semiconductor material having one conductivity type.

Then, in the state shown in FIG. 4C, impurity ions are implanted to form the source / drain regions. Here, if an N-channel type thin film transistor is to be formed, P (phosphorus) is doped. If a P-channel type thin film transistor is to be formed, B (boron) is doped.

In the implantation of the impurity ions, the source electrode 407 and the drain region 409 are automatically formed by using the gate electrode 406 as a mask. Further, a region 408 immediately below the gate electrode is defined as a channel formation region. This step is called the self-alignment process.

After the implantation of the impurity ions, laser light irradiation is further performed to anilize the source region 407 and the drain region 409 damaged by the implantation of the impurity ions. At this time, the implanted impurity ions are activated at the same time.

After the step shown in FIG. 4C is finished, a silicon oxide film or a silicon nitride film is formed as an interlayer insulating film. Then, contact holes are formed to form a source electrode 412 that communicates with the source region 407 and a drain electrode 413 that communicates with the drain region 409. The source electrode 412 and the drain electrode 413 are made of a suitable metal material such as aluminum.

[0010]

The thin film transistor is completed by the steps shown in FIG. 1. However, it has been found that the thin film transistor obtained by the above steps has a problem in stability of its characteristics. There is.

For example, the following test is performed on the thin film transistor obtained by the manufacturing process as shown in FIG.・ Measure the gate voltage-drain current characteristics (characteristic 1) at room temperature. Next, the entire device is heated to 150 ° C. with a voltage of plus 20 V applied to the gate electrode.・ Again, at room temperature, gate voltage-drain current characteristics (characteristic 2
And) is measured. -Next, the whole device is heated to 150 ° C with a voltage of -20 V applied to the gate electrode.・ Again, at room temperature, gate voltage-drain current characteristics (characteristic 3
And) is measured.

When the above test is conducted, many samples in which the characteristics 1 to 3 do not match are found. As a result of diligent research on this problem, it was found that a major factor is the trap level existing in the gate insulating film. That is, by trapping charges in the high-density trap levels existing in the gate insulating film, the characteristics 1 to 3 in the above test are obtained.
There will be a gap.

Naturally, the existence of the trap level causes a change in the characteristics of the thin film transistor with time and instability.

The inventors of the present invention have found that the factors causing the trap level are as follows. That is, in the step shown in FIG. 4C, P or B impurity ions are implanted through the gate insulating film. Then, due to the impact of the ions implanted at this time, the gate insulating film is damaged and high-density trap levels are formed in the gate insulating film.

An annealing method by heating may be used to eliminate or reduce the trap levels formed in the gate insulating film. However, particularly when an inexpensive glass substrate (for example, Corning 7059 glass or Corning 1737 glass) is used, it is not possible to perform heating to the extent that sufficient annealing can be performed due to the heat resistance problem of the glass substrate.

Generally, when a glass substrate is heated at a temperature equal to or higher than its strain point for a long time, it is warped or deformed. When a liquid crystal display device is configured using glass substrates that are warped or deformed as described above, the distance between the glass substrates cannot be kept constant, and the thickness of the liquid crystal layer injected between the glass substrates becomes uneven. Will occur. This causes non-uniformity and unclearness of display. In general, the thickness of the liquid crystal layer of a liquid crystal display device is about several μm, so slight deformation of the glass substrate poses a serious problem. And this problem becomes apparent as the glass substrate becomes larger.

On the other hand, when an expensive quartz substrate is used as the substrate or when it is used for a liquid crystal electro-optical device, it is given up,
When a silicon wafer is used as the substrate, heat treatment can be performed at a high temperature of 800 ° C. or 900 ° C. or higher. When the heat treatment is performed at such a high temperature, damage to the gate insulating film at the time of implanting impurity ions can be sufficiently annealed.

As an annealing method that does not cause thermal damage to the glass substrate, there is a method using laser light irradiation as described above. However, particularly when a silicon oxide film is used as the gate insulating film, the annealing effect cannot be obtained because the laser light passes through the silicon oxide film.

Therefore, an object of the invention disclosed in this specification is to solve the problem of damage to the gate insulating film during the implantation of the impurity ions. Especially, the strain point is 7 as a substrate
An object of the present invention is to solve the problem of damage to the gate insulating film in the case of using a glass substrate that is inexpensive but has low heat resistance such as 00 ° C. or lower. Another object is to solve the problem of damage to the gate insulating film and obtain a thin film transistor having a reduced OFF current value.

[0020]

One of the inventions disclosed in this specification is, as shown in the example in FIG. 2C, between a source region 201 and a channel formation region 203 and a channel formation region. Low concentration impurity regions 202 and 204 are provided between 203 and the drain region 205, and the dimension 21 of the low concentration impurity regions 202 and 204 in the source / drain direction is 21.
3 and 214 are the same or substantially the same, the concentration of the impurity imparting one conductivity type in the low concentration impurity regions 202 and 204 is lower than that in the source region 201 and the drain region 205, and the channel formation is performed. It is characterized in that the gate insulating film is larger than the region 203 and does not exist on the low concentration impurity region.

The above-mentioned structure is particularly characterized in that the gate insulating film is not present on the low concentration impurity. With such a structure, the influence of defects existing in the gate insulating film can be eliminated.

Another structure of the invention is a method of forming a source region 201 and a drain region 205 by implanting impurity ions using the gate electrode 107 as a mask, as shown in FIG. An insulating film (corresponding to a portion indicated by 206) extending from the gate insulating film 110 is not formed on the regions 201 and 205 serving as the source and drain regions, and the gate electrode 10 is formed.
Immediately below 9 and regions 201 and 2 to be source and drain regions
In a state in which an insulating film (corresponding to a portion indicated by 206) extending from the gate insulating film is formed on the pair of regions 202 and 204 between the semiconductor layer 05 and the region 05, impurity ions imparting one conductivity type are implanted. And source and drain regions 201
And 205 to form the pair of regions 202 and 2
04 as a low concentration impurity region and a step of removing the insulating film 206 on the pair of regions, and an impurity imparting one conductivity type implanted into the low concentration impurity regions 202 and 204. Is lower than that in the source and drain regions 201 and 205.

By adopting the above structure, the low concentration impurity regions 202 and 204 can be formed. This is because impurity ions are directly implanted into the regions 201 and 205, which are the source and drain regions, by implanting the impurity ions in a state where the insulating film remains in the region 206 on this region. This is because impurities are implanted into the regions 202 and 204, which are low-concentration impurity regions at the same time, through the insulating film.

Further, an insulating film 206 extending from the gate insulating film 110 used when forming the low concentration impurity region.
By removing the portion of, it is possible to eliminate the influence of the defect existing in this portion. That is, it is possible to eliminate the negative factor due to the provision of the low-concentration impurity region and obtain the significance of the low OFF current characteristic.

In the structure of another invention, as shown in FIG. 2 as an example, impurity ions are implanted by using a region 206 extending from a gate insulating film left on a part of the active layer as a mask to implant a low concentration impurity. The method includes a first step of forming the regions 202 and 204 and a second step of removing the region 206 extending from the gate insulating film after the step.
Source and drain regions 201 and 20
5 is exposed, and the low-concentration impurity region 2 is present in this region.
It is characterized in that a higher concentration of impurities is injected as compared with 02 and 204.

The above characteristics are characterized in that the region 206, which is a part of the insulating film used for forming the low-concentration impurity regions 202 and 204, is removed thereafter. By doing so, it is possible to eliminate the influence of defects formed in the region 206 at the time of implanting the impurity ions.

[0027]

【Example】

[Embodiment 1] FIG. 1 shows a manufacturing process of this embodiment. The characteristics of the thin film transistor shown in this embodiment are shown below. A low OFF current characteristic is achieved by arranging a low concentration impurity region by a self-alignment process. Eliminate problems caused by damage to the gate insulating film during ion implantation. -Manufactured by a low-temperature process that an inexpensive glass substrate can withstand.

First, a silicon oxide film 102 is formed as a base film on a Corning 1737 glass substrate (strain point 667 ° C.) 101 to a thickness of 3000 Å. The silicon oxide film 102 may be formed by a plasma CVD method or a sputtering method.

Since the strain point of the Corning 1737 glass substrate is 667 ° C., it is necessary to keep the process temperature at or below that temperature. (Of course, the process temperature should be as low as possible)

Corning 705 is used as a glass substrate having excellent optical characteristics which can be used in a liquid crystal electro-optical device.
There are 9 glass substrates. However, since the strain point of this glass substrate is 593 ° C., when using this glass substrate,
The process temperature must be below this temperature. In any case, when an inexpensive glass substrate is used instead of an expensive substrate such as a quartz substrate, it is necessary to pay attention to its heat resistance.

After the base film 102 is formed, an amorphous silicon film (not shown) (this amorphous silicon film will later become a starting film for forming the active layer 103) is formed to a thickness of 500 Å. This amorphous silicon film may be formed with a required thickness.

The formation of this amorphous silicon film is performed under reduced pressure heat C.
The VD method is preferred. This is because the hydrogen concentration in the formed amorphous silicon film is the lowest when the low pressure thermal CVD method is used. The lower the hydrogen concentration in the film, the higher the crystallinity can be obtained in the subsequent crystallization step.

When the plasma CVD method is used,
In order to sufficiently release hydrogen in the film, it is useful to apply heat treatment after the film formation to promote the release of hydrogen. This dehydrogenation treatment by heating is also useful when the low pressure thermal CVD method is used. This heat treatment needs to be performed under the condition that the amorphous silicon film is not crystallized.

Next, heat treatment or laser light irradiation is performed to crystallize the amorphous silicon film to obtain a crystalline silicon film. Then, by patterning this crystalline silicon film, the active layer 103 of the thin film transistor is obtained.

Next, a silicon oxide film is formed as the gate insulating film 100 to a thickness of 1000Å. As the structure of the gate insulating film 100, a multilayer film of a silicon oxide film and a silicon nitride film may be used. For example, a laminated film such as a silicon nitride film-a silicon oxide film-a silicon nitride film may be used. Alternatively, a silicon oxynitride film may be used as the gate insulating film. The silicon oxynitride film can be formed by a plasma CVD method using TEOS gas and N ₂ O gas as source gases, for example.

Next, an aluminum film 104 is formed by a sputtering method to form a gate electrode. In this embodiment, aluminum containing 0.1% scandium is used. This is to suppress the generation of hillocks and whiskers due to abnormal growth of aluminum in the subsequent laser light irradiation step and the like.

The aluminum film is used here because anodization is performed later. Other than the aluminum film, a metal material capable of anodic oxidation, for example, tantalum can be used.

Then, in the electrolytic solution, the aluminum film 104 is formed.
Is used as an anode to form a dense anodic oxide film 105. Here, PH containing tartaric acid as an electrolytic solution
Use an ethylene glycol solution of ≈7. When this electrolytic solution is used, an anodic oxide film having a dense film quality can be formed.

This anodic oxide film is important for improving the adhesion of the resist mask formed later. The dense anodic oxide film 105 has a thickness of several tens of Å to 10
About 0Å is enough. The thickness of the dense anodic oxide film can be controlled by the applied voltage.

Next, the resist mask 106 is arranged. This resist mask is used to form a gate electrode. (Fig. 1 (A))

The gate electrode 107 is formed by patterning the aluminum film in the state of FIG. An acidic solution containing 3 to 20% citric acid was used as an electrolytic solution, and the gate electrode 1 was placed in this solution.
Anodization is performed using 07 as an anode. In this step, the porous anodic oxide 108 is formed. This anodic oxidation can be controlled by the anodic oxidation time, and the growth amount can be several thousand Å
The above can be done. Here, the growth amount is 40
00 °. The growth amount of the porous anodic oxidation can determine the approximate size of the low-concentration impurity region to be formed later.

This anodic oxidation selectively proceeds on the side surface of the gate electrode. This is because the dense anodic oxide film and the resist exist on the upper surface of the gate electrode 107, and the electrolytic solution cannot enter the surface. (Fig. 1 (B))

Next, the resist mask 106 and the dense anodic oxide film 195 are removed, and a dense anodic oxide film is formed again. The dense anodic oxide film 195 may not be removed.

In this step, since the electrolytic solution (or ion) enters the inside of the porous anodic oxide 108, the dense anodic oxide film 10 is formed around the gate electrode 107.
9 is formed.

If the dense anodic oxide film 109 is thickened, an offset gate region can be formed later by the thickness. Here, the dense anodic oxide film 109 is formed in order to suppress the generation of hillocks and whiskers and the problem of short circuit between wirings. Therefore, the film thickness may be such that a barrier effect can be obtained. Here, the thickness is 500 Å. The dense anodic oxide film 109 can be practically formed up to a thickness of about 3000 Å. (If it is too thick, the applied voltage will be high, which is dangerous, and the controllability of the film thickness will deteriorate.)

Thus, the state shown in FIG. 1C is obtained. Then, the gate insulating film exposed in this state is removed. Then, as indicated by 110 in FIG. 1D, the gate insulating film is partially left.

When the state shown in FIG. 1D is obtained, the porous anodic oxide 108 is removed with a chromium mixed acid (a mixed acid of phosphoric acid, acetic acid and nitric acid). Thus, the state shown in FIG. 1 (E) is obtained.

After obtaining the state shown in FIG.
As shown in (A), P (phosphorus) or B (boron) ions are implanted. A plasma doping method or an ion implantation method may be used in this step.

In this step, the exposed regions of the active layer shown by 201 and 205 are heavily doped with impurity ions. On the other hand, since the gate insulating film (silicon oxide film) exists in the regions 202 and 204, a part of the ions are shielded, and the impurity ions are doped at a lower concentration than the regions 201 and 205. It

In this step, the regions 201 and 205 become the source region and the drain region. Also, 202
Regions 204 and 204 are low-concentration impurity regions. The low concentration impurity region 204 on the drain region 205 side is LDD.
It is generally called a (lightly doped drain) region.

In the step shown in FIG. 2A, since the gate electrode 107 and the surrounding anodic oxide film 109 serve as a mask, impurity ions are not implanted into the region 203. The region 203 is the channel forming region.

Although the offset gate region is formed in the active layer by the thickness of the dense anodic oxide film 109, since the thickness of the anodic oxide film 109 is as thin as 500 Å in this embodiment, the offset gate region is thin. The existence of the area is ignored.

Further, the high concentration and the low concentration referred to here are problems of relative comparison and are not absolute. Generally, the impurity concentration in the source region and the drain region is on the order of 10 ¹⁸ cm ⁻³ to 10 ²¹ cm ⁻³ ,
The impurity concentration of the low-concentration impurity region is a value that is smaller than that by about two digits. The specific value needs to be set according to the required characteristics of the thin film transistor and the manufacturing process conditions.

In this step, the region into which the impurity ions are implanted is damaged by the impact of the ions. Here, damage to the gate electrode 107 and the anodic oxide film 109 is not a problem. This is because the gate electrode made of aluminum has a large thickness, and the electrical conductivity does not change noticeably due to the impact of ions. Further, the anodic oxide film 109 does not cause any particular problem.

However, the source region 201 and the drain region 205, the low-concentration impurity regions 202 and 204, and the region 206 of the gate insulating film 110 into which the impurity ions are implanted are damaged by the impact of the implanted ions.

Specifically, in the source region 201, the drain region 205, and the low-concentration impurity regions 202 and 204, those having crystallinity become amorphized by the impact of the implanted ions. Also, ion bombardment causes many defects. That is, the implantation of the impurity ions causes the active layer to become amorphous (not always completely made amorphous). Further, the implantation of the impurity ions causes defects at high density in the active layer.

Also, the region 206 of the gate insulating film 110 is damaged by the implantation of the impurity ions, and defects are formed at high density.

Recrystallization of the active layer amorphized by the implantation of the impurity ions, annealing of defects formed in the active layer, and annealing of defects formed in the gate insulating film are performed at 800 ° C. or higher. It can be preferably carried out by adding heat treatment at a high temperature of 950 ° C. or higher.

However, when a glass substrate having a low heat resistance (generally, its strain point is 700 ° C. or lower) is used, it is impossible to add the heat treatment at the above high temperature. Therefore, in this embodiment, annealing is performed by irradiating with laser light.

According to this method of irradiating laser light, the active layer can be annealed, but the gate insulating film cannot be annealed. This is because the laser light is transmitted to the silicon oxide film forming the gate insulating film.

If a laser having a corresponding single wavelength (about 100 nm or less) of 10 eV or more is used, the silicon oxide film can be effectively annealed.
Such lasers have not been commercialized for commercial use.

Therefore, the defects formed in the region 206 of FIG. 2A cannot be annealed by laser light irradiation.

Therefore, in the configuration shown in this embodiment,
After the impurity ion implantation step shown in FIG. 2A, the exposed region of the gate insulating film 110 is removed by a dry etching method.

Here, etching mainly using CHF ₃ is used, and etching is performed by an etching method having vertical anisotropy.

Thus, as shown by 207, a state in which the gate insulating film 207 remains just below the gate electrode 107 and the surrounding anodic oxide film 109 is obtained. In the etching process of the exposed gate insulating film, a part of the exposed region 208 of the underlying silicon oxide film 102 is removed.

In this step, the gate electrode 10
Since the gate wiring extending from 7 is already formed, there is no particular problem even if the exposed underlying silicon oxide film is removed in the region 208. Thus, FIG.
The state shown in (B) is obtained.

Next, a silicon oxide film is formed as an interlayer insulating film 209 by plasma CVD to a thickness of 6000Å. Further, an ITO electrode is formed as the pixel electrode 210. Then, contact holes are formed to form a source electrode 211 and a drain electrode 212. Here, a stacked film of a titanium film, an aluminum film, and a titanium film is used as the source and drain electrodes. The drain electrode is the pixel electrode 2
It will be in the state of being connected to 10.

In the structure shown in FIG. 2C, the dimension indicated by 213 and the dimension indicated by 214 are the same or substantially the same. This is because the dimensions indicated by 213 and 214 are determined by the growth distance of the porous anodic oxide 108 formed in the step of FIG.

Normally, the growth of the anodic oxide indicated by 108 around the gate electrode is carried out symmetrically with respect to the gate electrode. Therefore, the growth distance of the formed anodic oxide 108 is also symmetrical about the gate electrode. As a result,
The dimensions indicated by 213 and 214 in FIG. 2C are the same or almost the same. This is a salient feature when utilizing the self-alignment process.

By adopting the manufacturing process shown in this embodiment, the low-concentration impurity region can be formed by utilizing the self-alignment process. A low OFF current characteristic can be realized by the action of the low concentration impurity region. The influence of damage to the gate insulating film that occurs when forming the low-concentration impurity region by using the self-alignment process can be eliminated. It is possible to obtain such effects at the same time.

[Embodiment 2] This embodiment is an example in which a silicon oxynitride film is used as a base film in the structure shown in Embodiment 1. In this embodiment, the parts and the manufacturing method thereof are the same as those described in the first embodiment unless otherwise specified.

First, as shown in FIG. 1A, the glass substrate 1
A silicon oxynitride film is formed as a base film 102 on 01. In this embodiment, a silicon oxynitride film is formed to a thickness of 3000 Å by the plasma CVD method using TEOS gas and N ₂ O gas as source gas.

The reason why the silicon oxynitride film is used as the base film here is to prevent the base film from being etched in the subsequent step of removing the gate insulating film. This utilizes the fact that the silicon oxynitride film and the silicon oxide film have different etching rates under a predetermined etching condition.

Next, the active layer 103 is formed, and then the silicon oxide film 100 which functions as a gate insulating film is formed. Then, an aluminum film 104 forming a gate electrode is formed, and a dense anodic oxide film 105 is formed on the surface thereof. After forming the anodic oxide film 105, a resist mask 106 for forming a gate electrode is arranged thereon. In this way, the state shown in FIG.

Next, the gate electrode 107 is formed by patterning the aluminum film using the resist mask 106. Next, anodic oxidation is performed with the resist mask 106 left to form a porous anodic oxide 108. (Fig. 1 (B))

Further, the resist mask 106 and the dense anodic oxide film 105 are removed, and the dense anodic oxide film 10 is newly added.
9 is formed. (Fig. 1 (C))

Then, the exposed gate insulating film (silicon oxide film) 100 is removed to obtain a state in which a part of the gate insulating film 110 remains, as shown in FIG.

After obtaining the state shown in FIG. 1 (D), the porous anodic oxide 108 is removed to obtain the state shown in FIG. 1 (E).

Then, in this state, impurity ions are implanted as shown in FIG. Then, the source region 201 and the drain region 205, which are high-concentration impurity regions, the low-concentration impurity regions 202 and 204, and the channel formation region 203 are formed in a self-aligned manner. At this time, the region 206 extending from the gate insulating film 110 made of a silicon oxide film is damaged by the impact of ions.

Then, as shown in FIG. 3B, the exposed gate insulating film is removed to remove the damaged region 2
06 can be removed. The exposed gate insulating film is removed by dry etching. At this time, the etching rate of the silicon oxynitride film 102 of the base film can be made sufficiently smaller than the etching rate of the gate insulating film 110 made of a silicon oxide film, so that the base film is apparently not etched. be able to. (Fig. 3
(B))

Then, an interlayer insulating film 209 is formed, a pixel electrode 210 is formed, a source electrode 211 and a drain electrode 212 are formed, and a thin film transistor is completed.

When the structure shown in this embodiment is adopted, in addition to the effect shown in the first embodiment, a structure in which the base film is not removed by etching can be obtained.

[Embodiment 3] This embodiment is characterized in that, in the structure shown in Embodiment 1, the base film 102 is composed of a laminated film of a silicon oxide film and a silicon nitride film. Here, the thickness of the silicon oxide film is 3000 Å and the thickness of the silicon nitride film is 500 Å.

When the structure as shown in this embodiment is adopted, the etching rate of the silicon nitride film can be made smaller than that of the silicon oxide film. It is possible to adopt a configuration in which the ground film is not etched.

[Embodiment 4] This embodiment is characterized in that in the structure shown in Embodiment 1, the gate insulating film is a laminated film of a silicon oxide film and a silicon nitride film. Here, an example in which a stack of a silicon nitride film—a silicon oxide film—a silicon nitride film is used as a gate insulating film is shown.

In the case of such a structure, since the laser light passes through the silicon oxide film in particular, it is difficult to anneal the defects formed in the silicon oxide film when the laser light is used. Becomes

Therefore, also in such a case, it is very useful to remove the region of the gate insulating film, which is implanted with the impurity ions, as shown by 206, as in the step shown in FIG.

[0088]

In a thin film transistor having a low concentration impurity region formed by using a part of a gate insulating film as a mask, a part of the gate insulating film damaged by the impact of impurity ions is removed to remove the gate. The influence of defects existing in the insulating film can be eliminated.

Further, by providing a low concentration impurity region between the source region and the channel forming region and between the channel forming region and the drain region, a low OFF current characteristic can be realized.

[Brief description of drawings]

FIG. 1 shows a manufacturing process of a thin film transistor.

2A to 2C show a manufacturing process of a thin film transistor.

FIG. 3 illustrates a manufacturing process of a thin film transistor.

FIG. 4 shows a manufacturing process of a conventional thin film transistor.

[Explanation of symbols]

101 glass substrate 102 base film (silicon oxide film or silicon oxynitride film) 103 active layer 104 aluminum film 105 dense anodic oxide film 106 resist mask 107 gate electrode 108 porous anodic oxide 109 dense anodic oxide film 100 gate Insulating film 110 Gate insulating film 201 Source region (high-concentration impurity region) 202 Low-concentration impurity region 203 Channel forming region 204 Low-concentration impurity region (LDD region) 205 Drain region 206 Region damaged by impact of implanted ions. 207 Gate insulating film 208 Region where base film is removed 209 Interlayer insulating film 210 Pixel electrode (ITO electrode) 211 Source electrode 212 Drain electrode

Claims (9)

[Claims] 1. A low-concentration impurity region is provided between a source region and a channel formation region and between a channel formation region and a drain region, and the low-concentration impurity region has the same or substantially the same dimension in the source / drain direction. The concentration of the impurity imparting one conductivity type in the low-concentration impurity region is lower than that in the source region and the drain region, and higher than that in the channel forming region, and on the low-concentration impurity region, A semiconductor device characterized by the absence of a gate insulating film. 2. A semiconductor device according to claim 1, wherein the gate insulating film is composed of a silicon oxide film. 3. A semiconductor device according to claim 1, wherein the gate insulating film is composed of a multilayer film containing a silicon oxide film. 4. The semiconductor device according to claim 1, wherein the gate insulating film contains silicon oxide. 5. A method of forming a source region and a drain region by implanting impurity ions using the gate electrode as a mask, which comprises an insulating film extending from a gate insulating film on the region to be the source and drain regions. In the state where the film is not formed and the insulating film extending from the gate insulating film is formed on the pair of regions immediately below the gate electrode and the regions to be the source and drain regions, one conductivity type is formed. Implanting impurity ions to be applied, forming source and drain regions and making the pair of regions low-concentration impurity regions, and removing the insulating film on the pair of regions, A semiconductor device characterized in that a concentration of an impurity imparting one conductivity type injected into a low concentration impurity region is lower than that in the source and drain regions. Of manufacturing. 6. A first step of implanting impurity ions to form a low-concentration impurity region by using as a mask a region extending from a gate insulating film left on a part of the active layer, and the gate after the step. A second step of removing a region extended from the insulating film, and in the first step, the source and drain regions are exposed, and the region is different from the low-concentration impurity region in comparison with the low-concentration impurity region. A method for manufacturing a semiconductor device, characterized in that a high concentration of impurities is implanted. 7. A method of manufacturing a semiconductor device according to claim 5, wherein the gate insulating film is composed of a silicon oxide film. 8. A method of manufacturing a semiconductor device according to claim 5, wherein the gate insulating film is composed of a multilayer film including a silicon oxide film. 9. The method for manufacturing a semiconductor device according to claim 5, wherein the gate insulating film contains silicon oxide.