JPH0964738A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress hunting caused when an analog signal is converted into a digital signal by comparing an output value with a present digital signal and storing a digital output signal as an output value when the comparison result indicates consecutively dissidence while a prescribed number of conversion clocks is counted. SOLUTION: A digital signal SD resulting from converting an analog voltage signal SA outputted from the A/D converter main body 1 is compared with a digital signal SDD being a current output stored in an output storage register 3 are compared by a prescribed number N of times. When the comparison for N times is dissident, that is, the dissidence of both is consecutive for N times, the arithmetic result of the converter main body 1 is stored in the output storage register 3 to configure a pseudo hysteresis means. Even when hunting takes place in the arithmetic result of the converter main body 1, hunting is surely eliminated from the digital signal SDO outputted from the output storage register 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital converter for converting an analog signal into a digital signal.

[0002]

2. Description of the Related Art As a conventional analog-to-digital converter, for example, as shown in FIG. 5, an analog input signal is input to an n-bit parallel comparison type analog-to-digital converter ADC so that the analog-to-digital converter ADC By comparing the analog input voltage with a plurality of threshold voltages, it is converted into a digital value and an n-bit digital output signal corresponding to the analog input signal is output.

[0003]

However, in the above-mentioned conventional analog-to-digital converter, assuming that the input analog signal has no noise component, and the converter itself does not have input conversion noise. As shown in FIG. 6 (a), when the analog input signal exceeds a certain threshold voltage, the output digital code changes as shown in FIG. 6 (b).
In an actual system, noise is always present, and if the analog input signal has not only signal components as shown in FIG. 7A but also white noise in the voltage range shown by the broken line as input conversion noise, the output code Has an unsolved problem of causing a so-called hunting phenomenon in which an analog input signal flutters near a threshold voltage as shown in FIG. 7B.

Therefore, the present invention has been made by paying attention to the unsolved problem of the above-mentioned conventional example, and can reliably suppress the hunting phenomenon when an analog signal is converted into a digital signal. It is intended to provide a converter.

[0005]

In order to achieve the above object, an analog / digital converter according to the present invention is an analog / digital converter for converting an analog signal into a digital signal, in which a conversion clock of a predetermined frequency is used. A clock signal generating means to be generated, a converter main body for converting an analog input signal into a digital output signal at a conversion clock timing of the clock signal generating means, and an output for storing the digital output signal of the converter main body as an output value. Value storing means, digital comparing means for comparing the output value stored in the output value storing means with the current value of the digital signal of the converter main body, and the conversion result of the digital comparing means is a predetermined number. The digital output signal is output by the output value storage means when the disagreement continues while counting the use clocks. It is characterized in that a storage controlling means for storing the value.

In the present invention, the converter main body sequentially converts the analog signal into a digital signal at the timing of the conversion clock, but the output value stored in the output value storage means is output to the outside. . Then, this output value is compared with the current value of the current converter main body by a digital comparator, and the comparison result is supplied to the storage control means, and the storage control means supplies a predetermined number of conversion clocks between counting. By storing the current value in the output value storage means while continuing the disagreement, the pseudo hysteresis means is configured to suppress the hunting phenomenon of the output value.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will now be described with reference to the drawings.
It will be described based on. FIG. 1 shows an embodiment of the present invention.
It is a block diagram. In the figure, 1 is the input analog power
Pressure signal S_AIs an n-bit digital signal S_DConvert to
For example, a parallel comparison type analog-digital converter
The converter body, which is an analog voltage signal S_AIs input
Input terminal t_AAnd conversion clock C_K1Is the latch signal
Input terminal t_CHas and latch
Input terminal t_CConversion clock C_K1Is entered each time
Analog voltage signal S_ADifferent threshold voltages are input (2
ⁿ-1) Compared with the threshold voltage with one comparator, and the comparison result
Is supplied to the encoder through a predetermined gate.
Latch the resulting digital signal and output n bits.
Force terminal t_DFrom digital signal S_DIs output.

[0008] Here, the clock input to the terminal t _C, conversion clock from the clock generation circuit 2 as a clock generating means for generating a conversion clock C _K1 of the predetermined frequency C _K1
Is entered. In addition to the conversion clock C _K1 , this clock generation circuit 2 is synchronized with this and delays more than the conversion time from the start of conversion of the analog voltage S _A of the converter main body 1 into a digital signal to the end of conversion. Generates a clock signal C _K2 .

As for the n-bit digital signal S _D output from the output terminal t _D of the converter main body 1, the latch signal _CL is input to the latch signal input terminal t _L of the output storage register 3 as the output value storage means. The conversion value stored at the timing and stored in the output storage register 3 is output from the output terminal t _O as the n-bit output digital signal S _DO .

On the other hand, the digital signal S _{D from the} converter body 1
And the digital signal S _DO stored in the output storage register 3 are input to the digital comparator 4 as the digital comparison means as the output value and the current conversion value, respectively, and when the two coincide with each other, It outputs a 1-bit comparison signal C _S that has a logical value “1” and a logical value “0” when they do not match.

Here, an example of the digital comparator 4 is, as shown in FIG. 2, n exclusive OR circuits XO corresponding to n bits of both input digital signals S _D and S _DO.
R _{1 to} XOR _n and these exclusive OR circuits XOR ₁ to
Each of the digital signals S _D output from the converter main body 1 is configured with one logical sum circuit NOR to which the output of XOR _n is input, and to one input side of each exclusive OR circuit XOR _{1 to} XOR _n. Each bit of the digital signal S _DO output from the output storage register 3 is input to the other input side.

Further, the conversion clock C _K2 generated by the clock generation circuit 2 is supplied to a comparison number counting counter 5 composed of, for example, a ring counter, and the comparison number counting counter 5 presets N conversion numbers. Clock C _K2
Pulsed counter output C _O becomes the logic value "1", for example, every counting the is output. Then, the comparison signal C _S output from the digital comparator 4 is input to the comparison result storage register 6. This comparison result storage register 6 is
For example, as shown in FIG. 3, the comparison signal C _s of the digital comparator 4 and the conversion clock C from the clock generation circuit 2
_The AND gate 4a to which _k2 is input, and the output of this AND gate 4a is input to the set terminal S and the reset terminal R
The counter output C _O of the comparison counter 5 is input to the RS flip-flop 4c via the delay circuit 4b.
And an AND gate 4d to which the output signal C _F output from the inverted output terminal of the flip-flop 4c and the counter output C _O of the comparison counter 5 are input, and the output of the AND gate 4d is a latch signal. is output to the latch signal input terminal t _L of the output storage register 3 as C _L.

[0013] Therefore, the flip-flop 4c, the counter output of the comparison number counting counter 5 C _O delay circuit 4
The output signal C _F that is reset when input to the reset terminal R via b and is output from the inverted output terminal
Becomes a logical value "1", and in this state, the conversion clock C
_It is set when the comparison signal C _S of the digital comparator 4 is a logical value "1", that is, when the digital signals S _D and S _{DO of the} converter body 1 and the output storage register 3 coincide with each other while _K2 is at a high level, When the output signal C _F becomes the logical value “0” and the comparison signal C _S maintains the logical value “0” until it is reset by the counter output C _O , that is, the digital signals S _D and S _DO When the disagreement state is maintained, the reset state is maintained without being set, and the output signal C _F thereof maintains the logical value “1”, which means that the count output C _O of the comparison number counter 5 is a logical value. When the value becomes "1", it is output as the latch signal C _L.

The comparison counter 5 and the comparison result storage register 6 constitute storage control means. Next, the operation of the above embodiment will be described. In the initial state, the output storage register 3, the comparison count counter 5, and the comparison result storage register 6 are cleared. In this state, an analog voltage signal S _A having a value other than “0” that fluctuates over time is input to the converter body 1, and the clock generation circuit 2 generates conversion clocks C _K1 and C _K2 . And an n-bit analog voltage signal S _A from the converter body 1 every time the conversion clock C _K1 is generated.
Then, the digital signal S _D corresponding to is output.

At this time, since the n-bit digital signal S _DO output from the output storage register 3 maintains "0", the digital comparator 4 outputs the digital signal S _D.
And a comparison signal C _S having a logical value “0” indicating that S _DO does not match is output. The conversion clock C _K2 is slightly delayed from the conversion clock C _K1 from the clock generation circuit 2.
Is generated, the comparison counter 5 is incremented by "1", but since the predetermined number N has not been reached, the counter output C _O maintains the logical value "0".
In the comparison result storage register 6, since the output of the AND gate 4a maintains the logical value "0" and the flip-flop 4c maintains the reset state, the output signal C _F of its inverting output terminal maintains the logical value "1". However, the counter output C
_{Since O} has the logical value "0", the latch signal C _L maintains the logical value "0", and the output storage register 3 maintains the clear state.

After that, every time the clock generation circuit 2 sequentially generates the conversion clock C _K1 , analog-digital conversion is performed in the converter main body 1, and an n-bit digital signal S _D is output from the output terminal t _D. This is compared with the digital signal S _DO which is the previous output value stored in the output register 3 by the digital comparator 4. At this time,
In the initial state, the digital signal S _DO which is the previous output value stored in the output storage register 3 represents “0”, while the digital signal S _D which is the calculation result of the converter body 1 is an analog signal. Since it has a value corresponding to the voltage signal S _A , the comparison signal C _S maintains the state of the logical value “0”, the flip-flop 4 c of the comparison result storage register 6 maintains the reset state, and the latch signal C _L Is a logical value "0"
To maintain the state.

After that, when the count value of the comparison count counter 5 reaches the predetermined value N, the count output C _O of the logical value "1" is output from the comparison count counter 5, so that the comparison result storage register 6 stores data. The AND gate 4d outputs a latch signal C _L having a logical value “1”, and the output storage register 3 stores the digital signal S _D representing the current value output from the converter main body 1 as an output value. It is output from the output terminal t _O.

On the other hand, in the comparison result storage register 6, the delay signal is output from the delay circuit 4b to the reset terminal R of the flip-flop 4c at a time point slightly delayed from the time point when the counter output C _O is output from the comparison number counter 5. Therefore, the flip-flop 4c is reset. Thus, the count output C from the comparison counter 5
Comparison is made when the digital signals S _D and S _{DO of the} converter main body 1 and the output storage register 3 continue to be inconsistent until the _O is output and the comparison signal C _S of the digital comparator 4 continues to be a logical value "0". The result storage register 6 supplies the latch signal C _L having the logical value “1” to the output storage register 3 to update the output value, but the analog voltage signal S _A input to the converter main body 1 is converted into white noise by input conversion. When the level of the analog voltage signal S _A is a value near the threshold voltage input to one of the comparators of the converter body as noise, as described in the above-mentioned section of the prior art. In addition, hunting occurs in the output code of the digital signal S _D output from the converter body 1.

In this state, a state occurs in which the digital signal S _D of the converter body 1 input to the digital comparator 4 and the digital signal S _DO of the output storage register 3 coincide with each other, and the comparison signal C _S is logical. The value becomes "1". Therefore, the flip-flop 4c of the comparison result storage register 6 is in the set state, and the output signal C _{F of the} inverted output terminal thereof is set.
Holds a logical value "0", and even if the comparison output counter 5 outputs the counter output C _O in this state, the latch signal C _L output from the AND gate 4d has a logical value "0". Becomes

Therefore, the output storage register 3 does not newly store the digital signal S _D of the converter body 1 but holds the currently stored digital signal S _DO as it is and outputs it from the output terminal t _O. It As a result, the digital signal S _DO output from the output terminal t _O has a value that reliably suppresses hunting. As described above, according to the above-described embodiment, the digital signal S _{D obtained} by converting the analog voltage signal S _A output from the converter body 1 into a digital value and the digital signal that is the current output value stored in the output storage register 3 are used. Compare the signal S _DO with a predetermined value N times,
When all of the N times do not match, that is, when the two mismatched states continue N times, the pseudo-hysteresis means is configured to store the calculation result of the converter main body 1 in the output storage register 3. Therefore, even if hunting occurs in the calculation result of the converter main body 1, the value of the digital signal S _DO output from the output storage register 3 is a value in which hunting is reliably removed.

In the above embodiment, the case where the clock generation circuit 2 generates two types of synchronized conversion clocks C _K1 and C _K2 has been described, but the present invention is not limited to this and one conversion is performed. Generates only the clock C _K1 for use in the converter, and supplies it directly to the converter body 1, and supplies it to the comparison counter 5 and the comparison result storage register 6 via a delay circuit for delaying the conversion time of the converter body 1. You may do it.

[0022] In the above embodiment has been described for the case of an n-number of the exclusive-OR circuit EXO ₁ ～EXO _n and one OR circuit OR corresponding digital comparator 4 to n bits, However, the number of exclusive OR circuits is less than n, depending on the maximum frequency and signal amplitude of the input analog signal and the conversion cycle of the converter main body 1.

That is, when the output code does not change more than 2 ^m (m <n) steps within the conversion time of N times in the converter main body 1, the digital comparator 4 includes m exclusive OR circuits. It can be configured with one logical sum circuit. The reason is that if the inputs of the m exclusive OR circuits are the lower m bits of the output code, the code will not change and the comparator output will not output coincidence within a change of 2 ^m .

Further, although the case where the comparison result storage register is configured to include the flip-flop 4c has been described in the above embodiment, the present invention is not limited to this, and the comparison signal C _S of the digital comparator 4 is converted into a conversion clock. Each time C _K2 is input, it is stored, and when the counter output C _O of the comparison counter 5 is input, the NAND output of the N stored comparison signals C _S is latched by the latch signal C _L. You may make it output as.

Furthermore, in the above embodiment, the case where the digital comparison means, the output value storage means, and the storage control means are configured by hardware has been described, but the present invention is not limited to this, and the arithmetic processing unit and the storage. The apparatus may be applied to perform arithmetic processing as shown in FIG. That is, the processing of FIG.
Each time the conversion clock C _K2 is input, it is executed as an interrupt process for the main program.
1 is the digital signal S _D which is the calculation result of the converter main body 1.
Is read, and then the process proceeds to step S2 to compare the read digital signal S _D with the current output value S _DO stored in the output value storage area of the storage device, and it is determined whether or not they do not match. If the two do not match, the process proceeds to step S3, the determination flag F is set to "1", and then the process proceeds to step S5, and if they match, the process proceeds to step S4 and the determination flag F is determined. Is reset to "0" and then the process proceeds to step S5.

In step S5, the count value N indicating the number of comparisons is incremented by "1", and then the process proceeds to step S6 to determine whether or not the number of comparisons N has reached a predetermined value N _S , and N < When it is N _S , the interrupt processing is ended as it is, and when N = N _S, it proceeds to step S7 and determines whether or not the determination flag F is set to “1”, and F = 1. Sometimes, the process goes to step S8 to output the digital signal S _D as the output digital signal S _DO , then the process goes to step S9, and the digital signal S _D is output.
_After updating and storing _D in the output value storage area, step S10
Then, the number of comparisons N is cleared to "0", the determination flag F is reset to "0", and then the interrupt process is ended.

When the determination result of step S7 indicates that the determination flag F is reset to "0", the process directly proceeds to step S10. In the process of FIG. 4,
The processing of steps S2 to S4 corresponds to the digital comparison means, the processing of steps S8 and S9 corresponds to the output value storage means, and the processing of steps S5 to S7 corresponds to the storage control means.

[0028]

As described above, according to the analog / digital converter of the present invention, the conversion result of the converter main body for converting an analog signal into a digital signal and the present value stored in the output value storage means are stored. The output value storage means stores the conversion result of the converter main body when the output value storage means compares the output value with the digital comparison means and the comparison result continues to disagree for a predetermined number of times. When hunting occurs in the conversion result of the converter itself within a predetermined number of times when it is near the threshold voltage of the converter main body, the previous value is held in the output value storage means. The effect that a digital signal in which hunting is suppressed can be output is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of the digital comparator of FIG.

FIG. 3 is a block diagram showing a specific configuration of a comparison result storage register in FIG.

FIG. 4 is a flowchart showing another embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is an explanatory diagram showing an ideal analog / digital conversion state in a conventional example.

FIG. 7 is an explanatory diagram showing an analog / digital conversion state in the case where input conversion noise is included in a conventional example.

[Explanation of symbols]

 1 converter main body 2 clock generation circuit 3 output storage register 4 digital comparator 5 comparison count counter 6 comparison result storage register

Claims (1)

[Claims] 1. An analog-to-digital converter for converting an analog signal into a digital signal, wherein a clock signal generating means for generating a conversion clock of a predetermined frequency and an analog input signal at the timing of the conversion clock of the clock signal generating means. To a digital output signal, an output value storage means for storing the digital output signal of the converter body as an output value, an output value stored in the output value storage means and the converter main body Digital comparison means for comparing the current value of the digital signal and digital output by the output value storage means when the comparison result of the digital comparison means continues to disagree while counting a predetermined number of the conversion clocks. An analog-digital converter, comprising: storage control means for storing a signal as an output value. .