JPH0963208A - Error correction device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use a circuit configuration of an error correction circuit and its software in common when an error is corrected at the time of recording and reproducing an MD and a DCC, which are different in algorithm. SOLUTION: A syndrome of the MD or a syndrome of the DCC is selectively calculated by a syndrome calculation block 22 based on an MD mode or a DCC mode decided by an instruction block 25. An error is corrected by a correction block 26 based on the syndrome of the MD or the DCC calculated by the syndrome calculation block 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention performs error correction at the time of recording / reproducing of MD (mini disc) and DCC (digital compact cassette) which employ both C1 series and C2 series dual Reed-Solomon codes. The present invention relates to an error correction device.

[0002]

2. Description of the Related Art FIG. 7 shows, as an example of a conventional recording / reproducing apparatus, a composite type which selectively records and reproduces digital signal format MD 31a and DCC 35a and analog signal format ACC (analog compact cassette) 39a. The recording / reproducing apparatus is shown. MD playback system is MD playback unit 31
And a signal processing circuit 32, and a DSP (digital signal processor) 33 and D for ATRAC audio expansion.
The A / A conversion circuit 34 is provided, and the DCC reproduction system has a DCC reproduction unit 35, a signal processing circuit 36, a PASC system audio decompression DSP 37, and a D / A conversion circuit 38. Also,
The ACC reproducing system has only the ACC reproducing unit 39. Then, in this circuit, the switching circuit 40 is used as a common circuit.
And an amplifier 41 and a speaker 42. MD
The reproduction system signal processing circuit 2 is composed of an EFM decoder, an MD error correction circuit and a CD-ROM decoder. The DCC reproduction system signal processing circuit 6 is an 8-10 modulation decoder and a DCC error correction circuit. It is composed by.

Here, in MD and DCC, a double Reed-Solomon (RS) code mainly consisting of a C1 sequence for random error correction and a C2 sequence mainly for burst error correction is cross-interleaved.
Then, the correction algorithm is different. That is, C1 of MD
The series consists of 32 words from W0 to W31 and is C2
The series is composed of 28 words from T0 to T27. Furthermore, the parity of MD is 4 words for both C1 and C2 series, and the erasure correction for the C2 series in the recording mode and during reproduction is up to 4 erasures.

On the other hand, the DCC C1 series has W0 to W
It consists of 24 words up to 23, and the C2 series is T0 to T
It consists of 32 words up to 31 words. Furthermore, DCC
The C1 and C2 series have a parity of 4 words and 6 words respectively, and the erasure correction of the C2 series in the recording mode and the reproduction is up to 6 erasures. Also, DCC
In addition to the C1 and C2 series main tracks, there are auxiliary tracks of only the C1 series.

C is used for error correction during reproduction of MD or DCC.
A series of corrections is performed first. In this C1 correction, 1 error correction, 2 error corrections, and detection of 3 or more errors are performed. As shown in Table 1, "no error correction", "1 error correction", and "2 error correction" are used as pointers indicating the correction status. , C3 flag (C1F = F0, F1, F2) indicating “3 errors or more and not corrected” is set. This C1
The flag C1F is used as information indicating an error position in C2 correction.

[0006]

[Table 1]

In the C2 correction, so-called erasure correction is performed to correct the error when the error position is known by the C1 correction, that is, when which word among the words in the C2 series is known. .
Here, since the word of the C2 series belongs to any block in the C1 series, C is used in the erasure correction.
For two series of words, the C1 flag C1F of the block of the C1 series to which the word belongs is read, and 1 error correction, 2 error corrections and 3 or more errors are detected. Subsequently, the position of the C1 flag C1F is regarded as an error position, erasure correction is performed up to 4 words in the MD and up to 6 words in the DCC, and if the correction is impossible, the interpolation flag is set.

[0008]

However, in the above-mentioned conventional apparatus, since the error correction circuit for MD and the error correction circuit for DCC are separately required, the circuit configuration and software are complicated and expensive. There is a problem.

In view of the above conventional problems, the present invention provides an error correction circuit for an MD and a DCC when performing error correction during recording / reproduction of an MD and a DCC having different correction algorithms.
It is an object of the present invention to provide an inexpensive error correction device that can be used both as a circuit configuration of an error correction circuit for software and software.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention determines whether MD mode or DCC mode is used and M
The syndrome of D or the syndrome of DCC is selectively calculated. That is, according to the present invention,
An error correction device that employs both C1 series and C2 series dual Reed-Solomon codes to perform error correction during recording / reproduction of MD and DCC, and mode determining means for determining whether the mode is MD mode or DCC mode. Syndrome calculating means for selectively calculating the syndrome of MD or the syndrome of DCC based on the mode judged by the mode judging means; and error correcting means for performing error correction based on the syndrome calculated by the syndrome calculating means. There is provided an error correction device having:

[0011]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing an embodiment of an error correction device according to the present invention, FIG. 2 is a block diagram showing an information recording / reproducing device equipped with the error correction device of FIG.
3 is a block diagram showing the signal processing circuit of FIG. 2 in detail, FIG. 4 is a flow chart for explaining the medium determination mode,
FIG. 5 is a flowchart for explaining a routine for correcting the C1 sequence of the Reed-Solomon code, and FIG. 6 is a flowchart for explaining a routine for correcting the C2 sequence of the Reed-Solomon code.

The error correction device shown in FIG. 1 is applied to an information recording / reproducing device as shown in FIGS. 2 and 3, for example, and this recording / reproducing device reproduces each signal recorded in MD 31a, DCC 35a and ACC 39a. And a composite type recording / reproducing apparatus for performing recording on such a medium. In this device, the MD reproduction unit 31 and the DCC reproduction unit 35
And a common signal processing circuit 50 in which the digital reproduction signals of the ACC reproducing section 39 and the AD conversion circuit 43 are shown in detail in FIG.
Is applied to

The signal processing circuit 50, as shown in FIG.
D reproduction system EFM decoder 501 and DCC reproduction system 8-
10 modulation decoder 502 and decoders 501, 5
Error correction of the signal demodulated by 02 is performed by the common error correction device 503 shown in detail in FIG. The MD reproduction signal error-corrected by the error correction device 503 is decoded by the CD-ROM decoder 504 into digital audio data. And the CD
The MD audio data decoded by the ROM decoder 504, the DCC audio data and the ACC audio data that are error-corrected by the error correction device 503 are selected by the switch SW according to the setting mode.

The signal thus processed by the signal processing circuit 50 is processed by the DSP 51, the DA conversion circuit 52, and the DSP 51 shown in FIG.
It is reproduced by the amplifier 41 and the speaker 42. DSP
Reference numeral 51 designates an MD instruction ROM 511 in which a signal processing procedure for complementary audio expansion of an MD reproduction signal audio-compressed by the ATRAC method is stored, and a PASC.
The DCC instruction ROM 512 in which a signal processing procedure for complementarily expanding the sound of the DCC reproduced signal compressed by the method is stored, and the noise subtraction signal is statistically calculated to improve the sound quality of the sound signal recorded in the ACC 39a. Sound quality improvement instruction ROM 51 in which noise subtraction data having a predetermined periodicity is stored
3

Next, referring to FIG. 1, the error correction device 50
The configuration of No. 3 will be described in detail. Circuits 2-20 are input terminals 1
The error correction circuit is configured to correct an error, and the parts 2 to 20 constituting the error correction circuit are composed of the syndrome operation block 22 including the circuits 2 to 8 and the circuit 9
To 14 and a correction block 26 including circuits 15 to 20. Also, the blocks 22, 23 and 26 are address blocks 24,
It is controlled by the instruction block 25 and the auxiliary track interrupt detection circuit 27. The auxiliary track interrupt detection circuit 27 includes blocks 22, 23 and 26.
Performs interrupt processing so as to selectively correct the C1 and C2 series of the main track of the DCC 35a and the C1 series of the auxiliary track, and is not used in the MD mode.

The error flag position detection circuit 2 is a circuit for evaluating the C1 error flag for erasure correction of the C2 series during reproduction, and corresponds to each word of the C2 series.
The 1-error flag is read to detect the position and number of 2-word error of C1 and error of 3 words or more. The circuit 2 also generates and outputs a RAM address for reading the error flag.

The parity location setting circuit 3 outputs the position of the parity to the location selection circuit 4 in accordance with each sequence of the sequences C1 and C2 in order to calculate the parity by using erasure correction during recording. In particular, when the mode of the DCC 35a having the auxiliary track is selected, the parity location setting circuit 3 outputs the position of parity to the location selection circuit 4 in accordance with the main track series C1 and C2 and the auxiliary track series AUXC1. The location selection circuit 4 selects the error position from the error flag position detection circuit 2 in the reproduction mode, selects the parity position from the parity location setting circuit 3 in the recording mode, and outputs it to the register output selection circuits 9 and 11. To do.

The syndrome check circuit 5 receives data from a RAM (not shown) input from the data bus 1 and, when the MD mode is selected, as described later, C1.
In the sequence, four syndromes Sp0 to Sp3 (Equation 1) are calculated, and in the C2 sequence, four syndromes Sq0 to Sq are calculated.
3 (Equation 2) is calculated, and on the other hand, when the DCC mode is selected, four syndromes Sp0 to Sp0 in the C1 sequence will be described later.
Sp3 (Equation 3) is calculated, and in the C2 series, six syndromes Sq0 to Sq6 (Equation 4) are calculated and output to the syndrome selection circuit 6. The syndrome selection circuit 6 selects the syndrome from the syndrome selection circuit 6 and the output from the register 19 or 16 and outputs it to the α-i conversion ROM 7 of the table for converting it into an exponent.

The syndrome storage register 8 stores α-i
The conversion ROM 7 stores the α-i converted syndrome, and this register 8 also outputs a flag “1” when all the stored syndromes are “00”. The register output selection circuits 9 and 11 select the syndrome stored in the syndrome storage register 8, the data selected by the location selection circuit 4 and the data stored in the register 14 and output them to the adder circuit 12, and also make corrections. The data symbol address latch circuit 10 stores the error position obtained by the calculation when executing the error correction, and outputs it to the RAM address output circuit 24.

The adder circuit 12 is a register output selection circuit 9,
The data selected by 11 is added. Since this addition is addition of the exponent part of α, the instruction is multiplication. The register input / output selection circuit 13 is the addition circuit 1
The output of 2 or the syndrome which is α-i converted by the ROM 7 is selected and stored in the register 14 in the subsequent stage. The register 14 is used to temporarily store the data during the calculation and output it to the register output selection circuits 9 and 11.

The i-α conversion circuit 15 performs an i-α conversion on the output of the adder circuit 12, and this data is added to the data stored in the register 19 by the exclusive OR circuit 17 and stored in the register 19 again. It When the value of "X" is input in order to obtain the solution "Z" of Z2 + Z + X = 0 at the time of correcting two words, the register 16 converts it to the value of "Z", stores it, and outputs it. The correction data output circuit 20 outputs the correction data obtained by the exclusive OR circuit 18 from the data from the i-α conversion circuit 15 and the error data on the data bus 1 onto the data bus 1.

The RAM address output circuit 24 includes a C1 series RAM address (C1RAMAD), a C1 series error flag RAM address (C1FLGAD), and a C1 series RAM address.
2 series RAM addresses (C2RAMAD) and C2 series error flag RAM addresses (C2FLGAD)
And error flag data of each series (ERFLGBUF)
Is generated and output.

Since the AUX information is not synchronized with the main data C1 and C2 at the time of reproduction, the auxiliary track interrupt detection circuit 27, which is used only when the DCC mode is selected, calculates and corrects in the form of interrupt, and inputs at the time of reproduction. The change point of the signal is detected and the interrupt flag is output.
There are four change points of the input signal in one frame, 1
The auxiliary track data is processed by two series for each time. The auxiliary track interrupt detection circuit 27 also uses the RAM address (AXC) of the auxiliary track data AUXC1 series.
1AD) and the RAM address (AXFLGAD) of the error flag of the auxiliary track data AUXC1 series are generated and output.

Next, the instruction circuit 25 will be described in detail. First, the clock generator (CLOCKGE).
N) generates various clocks used in this device from each input signal. Instruction counter (I
NSTCNT) is the C1 and C2 syndrome operation and C
This is a 10-bit counter for one error flag evaluation instruction, and the output of this counter is the address of the instruction ROM (INSTROM) 25a. One step of this instruction is from the rising edge of the clock to the rising edge, and is counted up by the clock. The jump of this instruction is performed by loading the following jump destination address into this counter.

The instruction ROM 25a outputs 16-bit data with the count value output from the instruction counter (INSTCNT) as an address, and this data determines the processing operation in each step of the instruction. The instruction selector (INSTSEL) is an instruction ROM 25a.
Output destinations of the 16-bit data output from are distributed according to the type of processing (syndrome operation, error flag processing, etc.). This output is output at the clock timing. Further, this selector outputs a signal for stopping the instruction when accessing the RAM.

The load address generator (LOADAD) reads the data in which the count value output from the instruction counter (INSTCNT) is latched, and when this data is an address for jumping, determines the jump destination address according to each input condition. Output to the instruction counter (INSTCNT).

Here, although the instruction of the syndrome calculation and the instruction of the correction process are in progress at the same time, the RAM cannot be accessed at the same time, so the instruction controller (INSTCONT) monitors the address so that the RAM access does not collide. It controls the instruction counter (INSTCNT). Further, although the syndrome calculation and the correction process are performed at the same time, since the sequence being corrected is the syndrome one sequence before the syndrome calculation performed at the same time, the flag controller (FLGCONT) stores information and flags related to the syndrome calculation. , This information and flags are used in the correction process.

In such a structure, MD31 or D
When error processing is selectively performed at the time of recording / reproducing CC35, as shown in FIG.
The mode is determined by (step S1), the MD error correction process is executed when the MD mode is selected (step S2), and the DCC error correction process is executed when the DCC mode is selected. Yes (step S3).

Next, the error correction processing and the erasure correction processing in FIGS. 5 and 6 will be described. 1. Error correction Error correction is performed on the received data by performing a syndrome operation (hereinafter referred to as syndrome check).
Correcting the position and value of the data based on the result. In this case, one error data has two unknowns (position and value), and since MD has 4 parity for both C1 and C2 sequences, error correction of up to 2 words is possible. Here, the syndromes Sp0 to Sp3 of the C1 series and the syndromes Sq0 to Sq3 of the C2 series in MD are respectively calculated by the following equations (Equation 1 and Equation 2), and the syndromes Sp0 to Sp3 of the C1 series in DCC are , C2 series syndrome Sq0
Sq5 is calculated as in the following equations (Equation 3 and Equation 4), respectively.

[0030]

[Equation 1]

[0031]

[Equation 2]

[0032]

(Equation 3)

[0033]

(Equation 4)

The 1-word and 2-word error correction will be described below. 1-1.1 Error correction When there is one error, the result of the thin check (S0
S3) is as follows, where Ei is the error magnitude and Xi is the error position.

[0035]

(Equation 5)

The correction process is performed by the data D at the memory address Xi.
i is read and the result of adding Ei is the memory address X
It ends by writing to i.

1-2.2 Error correction The syndrome in the case of two errors is Ei and Ej as the error size and Xi and Xj as the error position.

[0038]

(Equation 6)

It becomes There is also a method of obtaining four unknowns by solving these four simultaneous equations, but here, the equation of the root of the position is introduced to reduce the processing steps. First, the sum and product of error positions are defined.

[0040]

(Equation 7)

These Xi and Xj are the roots of the following equation F (Y).

[0042]

(Equation 8)

Expanding this equation,

[0044]

[Equation 9]

Since it is not possible to refer to the table in this format, if the variable is transformed into Y = C1 * Z, the above equation becomes

[0046]

(Equation 10)

It is possible to obtain Zi by using the contrast ROM 7 of C2 / C12 and Z, and obtain Xi and Xj by Xi = C1 * Z Xj = C2 / Xi. Also, C1,
C2 is given as a function of the syndromes S0 to S3.

[0048]

[Equation 11]

In the actual correction work, C1 and C2 are obtained, the result is referred to the control ROM 7, and the reference result is multiplied by C1 to obtain Xi. The error magnitudes Ei and Ej are

[0050]

(Equation 12)

The error correction of two words is completed by rewriting the data in the memory based on the above calculation result.

2. Erasure correction Erasure correction is a correction method in which the position of an error is known in advance and only the error value is obtained. In MD, since the number of C2 sequence parities is 4, it is possible to perform erasure correction of a maximum of 4 words. In addition, since the number of C2 sequence parities is 6 in the DDC, erasure correction of a maximum of 6 words can be performed. The erasure correction will be described in detail. First, the error positions are X1 to X.
6. With the error values Y1 to Y6, pre-calculation as shown in the following equation (Equation 13) is performed, and then the following equation (Equation 14 to 18)
The erasure correction of 6 to 1 word is carried out by.

[0053]

X1 + X2 = B1 X1 * X2 = B2 B1 + X3 = C1 B1 * X3 + B2 = C2 B2 * X3 = C3 C1 + X4 = D1 C1 * X4 + C2 = D2 C2 * X4 + C3 = D3 C3 * X1 * D4 = D4 = D4 X5 + D2 = E2 D2 * X5 + D3 = E3 D3 * X5 + D4 = E4 D4 * X5 = E5 (X1 + X6) * (X2 + X6) (X3 + X6) (X4 + X6) (X5 + X6) = X3 + X5) (X3 + X5) (X2 + X5) (X2 + X5) (X2 + X5) (X2 + X5) (X2 + X5) (X2 + X5) (X2 + X5) (X1 + X4) (X2 + X4) (X3 + X4) = I4 (X1 + X3) (X2 + X3) = I3 (X1 + X2) = I2

[0054]

[Equation 14] [6 Erasure, Y6] T5 = S5 + E1 * S4 + E2 * S3 + E3 * S2 + E
4 * S1 + E5 * S0 Y6 = T5 / I6 [Syndrome correction] S0 + Y6 → S0 S1 + Y6 * X6 → S1 S2 + Y6 * X62 → S2 S3 + Y6 * X63 → S3 S4 + Y6 * X64 → S4

[0055]

[Equation 15] [5Erasure, Y5] T4 = S4 + D1 * S3 + D2 * S2 + D3 * S1 + D
4 * S0 Y5 = T4 / I5 [Syndrome correction] S0 + Y5 → S0 S1 + Y5 * X5 → S1 S2 + Y5 * X52 → S2 S3 + Y5 * X53 → S3

[0056]

[4 Erasure, Y4] T3 = S3 + C1 * S2 + C2 * S1 + C3 * S0 Y4 = T3 / I4 [Syndrome correction] S0 + Y4 → S0 S1 + Y4 * X4 → S1 S2 + Y4 * X42 → S2

[0057]

[3 Erasure, Y3] T2 = S2 + B1 * S1 + B2 * S0 Y3 = T2 / I3 [Syndrome correction] S0 + Y3 → S0 S1 + Y3 * X3 → S1

[0058]

[Equation 18] [2Erasure, Y2] [1Erasure, Y1] T1 = S1 + X1 * S0 Y2 = T1 / I2 Y1 = S0 + Y2

Next, the C1 correction process will be described with reference to FIG. In this C1 correction process, D mode and D mode
In the CC mode, the syndrome calculation shown in step S102 is different from the parity position shown in step S115. When the C1 correction process starts (step S10)
1) First, the syndromes Sp0 to Sp3 are calculated by the above-described equation (Equation 1) in the MD mode and by the equation (Equation 3) in the DCC mode (step S102),
Next, the syndromes Sp0 to Sp3 are converted from α to i and stored in the register 8.

After step S102, it is determined whether the current operation mode is the recording mode (step 103).
This determination is made by setting a predetermined flag when the recording mode is set by the operation switch of the composite recording / reproducing apparatus shown in FIG. 2 and observing this flag. If it is not in recording mode, it is regarded as playback mode. That is, all rewinding modes other than recording and reproduction are also treated as reproduction modes. Step S below
The case in which the reproduction mode is determined in 103 will be described first.

In the reproduction mode, the syndromes S0 to S
It is determined whether all 3 are "0" (step 104), and Y
In the case of ES, "0" is written in each of the C1 error flags F0, F1, and F2 (step S105), and when all blocks are completed, the process proceeds to the C2 correction process shown in FIG. 6 (step S118). On the other hand, when all the syndromes S0 to S3 are not “0” in step S104, first,

[0062]

[Equation 19]

Based on, the modified syndromes σ1 to σ3 for detecting the one-word error are calculated (step S1
06) It is determined whether or not there is a one-word error (step S
107). In the case of a 1-word error, the 1-word correction described above is performed and the corrected data is written (step S10).
8) Then, based on Table 1 as well, "1" is written in the C1 error flag F0 (step S109). Next, when all the blocks are completed, the process proceeds to the C2 correction process shown in FIG. 6 (step S118).

On the other hand, if there is no one-word error in step S107, then as shown in the following equation (Equation 20), 2
X1, X2, φ1, φ2 for detecting word error
Is calculated (step S110), and then it is determined whether or not there is a two-word error (step S111).

[0065]

(Equation 20)

In the case of a 2-word error, 2-word correction is performed as described above to write the correction data Xi and Xj (step S112). Then, as shown in Table 1, the C1 error flag F1 is set to "1". Write (step S112). Next, when all the blocks are completed, the process proceeds to the C2 correction process shown in FIG. 6 (step S118).

If it is not a 2-word error in step S111, "1" is written in the C1 error flag F2 as shown in Table 1 (step S114), and if all blocks are finished, C2 shown in FIG. Proceed to the correction process (step S118).

If it is determined in step S103 that the recording mode is set, the parity position (W in MD mode) is set.
28 to W31, W20 to W23 in DCC mode are loaded (step S115), pre-calculation is performed (step S116), and 4 erasure correction is performed (step S1).
17). Next, when all the blocks are completed, the process proceeds to the C2 correction process shown in FIG. 6 (step S118).

Next, the C2 correction process will be described with reference to FIG. In this C2 correction process, in the MD mode and in the D mode
In the CC mode, the syndrome calculation shown in step S123 differs from the erasure correction shown in steps S136 and S142. This C2 correction processing is 1 error correction, 2
Error correction and detection of three or more errors are performed. Also, C
Erasure correction of up to 4 words in MD mode and up to 6 words in DCC mode is performed by regarding the position of 1 flag as an error position.

First, the C1 flag is read (step S
122). Here, the C1 flags of F0 and F1 indicate that 1 error correction and 2 error correction were performed in the C1 correction, and the C1 flag of F2 indicates that three or more errors were detected. There is a high probability of erroneously correcting 3 or more errors as 2 errors. Therefore, in the C2 correction, attention is paid to the numbers and positions of the F1 and F2 flags to perform the correction. Next, in MD mode, the syndromes Sq0 to Sq3 are calculated by the above-described equation (Equation 2), and in the DCC mode, the syndromes Sq0 to Sq5 are calculated by the equation (Equation 4).
Is calculated (step S122), and the syndrome is α
→ i-convert and store in register 8.

Then, similarly to the case of C1, it is judged whether or not the recording mode is set (step S124), and if it is the reproduction mode, the process proceeds to step S125 and thereafter. Step S125
In the following, the syndromes Sq0 to Sq3 (or Sq0 to Sq
It is determined whether the number of errors is "0" by determining whether all q5) are "0" (step S125),
In the case of "0", "0" is written in the C2 error flags F0, F1, and F2 (step S126).
The correction process ends (step S127).

On the other hand, when all the syndromes Sq0 to Sq3 (or Sq0 to Sq5) are not "0" in step S125, the modified syndromes σ1 to σ3 for detecting the one-word error are calculated (step S1.
28), and then it is determined whether or not there is a one-word error (step S129). In the case of a 1-word error, 1-word correction is performed and the corrected data is written (step S130), and then the C2 error flags F0, F1, F2 are written.
Write "0" to both (step S131).
2 The correction process ends (step S127).

On the other hand, if the one-word error is not detected in step S129, the modified syndromes X1, X2, φ1, and φ2 for detecting the two-word error are calculated (step S132), and it is determined whether or not there is a two-word error. It is determined (step 133). Then, in the case of a 2-word error, 2-word correction is performed to make correction data Xi, Xj.
Is written (step S134), then "0" is written in the C2 error flags F0, F1, and F2 (step S135), and the C2 correction process is finished (step S127).

If no two-word error is found in step S133, erasure processing of up to 4 words in MD mode and up to 6 words in DCC mode is performed (step S136), and then C2 error flag F0 if correctable. , F1 and F2 are both written with "0" (step S137 → S138), and the C2 correction process is terminated (step S127). If the correction is not possible in step S137, the C2 error flags F0, F1, and F2 are set to "0", "1", and
Write "1" or "1" to all (step S13
8), the C2 correction process is terminated (step S12).
7).

In the recording mode in step S124, the parity position is loaded (step S14).
0), pre-calculation is performed (step S141), and erasure correction is performed for up to 4 words in MD mode and up to 6 words in DCC mode to perform parity calculation (step S142).

The reason why the recording mode is different from the reproduction mode is that the parities of the C1 and C2 series must be calculated during recording. Since the position of parity is known in advance, erasure correction is applied and parity calculation is performed instead of error correction. As described above, since the error position is not known during reproduction, the error position was detected by writing an error flag by C1 correction and reading it during C2 correction, but the position of parity was known during recording. C
Parity calculation can be performed using erasure correction even in one sequence.

[0077]

As described above, according to the present invention, M
When the MD syndrome or the DCC syndrome is selectively calculated by judging the D mode or the DCC mode to perform the error correction, when the error correction is performed at the time of recording / reproducing the MD and the DCC having different correction algorithms. In addition, the circuit configuration and software of the error correction circuit for MD and the error correction circuit for DCC can be shared, so that an inexpensive error correction device can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an error correction device according to the present invention.

FIG. 2 is a block diagram showing an information recording / reproducing apparatus including the error correction device of FIG.

FIG. 3 is a block diagram showing in detail the signal processing circuit of FIG.

FIG. 4 is a flowchart illustrating a medium determination mode.

FIG. 5 is a flowchart illustrating a routine for correcting a C1 sequence of Reed-Solomon code.

FIG. 6 is a flowchart illustrating a routine for correcting a C2 sequence of Reed-Solomon code.

FIG. 7 is a block diagram showing an information recording / reproducing device provided with a conventional error correction device.

[Explanation of symbols]

22 syndrome calculation block (syndrome calculation means) 26 correction block (error correction means) 25 instruction block (mode determination means)

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[Procedure amendment]

[Submission date] December 25, 1995

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction contents]

The syndrome check circuit 5 receives data from a RAM (not shown) input from the data bus 1 and, when the MD mode is selected, as described later, C1.
In the sequence, four syndromes Sp0 to Sp3 (Equation 1) are calculated, and in the C2 sequence, four syndromes Sq0 to Sq are calculated.
3 (Equation 2) is calculated, and on the other hand, when the DCC mode is selected, four syndromes Sp0 to Sp0 in the C1 sequence will be described later.
Sp3 (Equation 3) is calculated, and six syndromes Sq0 to Sq 5 (Equation 4) are calculated in the C2 sequence and output to the syndrome selection circuit 6. The syndrome selection circuit 6 selects the syndrome from the syndrome selection circuit 6 and the output from the register 19 or 16 and outputs it to the α-i conversion ROM 7 of the table for converting it into an exponent.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0047

[Correction method] Change

[Correction contents]

It is possible to obtain Xi and Xj by obtaining Z by the contrast ROM 7 of C2 / C1 ² and Z and setting Xi = C1 * Z Xj = C2 / Xi. Also, C1,
C2 is given as a function of the syndromes S0 to S3.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0054

[Correction method] Change

[Correction contents]

[0054]

[Equation 14] [6 Erasure, Y6] T5 = S5 + E1 * S4 + E2 * S3 + E3 * S2 + E
4 * S1 + E5 * S0 Y6 = T5 / I6 [Syndrome correction] S0 + Y6 → S0 S1 + Y6 * X6 → S1 S2 + Y6 * X6 ² → S2 S3 + Y6 * X6 ³ → S3 S4 + Y6 * X6 ⁴ → S4

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0055

[Correction method] Change

[Correction contents]

[0055]

[Equation 15] [5Erasure, Y5] T4 = S4 + D1 * S3 + D2 * S2 + D3 * S1 + D
4 * S0 Y5 = T4 / I5 [Syndrome correction] S0 + Y5 → S0 S1 + Y5 * X5 → S1 S2 + Y5 * X5 ² → S2 S3 + Y5 * X5 ³ → S3

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0056

[Correction method] Change

[Correction contents]

[0056]

[4 Erasure, Y4] T3 = S3 + C1 * S2 + C2 * S1 + C3 * S0 Y4 = T3 / I4 [Syndrome correction] S0 + Y4 → S0 S1 + Y4 * X4 → S1 S2 + Y4 * X4 ² → S2

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0066

[Correction method] Change

[Correction contents]

In the case of a 2-word error, 2-word correction is performed as described above and the correction data Ei and Ej are written (step S112). Then, as shown in Table 1, the C1 error flag F1 is set to "1". writing (step S11 3). Next, when all the blocks are completed, the process proceeds to the C2 correction process shown in FIG. 6 (step S118).

[Procedure amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] 0070

[Correction method] Change

[Correction contents]

First, the C1 flag is read (step S
122). Here, the C1 flags of F0 and F1 indicate that 1 error correction and 2 error correction were performed in the C1 correction, and the C1 flag of F2 indicates that three or more errors were detected. There is a high probability of erroneously correcting 3 or more errors as 2 errors. Therefore, in the C2 correction, attention is paid to the numbers and positions of the F1 and F2 flags to perform the correction. Next, in MD mode, the syndromes Sq0 to Sq3 are calculated by the above-described equation (Equation 2), and in the DCC mode, the syndromes Sq0 to Sq5 are calculated by the equation (Equation 4).
Is calculated (step S12 3 ) and the syndrome is set to α
→ i-convert and store in register 8.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0073

[Correction method] Change

[Correction contents]

On the other hand, if the one-word error is not detected in step S129, the modified syndromes X1, X2, φ1 and φ2 for detecting the two-word error are calculated (step S132), and then it is determined whether or not there is a two-word error. It is determined (step 133). Then, in the case of a 2-word error, 2-word correction is performed to make correction data Ei, Ej.
Is written (step S134), then "0" is written in each of the C2 error flags F0, F1, and F2 (step S135), and the C2 correction process is finished (step S127).

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name]

[Correction method] Change

[Correction contents]

If there is no 2-word error in step S133, erasure processing of up to 4 words in MD mode and up to 6 words in DCC mode is performed (step S136), and then C2 error flag F0 if correctable. , F1 and F2 are both written with "0" (step S137 → S138), and this C2 correction process is terminated (step S127). If the correction is not possible in step S137, the C2 error flags F0, F1, and F2 are set to "0", "1", and
Write "1" or "1" to all (step S13
9 ), the C2 correction process is terminated (step S12).
7).

[Procedure amendment 10]

[Document name to be amended] Drawing

[Correction target item name] Fig. 1

[Correction method] Change

[Correction contents]

FIG.

[Procedure amendment 11]

[Document name to be amended] Drawing

[Correction target item name] Fig. 6

[Correction method] Change

[Correction contents]

FIG. 6

Claims (1)

[Claims] 1. An error correction device which employs both C1 and C2 series Reed-Solomon codes to perform error correction during recording / reproduction of MD and DCC, and which is a mode for determining whether the mode is the MD mode or the DCC mode. Determining means, a syndrome calculating means for selectively calculating the syndrome of MD or the syndrome of DCC based on the mode judged by the mode judging means, and error correction based on the syndrome calculated by the syndrome calculating means. An error correction device having: