JPH0955096A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor memory in which adjacent sub-chips of arbitrary numbers can be constituted as one chip. SOLUTION: This device is provided with a first circuit B000 which is provided with a discriminating circuit discriminating whether sub-chips S0-S3 is individually operated or not owing to cutting of a fuse and a second discriminating circuit discriminating positions of the sub-chips S0-S3 in one chip when plural sub-chips are operated. An input signal is transmitted through buffers B1, B2, B3, B4 switched by an output of the first circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a plurality of adjacent sub chips on a semiconductor substrate.
The present invention relates to a semiconductor memory device cut out as one chip.

[0002]

2. Description of the Related Art Semiconductor memory devices such as dynamic
Random access memory (DRAM) is increasing in storage capacity and is being reduced in yield. Therefore, it has been proposed to combine a plurality of sub-chips into one chip to improve the yield (for example, Japanese Patent Laid-Open No. Hei 4).
-7867). That is, the defect density on the wafer is determined by the manufacturing process and is almost constant. Therefore,
For example, as shown in FIG.
If the number of non-defective products is 1, the 256-Mbit DRAM is configured as shown in FIG.
The number of non-defective sub-chips is dramatically increased to 61. That is, if four 256 Mbit DRAM sub chips are combined to form one chip, three 1 Gbit DRAM chips are obtained, and the yield is improved.

In the DRAM sub-chip method in which four DRAM sub-chips described above are combined to form one chip, it is necessary to distribute the signal input to one sub-chip to all the chips (see FIG. 11). Buffers B01, B02, B
The control signal DQi is once collected in the center of the chip via 03, B04, and then the sub chips S00, S10, S20, S3 are collected.
Redistribute to 0. In the case of a DRAM adopting a clock cycle, the buffer B01 is composed of a known latch circuit, the buffer B02 is composed of two known inverters, and the buffer B03 is composed of a known DFF and a control signal DQi. Signal propagation within a clock cycle.

[0004]

However, in the case of a sub-chip method in which a sub-chip capable of operating independently is connected to form one chip, a circuit for operating independently and the above-mentioned plurality of circuits are connected to operate. However, there is a problem in that the chip size becomes large due to the coexistence of circuits. In addition, since the control circuits when operating the sub-chips independently and when operating the sub-chips are different, it is necessary to independently perform a functional test when connected, which causes a problem that the test time of the large-capacity memory becomes long. .

Therefore, an object of the present invention is to provide a semiconductor memory device in which one chip can be constituted by an arbitrary number of adjacent sub chips.

[0006]

According to another aspect of the present invention, there is provided a semiconductor memory device, wherein a plurality of sub-chips, each of which is capable of operating as a semiconductor memory device independently, are arranged on the semiconductor substrate. In a semiconductor memory device as a chip, a first determination circuit for determining whether the sub-chip operates the sub-chip alone or in plural, and a position of the sub-chip in the chip when operating the sub-chip in plural. It is a configuration including a first circuit including a second determination circuit for determining.

Further, the sub-chip of the semiconductor memory device of the present invention receives the signal from the input pin at one input and receives the signal from the adjacent sub-chip at the other input by the DFF and buffers the signal. It is also possible to employ a configuration including a second circuit having a switch that switches depending on the output.

Further, in the semiconductor memory device of the present invention, the chip is arranged in a square of the sub chip, and only the circuit located substantially in the center of the chip is activated by the output of the first circuit as a buffer of an input signal. It is also possible to adopt a configuration including a third circuit.

Furthermore, the semiconductor memory device of the present invention is
The third circuit other than the third circuit arranged in the center of the chip may be in a high impedance state by the output of the first circuit.

The semiconductor chip of the present invention may further include a fourth circuit in which the sub chip has a switch for receiving and switching the first output, and outputting the output to the other input of the second circuit. It can also be configured to be provided.

[0011]

1 is a plan view showing a first embodiment of a semiconductor memory device according to the present invention. The semiconductor memory device of this embodiment has four sub chips S0, S1,
One chip is composed of S2 and S3, and each of the sub chips S0, S1, S2 and S3 has the function of a 256 Mbit DRAM, and they are combined to form a 1 Gbit DRAM.

Although not shown, each sub chip is provided with a power supply pad and a ground pad, and the sub chips S0, S
Power is supplied to 1, S2 and S3, respectively. The sub-chip S0 includes a first determination circuit that determines whether to operate independently or a plurality of sub-chips S0, and a second determination circuit that determines where in one chip the sub-chip S0 is arranged when operated in plurality. And a first circuit B000 having Similarly, the sub chip S1 includes a first circuit B001, the sub chip S2 includes a first circuit B002, and the sub chip S3 includes a first circuit B003.

Further, the sub chip S0 has an external input signal D
A buffer B1 receiving Qi, a buffer B2 receiving the output of the buffer B1 via the internal signal A1, and a buffer B3 receiving the output of the buffer B2 via the internal signal A2 are provided. Each of the remaining sub-chips S1, S2 and S3 includes a buffer B4 that receives the output of buffer B3 via internal signal A3, and a buffer B1 'that receives the outputs of these buffers B4.

Next, details of the first circuit B0 will be described with reference to FIG. The first circuit B0 is composed of an N-channel MOS transistor NM0 and a fuse F0 connected in series, and an inverter IV0 connecting the drain terminal of the transistor NM0 to an input, which is a sub chip (S0 to S0).
3) The first to judge whether the output MC operates independently.
It has a judgment circuit. Further, the first circuit B0 has a second judgment circuit when a plurality of sub-chips (S0 to S3) form one chip, and the second judgment circuit has an N-channel MOS transistor NM1 and a fuse F1. And the inverter IV2 which is connected in series and whose drain terminal of the transistor NM1 is connected to its input to serve as the output MI1.

The first circuits B000, B001, B002 and B003 provided in the sub chips (S0 to S3) output signals (MC, MI0, MI1) according to the positions where the sub chips (S0 to S3) are arranged with 1 Gbit DRAM. ) Becomes high level (H) and low level (L) as follows.

[0016]

[Table 1]

That is, when each sub-chip (S0 to S3) is operated independently, the fuse F that produces the output signal MC
Do not cut 0. Therefore, the output signal MC becomes L.
1G-bit DR by connecting sub chips (S0 to S3)
When operating as AM, output signals MC, MI0, M
The fuses F0, F1 and F2 corresponding to I1 are shown in Table 1 above.
Cut so that

Next, each of the buffer B1 of the sub chip S0 and the buffer B1 'of the sub chips (S1 to S3) will be described with reference to FIG. This buffer B
Reference numerals 1 and B1 'are a latch circuit 30 which receives an external input signal DQi and operates with a clock signal CLK, a DFF 31 which receives a signal A4 and operates with a clock signal CLK, and signals MI0 and MI for determining a 1-Gbit DRAM configuration of a sub chip.
A signal MC including a NAND circuit 29 that receives an inverted signal of 1 and a signal MC that determines a single operation of the sub chip, a transfer gate composed of a transistor 34 and a transistor 35, and a transfer gate composed of a transistor 36 and a transistor 37. Output signal of the latch circuit 30 or DFF
And a switch circuit for switching the output signal of 31 to output the output signal A1 and the output signal A5.

The buffer B2 of the sub chip S0 is connected to the signal A
An inverter 41 of a known technique for shaping the waveform 1 is provided (see FIG. 4).

Next, the buffer B3 of the sub chips (S0 to S3) will be described with reference to FIGS. 4 and 5, respectively. Referring to FIG. 4, the buffer B3 includes a transistor 47 and a transistor 48.
2 outputs the output signal A2 and outputs the output signal A3, and the sub-chip selection signals (MC, MI0, MI
According to 1), the switch outputs the signal A2 as the output signal A3 or puts the output A3 in a high impedance state. Further, referring to FIG. 5, this buffer B3
Are arranged at the corners of the sub chip 51.

When the sub chips (S0 to S3) are used individually, that is, as a 256 Mbit DRAM, the signal lines (A3, A3 ') connecting the sub chips are short-circuited to the wafer cut surface, which may cause a failure. Become.

The buffer B3 is a sub chip (S0 to S).
3) operates independently, each sub chip (S0 to S)
3) All of the buffers B3 arranged in the square are signal M
Since C is at a low level, the output signal A3 becomes high impedance, and the signal A3 can be separated from the wafer cut surface.

When the sub chips (S0 to S3) are used as a 1 Gbit DRAM, the DRA as one chip
The buffer B3 corresponding to the position approximately in the center of M is selectively activated.

Next, referring again to FIG. 3, the buffer B4 will be described. The buffer B4 is a one-chip DRA.
The sub chips (S0 to S3) receive the outputs (A3, A3 ') of the buffer B3 arranged almost in the center of the M plane arrangement.
Corresponding sub-chip selection signal (MC,
A selector including NANDs 22 and 23 and an OR-NAND 24 for selecting the signal A3 or the signal A3 'by MI0, MI1), and a DFF 25 for operating the selected signal with the clock signal CLK.

As a result, each sub chip (S0 to S
The skew of the address signal A5 propagated in 3) can be substantially eliminated.

When performing the wafer test and the wafer test in the wafer manufacturing process of the semiconductor memory device of the first embodiment of the present invention, the output MC of the first determination circuit of the first circuit remains the fuse F0 connected, that is, the sub-chip. Since it can be operated independently, all the sub chips on the wafer can be electrically tested.

In the wafer test process, first, the quality of the sub-chip on the wafer is judged, and then, as shown in FIG. 12B, the sub-chips are good parts corresponding to the four sub-chips. Cut the fuse in the circuit 1
The quality of the GDRAM chip is judged. In addition, a portion not continuous with four is a 256M DRAM chip and a portion continuous with four is a 1G DRAM chip.

Next, a second embodiment of the semiconductor memory device of the present invention will be described. Referring to FIG. 6, in the semiconductor memory device of this embodiment, the buffers B1 and B1 ′ of the semiconductor memory device of the first embodiment are replaced by buffer B10.
Other components are the same as those in the first embodiment except that the components are replaced with 1. Further, the buffer B101 is an external input DQi.
From the signal A1 to the DF operating with the clock signal CLK
It has the same components as the buffer B1 except that F61 and F62 are added, and the same components are designated by the same reference numerals. That is, the output signal of the latch circuit 30 is synchronized with the clock signal CLK to work on the DFFs 61 and 62.

As a result, the clock latencies can be made uniform when the sub chips (S0 to S3) are operated independently and when they are operated as a 1G DRAM.

In the above description, the known technique shown in FIG. 7 may be used as the latch circuit and the known technique shown in FIG. 8 may be used as the DFF.

Next, a third embodiment of the storage device of the present invention will be described. FIG. 9 is a plan view showing this third embodiment. In the semiconductor memory device of this embodiment, one chip is composed of eight sub-chips (S0 to S8), and each sub-chip (S0 to S8) has the function of a 256 Mbit DRAM and is combined to form a 2 Gbit DRAM.

Although not shown, each sub chip is provided with a power supply pad and a ground pad.
Power is supplied to each of S8).

A first determination circuit for determining whether the sub-chip S0 is operated alone or a plurality of sub-chips is operated, and when operated by a plurality of sub-chips S0, it is determined at which position of the 2 G-bit DRAM as one chip the sub-chip S0 is arranged. A first circuit B000 having a second judging circuit for judging is provided.

Similarly, the sub chips S1, S2, S
Each of S3, S4, S5, S6 and S7 corresponds to the first
Circuit B001, B002, B003, B004, B0
05, B006, B007.

Further, referring to FIG. 10, the above-mentioned first circuit (B000 to B007) is connected in series with the second determination circuit of the first circuit of the semiconductor memory device of the first embodiment. A channel MOS transistor NM3 and a fuse F3 are added, a drain terminal of the transistor NM3 is connected to an input, an output MI3 and a fuse F3 are added, and a drain terminal of the transistor NM3 is connected to an input to output MI.
3 has the same configuration as that of the first circuit of the first embodiment except that an inverter IV3 of 3 is added to configure the second determination, and the same reference numerals are allotted to the constituent elements.

Although not shown, the sub chip (S0
S8) to S8) each have a buffer having the same configuration as the buffers B1, B2, B3, B4 of the semiconductor memory device of the first embodiment and signals having the same signals as A1, A2, A3, A4. .

When each of these sub chips (S0 to S8) is operated independently, the fuse F0 for producing the output signal MC is not cut and L is output to the output signal MC, as in the first embodiment. When operating the sub chips (S0 to S8) as a 2 Gbit DRAM, output signals MC,
Fuses F0, F corresponding to MI0, MI1, MI2
1, F2 and F3 are cut to obtain output signals MC, MI0, MI1 and MI2 corresponding to eight sub chips.

In the above description of the embodiment, four or eight adjacent sub-chips are used, but other numbers of sub-chips may be one chip. In this case, the buffer (B1,
B2, B3, B4) and signals (A1, A2, A3, A
4, A5) are the same, but the circuit configuration of the second determination circuit of the first circuit is different.

Further, the present invention can be applied to a static RAM or other semiconductor memory device in addition to the DRAM.

[0040]

As described above, according to the present invention, the position of a sub-chip in the case where a plurality of first decision circuits for deciding whether or not to operate the sub-chip independently are connected to form a single chip. Since the first circuit that includes the second determination circuit that determines according to the above is provided, the circuits can coexist and the degree of integration can be improved. In addition, since the functional test can be performed on each sub-chip independently, the test time can be shortened.

[Brief description of drawings]

FIG. 1 is a plan view showing a first embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a diagram showing a circuit configuration of a first circuit of FIG.

FIG. 3 is a diagram showing a circuit configuration of a buffer B1 and a buffer B4 of FIG.

FIG. 4 is a diagram showing a circuit configuration of a buffer B3 of FIG.

5 is a plan view showing the configuration of the sub chip of FIG. 1. FIG.

FIG. 6 is a diagram showing a circuit configuration of a buffer B101 and a buffer B4 of a second embodiment of a semiconductor memory device according to the present invention.

FIG. 7 is a circuit diagram showing an example of a latch circuit.

FIG. 8 is a circuit diagram showing an example of DFF.

FIG. 9 is a plan view showing a third embodiment of a semiconductor memory device according to the present invention.

10 is a diagram showing a circuit configuration of a first circuit of FIG.

FIG. 11 is a plan view showing a conventional semiconductor memory device.

FIG. 12 is a conceptual diagram on a wafer of a semiconductor memory device having a one-chip configuration with sub chips.

[Explanation of symbols]

21, 26, 27, 28, 33, 41, 43, 45, 7
1, 76, 77, 81, 86, 87, 91, 96, 9
7, IV0, IV1, IV2, IV3 inverters 22, 23, 29, 32, 44, 63 NAND 24 OR-NAND 25, 31, 61, 62 DFF 31 latches 34, 35, 36, 37, 46, 47, 48, 49,7
2,73,74,75,82,83,84,85,9
2, 93, 94, 95, NM0, NM1, NM2, NM
3 MOS transistors 51, S0, S1, S2, S3, S4, S5, S6, S
7, S00, S01, S02, S03 Sub chips A1 to A5, A01 to A04, A3 'Internal signals B1 to B4, B01 to B04, B1' Buffer B000 to B007 First circuit DQi External input signal MC sub chip connection signal MI0, MI1, MI2 Sub-chip position signal F0, F1, F2, F3 Fuse

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jutenori Muroya 5-7-1, Shiba, Minato-ku, Tokyo Inside NEC Corporation (72) Inventor Kentaro Shibahara 5-7-1, Shiba, Minato-ku, Tokyo Inside NEC Corporation (72) Inventor Ryuichi Oikawa 5-7-1, Shiba, Minato-ku, Tokyo Inside NEC Corporation (72) Hidemitsu Mori 5-7-1, Shiba, Minato-ku, Tokyo NEC Stock company (72) Inventor Shoichi Gan 5-7 Shiba, Minato-ku, Tokyo NEC Corporation Stock company (72) Inventor Kuniaki Koyama 5-7 Shiba, Minato-ku, Tokyo NEC Corporation In-house (72) Inventor Shinichi Fukuzawa 5-7-1, Shiba, Minato-ku, Tokyo NEC Corporation In-house (72) Inventor Toshiro Itani 5-7 Shiba, Minato-ku, Tokyo NEC Corporation (72) Inventor Kunihiko Kasama Tokyo 5-7-1, Shiba, Minato-ku, Nippon Electric Co., Ltd. (72) Inventor Takashi Okuda, 5-7-1, Shiba, Minato-ku, Tokyo (72), Inventor, Hideshi Oya, Tokyo 5-7-1, Shiba Ward, NEC Corporation (72) Inventor Masaki Ogawa 5-7-1, Shiba, Minato-ku, Tokyo Within NEC Corporation

Claims (5)

[Claims] 1. A semiconductor memory device in which a plurality of subchips adjacent to each other on a semiconductor substrate in which a plurality of subchips capable of operating independently as a semiconductor memory device are arranged into one chip, wherein the subchips are A first determination circuit for determining whether to operate a single sub-chip or a plurality of sub-chips, and a second determination circuit for determining the position of the sub-chip within the chip when operating the plurality of sub-chips. A semiconductor memory device comprising a first circuit. 2. The sub-chip has a switch that receives a signal from an input pin at one input, receives a signal from an adjacent sub-chip at the other input by a DFF, buffers the signal, and switches the output by the output of the first circuit. The semiconductor memory device according to claim 1, further comprising a second circuit. 3. A third circuit, wherein the chip is arranged in a square of the sub chip, and only a circuit located substantially in the center of the chip is provided with a third circuit activated as an input signal buffer by the output of the first circuit. Claim 1 characterized by the above-mentioned.
Alternatively, the semiconductor memory device according to item 2. 4. The third device arranged in the center of the chip.
4. The semiconductor memory device according to claim 3, wherein the third circuit other than the circuit of 1 is brought into a high impedance state by the output of the first circuit. 5. The sub-chip comprises a fourth circuit having a switch for receiving and switching the first output, and outputting the output to the other input of the second circuit.
Alternatively, the semiconductor memory device according to item 4.