JPH0951099A - Semiconductor device, manufacture thereof, display device and manufacture of the display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device such as a thin film transistor having a small irregularity in the characteristics. SOLUTION: A WSi2 film 2 is formed on a glass substrate 1, patterned, covered with an Si oxide film 3, which is covered with a polycrystal Si film 4, which is formed with a gate electrode via a gate insulating film 5, impurity regions to become source and drain region 6 is formed on the film 4, and the impurity regions are heat treated by an RTA method to be activated. The film 2 has an action for absorbing the heat of the RTA. The film 4 is heated directly and indirectly by the heat of the RTA and the heat radiated from the film 2 thereby to uniformly heat the entire film 4, and hence the activation of the impurities is conducted satisfactorily without irregularity.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a thin film transistor
(Thin Film Transistor) and other semiconductor devices, manufacturing methods thereof, and liquid crystal displays (LCD: Liqid Crystal Displa)
The present invention relates to a display device such as y) and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, active matrix LCDs
As a pixel driving element (pixel driving transistor) of
A thin film transistor using a polycrystalline silicon film formed on a transparent insulating substrate as an active layer (hereinafter referred to as polycrystalline silicon TF
(T) is under development.

Polycrystalline silicon TFTs have the advantage of higher mobility and higher driving capability than thin film transistors using an amorphous silicon film as an active layer. Therefore, if a polycrystalline silicon TFT is used, a high-performance LCD can be realized, and not only the pixel section (display section) but also the peripheral drive circuit (driver section) can be integrally formed on the same substrate.

In such a polycrystalline silicon TFT, as a method of forming a polycrystalline silicon film as an active layer, a method of directly depositing a polycrystalline silicon film on a substrate or an amorphous silicon film is formed on a substrate. Later, there is a method of polycrystallizing the same. Of these, the method of directly depositing the polycrystalline silicon film on the substrate is a relatively simple process of depositing at high temperature using, for example, the CVD method.

In order to polycrystallize an amorphous silicon film after depositing it, a solid phase growth method is generally used. This solid phase growth method is a method in which a polycrystalline silicon film is obtained by heat-treating an amorphous silicon film to polycrystallize the amorphous silicon film as it is. An example of a method for manufacturing a polycrystalline silicon TFT will be described with reference to FIGS.

Step A (see FIG. 16): An amorphous silicon film is formed on an insulating substrate (for example, quartz glass) 51 by a general low pressure CVD method, and further, in a nitrogen (N ₂ ) atmosphere, at a temperature of By performing a heat treatment at about 900 ° C., the amorphous silicon film is solid-phase-grown so that the polycrystalline silicon film 5 is formed.
Form 2 In order to use the polycrystalline silicon film 52 as an active layer of a thin film transistor, the polycrystalline silicon film 52 is processed into a predetermined shape by a photolithography technique and a dry etching technique such as an RIE method.

A reduced pressure C is formed on the polycrystalline silicon film 52.
A silicon oxide film as the gate insulating film 53 is deposited by using the VD method. Step B (see FIG. 17): After depositing a polycrystalline silicon film on the gate insulating film 53 by a low pressure CVD method, impurities are implanted into the polycrystalline silicon film and heat treatment is performed to activate the impurities. .

Next, after depositing a silicon oxide film 54 on this polycrystalline silicon film by the atmospheric pressure CVD method, the polycrystalline silicon film and the silicon are formed by using the photolithography technology and the dry etching technology by the RIE method. The oxide film 54 is processed into a predetermined shape. The polycrystalline silicon film is used as the gate electrode 55. Next, the self-alignment technique is used to implant impurities into the polycrystalline silicon film 52 using the gate electrode 55 and the silicon oxide film 54 as a mask to form the source / drain regions 56.

Finally, heat treatment is further performed to activate the impurities as the source / drain regions 56. Such a method is called a high temperature process because it uses a high temperature of about 900 ° C. during solid phase growth and impurity activation, and when a substrate with high heat resistance (for example, a quartz substrate) is used. Has the advantage that the processing time is short.

On the other hand, development using a low-temperature process, in which a relatively inexpensive glass substrate can be used without concern that the substrate is thermally strained, is also active. In particular, high performance is indispensable for the TFT, which is a driving device, and for this reason, various approaches have been taken such as improving the quality of the constituent material of the TFT using each process.

For example, a laser annealing method or an RTA method is used as a technique for activating an impurity region which influences device characteristics. In particular, the RTA method uses a high temperature of 700 ° C. or higher, but since it can be completed in an extremely short time, it does not adversely affect the substrate and can be activated in a short processing time.

[0012]

The laser annealing method has a problem that the activation process takes a long time because it is necessary to repeat beam scanning many times.
On the other hand, the RTA method has a problem that the temperature rise of the semiconductor film in which the impurity region is formed becomes non-uniform, which makes it difficult to perform good activation and deteriorates the device characteristics. In addition, when a large number of elements are manufactured, there is a problem that the characteristics of individual elements vary.

In particular, in a display device such as a liquid crystal display which uses several tens to several millions of these elements as pixel driving elements and peripheral driving circuit elements, the display is good due to variations in element characteristics. There is a problem that is not done. The present invention relates to a semiconductor device, a display device, and manufacturing methods thereof, and solves such problems.

[0014]

According to another aspect of the present invention, there is provided a semiconductor device including: a heat absorption film formed on a substrate; a semiconductor film formed on the heat absorption film; and a semiconductor film formed on the semiconductor film. A gate electrode formed via a gate insulating film, and an impurity region formed in the semiconductor film.

According to the semiconductor device of claim 2,
An insulating film is formed between the heat absorption film and the semiconductor film. Further, in the semiconductor device of the third aspect, the heat absorption film is provided substantially corresponding to the semiconductor film. Further, in the semiconductor device of the fourth aspect, the heat absorbing film uses a conductive material such as metal or a semiconductor material such as silicon.

According to the semiconductor device of claim 5,
The heat absorption film has a light shielding property. Further, in the semiconductor device of claim 6, a transparent substrate is used as the substrate. In the display device according to claim 7, the semiconductor device according to any one of claims 1 to 6 is used as at least one of a pixel driving element and a peripheral driving circuit element. Is.

Further, in the method of manufacturing a semiconductor device according to claim 8, a semiconductor film as an active layer of a transistor is provided on a substrate via a heat absorption film, and an impurity region provided in the semiconductor film. Is heat-treated and activated. Further, in the method of manufacturing a semiconductor device according to claim 9, a step of forming a heat absorbing film on the transparent substrate, a step of forming a semiconductor film on the heat absorbing film, and a step of forming a semiconductor film on the semiconductor film. , A step of forming a gate electrode via a gate insulating film, a step of forming an impurity region in the semiconductor film, and a step of heat-treating the impurity region to activate it.

Further, in the method of manufacturing a semiconductor device according to claim 10, a step of forming a heat absorption film on the transparent substrate,
A step of processing the heat absorbing film into a predetermined shape; a step of covering the heat absorbing layer with an insulating film; a step of forming a semiconductor film as an active layer of a transistor on the insulating film; In addition, the method includes a step of forming a gate electrode via a gate insulating film, a step of forming an impurity region in the semiconductor film, and a step of heat-treating the impurity region to activate it.

Further, in the method of manufacturing a semiconductor device according to claim 11, the semiconductor film is obtained by polycrystallizing an amorphous silicon film by heat treatment. In the method of manufacturing a semiconductor device according to claim 12, a laser annealing method is used for the heat treatment. Further, in the method of manufacturing a semiconductor device according to the thirteenth aspect, a conductive substance such as metal or a semiconductor substance such as silicon is used as the heat absorption film.

Further, in the method of manufacturing a semiconductor device according to the fourteenth aspect, the heat absorbing film has a light shielding property. In the method of manufacturing a semiconductor device according to claim 15, the RTA method is used as the heat treatment. According to the semiconductor device manufacturing method of the sixteenth aspect, a xenon arc lamp is used as a heat source of the RTA method.

Further, in a display device manufacturing method according to a seventeenth aspect, a semiconductor device manufactured by the semiconductor device manufacturing method according to any one of the eighth to sixteenth aspects is used as a pixel driving element and a peripheral device. It is used as at least one of the drive circuit elements. That is, since the heat absorption film has a function of absorbing heat and releasing the absorbed heat, according to the inventions of claims 1 to 6, the presence of the heat absorption film makes the activation state of the impurity region uniform. A semiconductor device can be obtained.

In particular, according to the third aspect of the invention, since the heat absorbing film has a size substantially corresponding to the semiconductor film, the function of the heat absorbing film is made to properly act on the necessary portion, and the other portion (for example, the substrate). Does not have a bad influence by heat. Further, according to the invention of claim 4, since the heat absorbing film is made of a conductive material or a semiconductor material, ions existing in the substrate are electrostatically shielded.

Further, according to the invention of claim 5, since the heat absorption layer has a light shielding property, when this is used for a display device such as an LCD, the amount of light directly entering the semiconductor device can be reduced. . Further, according to the invention of claim 7, it is possible to obtain an excellent display device using a uniform and excellent quality semiconductor device as a pixel driving element or a peripheral driving circuit element.

Further, according to the invention of claims 8 to 16,
It is possible to obtain a semiconductor device in which the impurity regions are well activated and uniform. In particular, according to the thirteenth aspect of the invention, since the heat absorption layer is a conductive material or a semiconductor material, the ions existing in the substrate are electrostatically shielded. Also,
According to the fourteenth aspect of the invention, since the heat absorption layer has a light shielding property, when this is used for a display device such as an LCD, the amount of light directly entering the semiconductor device can be reduced.

According to the fifteenth aspect of the invention, the RTA is used.
By using the method, impurities are activated in a short time without affecting the substrate. According to the sixteenth aspect of the invention, since the xenon arc lamp is used as the heat source of the RTA method, the heat absorption by the heat absorption layer is efficiently performed. According to the invention of claim 17, the uniform and excellent quality semiconductor device manufactured in a short time is used as a pixel driving element or a peripheral driving circuit element.
An excellent display device can be manufactured in a short time.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to FIGS. Step 1 (see Figure 1): on a substrate 1 such as quartz glass or alkali-free glass, by sputtering, a tungsten silicide (WSi _x) layer 2 (film thickness 1000 Å, except 50
Adjustable in the range of ~ 2000Å)).
In the sputtering method, an alloy target of W silicide is used. W silicide stoichiometry of (WSi _X) is X
= 2, but the composition of the alloy target is set to X> 2. This is because when the composition of the W silicide film 2 is close to X = 2,
Very large tensile stress occurs during the subsequent heat treatment,
This is because the W silicide film 2 may be cracked or peeled off. However, since the resistance value of W silicide is the lowest when X = 2, it is necessary to set the upper limit of X so that cracking or peeling does not occur.

Step 2 (see FIG. 2): the W silicide film
2 by using lithography technology and etching technology
Polycrystalline silicon as the active layer of the transistors mentioned
Process to the same pattern. Step 3 (see FIG. 3): the substrate 1 and the W silicide film 2
SiO to cover the ₂And insulating thin film 3 such as SiN
It is formed by a CVD method, a sputtering method, or the like. Specifically
Uses non-alkali glass as the substrate 1, and its surface
The formation temperature is 350 ° C. by the atmospheric pressure or low pressure CVD method.
And SiO of thickness 3000-5000Å₂Form a film
You.

The thickness of the SiO ₂ film, impurities in the substrate 1 by heat treatment or the like and the beam irradiation in the subsequent step is necessary thickness so as not to diffuse into the upper layer through the SiO ₂ film, 10
The appropriate range is 00-6000Å, 2000-6000
When set to Å, the diffusion prevention effect is good, of which 30
The case of 00 to 5000Å is most suitable. Also,
When SiN is used as the insulating thin film 3, the film thickness is appropriately in the range of 1000 to 5000Å, and 2000 to
The diffusion preventing effect is good when it is set to 5000Å, and among them, the case of 2000 to 3000Å is most suitable.

Step 4 (see FIG. 4): An amorphous silicon film 4a (film thickness 500Å) is formed on the insulating thin film 3. When this amorphous silicon film 4a is used as an active layer of a TFT, if the active layer is too thick, the off-current of the polycrystalline silicon TFT increases, and if it is too thin, the on-current decreases. The thickness of the crystalline silicon film 4a is
The range of 400-800Å is suitable, and the characteristic is good when it is set to 500-700Å, among which 500-600Å
Is most suitable.

There are the following methods for forming the amorphous silicon film 4a. Method using low pressure CVD: In order to form a silicon film by the low pressure CVD method, thermal decomposition of monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used. When monosilane is used, it becomes amorphous when the treatment temperature is 550 ° C. or lower, and becomes polycrystalline when the treatment temperature is 620 ° C. or higher. Then, at 550 to 620 ° C., the amount of amorphous containing fine crystals increases, and as the temperature decreases, the amount of amorphous becomes closer to amorphous and the amount of fine crystals decreases. Therefore, the amount of fine crystals in the amorphous silicon film 4a can be adjusted only by changing the temperature condition.

Method using plasma CVD method: To form an amorphous silicon film by plasma CVD method, thermal decomposition of monosilane or disilane in plasma is used.
In the actual process, the above method is adopted, and an amorphous silicon film containing no microcrystals is formed under the conditions of gas used: monosilane and temperature: 350 ° C. Step 5 (see FIG. 5): The surface of the amorphous silicon film 4a is scanned with a KrF excimer laser beam having a wavelength λ = 248 nm to perform an annealing treatment, and thus the amorphous silicon film 4a is processed.
Is melted and recrystallized to form a polycrystalline silicon thin film 4.

Laser conditions at this time are as follows: annealing atmosphere: 1 × 10 ⁻⁴ Pa or less, substrate temperature: room temperature to 600 ° C.
Irradiation energy density: 100 to 500 mJ / cm ² , scanning speed: 1 to 10 mm / sec (actually 0.1 to 1
It is possible to scan at a speed in the range of 00 mm / sec). As the laser beam, Xe having a wavelength λ = 308 nm is used.
A Cl excimer laser may be used. Laser conditions at this time are as follows: annealing atmosphere: 1 × 10 ⁻⁴ Pa or less, substrate temperature: room temperature to 600 ° C., irradiation energy density: 100
~ 500 mJ / cm ² , scanning speed: 1-10 mm / se
c (actually, scanning is possible at a speed in the range of 0.1 to 100 mm / sec).

Further, an ArF excimer laser having a wavelength λ = 193 nm may be used. The laser conditions in this case are as follows: annealing atmosphere: 1 × 10 ⁻⁴ Pa or less, substrate temperature:
Room temperature to 600 ° C, irradiation energy density: 100 to 500
mJ / cm ² , scanning speed: 1 to 10 mm / sec. Regardless of which laser beam is used, the grain size of polycrystalline silicon increases in proportion to the irradiation energy density and the number of irradiations. Therefore, if the energy density is adjusted so that the grain size of a desired size can be obtained. Good.

In this embodiment, a high throughput laser irradiation method is used for this excimer laser annealing. That is, in FIG. 14, 101 is a KrF excimer laser, 102 is a reflecting mirror that reflects the laser beam from the laser 101, and 103 is a laser that processes the laser beam from the reflecting mirror 102 into a predetermined state and irradiates the substrate 1. It is a beam control optical system.

In this structure, the high-throughput laser irradiation method means the laser beam control optical system 103.
A laser beam processed into a sheet shape (150 mm x 0.5 mm) is irradiated by superimposing a plurality of pulses, and stage scanning and pulse laser irradiation are perfectly synchronized, and laser irradiation is performed with extremely high precision overlap. By doing so, the throughput is increased.

Step 6 (see FIG. 6): In order to use the polycrystalline silicon film 4 as an active layer of a thin film transistor,
The polycrystalline silicon film 4 is processed into a predetermined shape by photolithography and dry etching by RIE. Then, an LTO film (Low Temperature) as a gate insulating film is formed on the polycrystalline silicon film 4 by a low pressure CVD method using a load lock type low pressure CVD apparatus.
Oxide: silicon oxide film 5 (thickness 1000 Å) is formed.

Step 7 (see FIG. 7): The gate insulating film 5
And an amorphous silicon film (film thickness 2
000Å) Deposit 6a. This amorphous silicon film 6a
Is doped with impurities (arsenic or phosphorus for N-type and boron for P-type) at the time of formation, but it may be deposited in a non-doped state and then the impurities may be implanted. Next, using a sputtering method, the tungsten silicide on amorphous silicon film 6a (WSi _x) layer 6b (thickness 1000 Å)
To form

Then, after depositing the silicon oxide film 7 on the W silicide film 6b by the atmospheric pressure CVD method, the polycrystalline silicon films 6a, W are formed by the photolithography technology and the dry etching technology by the RIE method. The silicide film 6b and the silicon oxide film 7 are processed into a predetermined shape. The amorphous silicon film 6a is used as the gate electrode 6 having a polycide structure together with the W silicide film 6b.

Step 8 (see FIG. 8): The gate insulating film 5
On the silicon oxide film 7 and the silicon oxide film 7, a silicon oxide film is deposited by the atmospheric pressure CVD method, and the entire surface is anisotropically etched back to thereby form the gate electrode 6 and the silicon oxide film 7.
Side walls 8 are formed on the sides of the. Then, using the self-alignment technique, the acceleration voltage: 80 KeV and the dose amount 3 are applied to the polycrystalline silicon film 4 by using the sidewall 8 as a mask.
Phosphorus (P) ions are implanted as impurities under the condition of × 10 ¹³ cm ^-2 to form the low-concentration impurity regions 9a.

Step 9 (see FIG. 9): The sidewall 8 and the silicon oxide film 7 are covered with a resist 10, and the self-alignment technique is applied again to the polycrystalline silicon film 4 using the resist 10 as a mask, an acceleration voltage: 80 KeV, and a dose. Amount 1 x
Phosphorus (P) ions are implanted as impurities under the condition of 10 ¹⁵ cm ^-2 to form high-concentration impurity regions 9b, thereby forming the source / drain regions 9 of LDD (Lightly Doped Drain) structure.

Step 10 (see FIG. 10): In this state, R
Rapid heating is performed by the TA (Rapid Thermal Annealing) method. That is, in FIG. 15, reference numeral 105 denotes a sheet-like light source that emits annealing light, which is constituted by a set of a xenon (Xe) arc lamp 106 and a reflecting mirror 107 that encloses the arc lamp 106 and which are vertically opposed to each other. There is. 10
Reference numerals 8 and 108 denote rollers for conveying the substrate 1, and 109.
Is a preheater for preheating, and 110 is an auxiliary heater for preventing the heated substrate from being rapidly cooled and cracked.

In such a structure, after the substrate 1 is preheated by the preheater 106, the sheet-shaped annealing light source 1
Heat treatment through 05. The RTA condition at this time is
Heat source: Xe arc lamp, temperature: 700 to 950 ° C. (pyrometer), atmosphere: N ₂ , time: 1 to 3 seconds.
Although heating by the RTA method uses high temperature, it can be completed in an extremely short time, so that there is no concern that the substrate 1 will be deformed.

If it is apprehended that a high temperature is suddenly applied to the substrate 1, RTA may be performed in plural times. That is, the time of each time is set to 1 to 3 seconds, and the temperature is changed each time the first time is repeated: 400 ° C. to the last time: 700 to 950.
Increase in steps such as ℃. Since the photoheat of the Xe arc lamp is absorbed more strongly in the amorphous portion and the silicide portion than in the polycrystalline portion, it becomes possible to heat only the necessary portion, and the low resistance of the (gate) wiring is obtained. Suitable for activation of impurities and impurities. Further, as will be described later, heating using the W silicide film 2 can be effectively performed.

By this rapid heating, the impurities in the source / drain regions 9 are activated and the amorphous silicon film 6a is polycrystallized. Furthermore, the polycrystal silicon film 6a and the W silicide film 6b are formed. The sheet resistance of the gate electrode 6 having a polycide structure is about 20 to 22
It drops to Ω / □. Further, the sheet resistance of the source / drain region 6 which has been subjected to the activation treatment is also 1 to 1.5 k
Ω / □, p-type is 1 to 1.2 kΩ / □, which is equivalent to the high temperature heat treatment by the diffusion furnace used in the high temperature process.

Particularly, in this embodiment, the polycrystalline silicon film 4 is used.
Corresponding to, the W silicide film 2 is formed thereunder. This W silicide film 2 has a function of absorbing the heat of the RTA, and the radiation heat from the W silicide film 2 which has absorbed the heat also activates the impurities in the polycrystalline silicon film 4. That is, the polycrystalline silicon film 4 is directly and indirectly heated by the heat generated by the Xe arc lamp and the radiant heat from the W silicide film 2 to uniformly heat and activate the entire polycrystalline silicon film 4. Work well without any variation.

The size of the W silicide film 2 is basically
It may be the same as or larger than that of the polycrystalline silicon film 4, but it is more preferable to adjust the area so as to correspond to the size of the pattern in the plane. That is, in the integrated semiconductor device, since the density of the pattern occurs on the substrate,
If the W silicide film 2 is evenly provided in each transistor, the heat absorption rate per unit area varies depending on the location, uniform heat treatment cannot be performed, and the temperature at the location where the W silicide film 2 concentrates is extremely high. There is a case where the substrate 1 becomes higher and is deformed.

Therefore, if the density per unit area of the heat absorbing film arranged in the lower layer is made to be substantially constant irrespective of the pattern formed in the upper layer, the temperature distribution is biased when activated by RTA. Can be resolved. Specifically, in a driver-integrated LCD panel, the density of transistors in the pixel portion is higher than that in the driver portion, so the size of the W silicide film 2 corresponding to the transistors in the driver portion is made larger than that in the pixel portion. As a result, the temperature distribution of the entire substrate 1 becomes substantially uniform.

In the LCD panel, it is preferable to adjust so that the W silicide film 2 occupies about 10% of the circuit area. Through this step, the polycrystalline silicon TFT (T
FT: Thin Film Transistor (A) is formed. Next, the polycrystalline silicon TFT manufactured as described above
L having a transmissive configuration using (A) as a pixel driving element
The structure of the pixel portion of the CD will be described with reference to FIG.

Step: Prior to forming the interlayer insulating film 11,
ITO is formed on the pixel region of the substrate 1 by the sputtering method.
(Indium Tin Oxide) storage electrode 12 for auxiliary capacitance
To form Process: The insulating film 13 is formed on the entire surface of the device. As a material of the insulating film 13, a silicon oxide film, a silicate glass, a silicon nitride film, or the like is used, and C
The VD method or PVD method is used.

Next, a contact hole for contacting the source / drain electrode 14 is formed in the insulating film 13, an ITO film is formed on the entire surface of the device including the contact hole by a sputtering method, and the ITO film is patterned. Then, the display electrode 15 is formed. Process: The transparent insulating substrate 1 on which the polycrystalline silicon TFT (A) is formed and the transparent insulating substrate 17 on which the common electrode 16 is formed are opposed to each other, and liquid crystal is sealed between the substrates 1 and 17. Thus, the liquid crystal layer 18 is formed. As a result, the pixel portion of the LCD is completed.

Next, FIG. 12 shows a block diagram of an active matrix type LCD in this embodiment. Each scanning line (gate wiring) G1 ... Gn, Gn + 1 ... G in the pixel section 19
m and each data line (drain wiring) D1 ... Dn, Dn + 1 ... Dm are arranged. The gate wirings and the drain wirings are orthogonal to each other, and the pixels 20 are provided in the orthogonal portions. Then, each gate wiring is connected to the gate driver 21, and a gate signal (scanning signal) is applied. In addition, each drain wiring is connected to a drain driver (data driver) 22 so that a data signal (video signal) is applied. A peripheral drive circuit 23 is configured by these drivers 21 and 22.

An LCD in which at least one of the drivers 21 and 22 is formed on the same substrate as the pixel portion 19 is generally a driver integrated type (driver built-in type).
It is called LCD. The gate driver 21 may be provided at both ends of the pixel unit 19. Further, the drain driver 22 may be provided on both sides of the pixel unit 19.

A polycrystalline silicon TFT manufactured by the same manufacturing method as that of the polycrystalline silicon TFT (A) is also used as a switching element of the peripheral drive circuit 23, and the polycrystalline silicon TFT (A) is manufactured in parallel. Then, they are formed on the same substrate. The polycrystalline silicon TFT for the peripheral drive circuit 23 adopts a normal single drain structure (not to mention the LDD structure) instead of the LDD structure.

By forming the polycrystalline silicon TFT of the peripheral drive circuit 23 in the CMOS structure, the size of each driver 21, 22 is reduced. FIG. 13 shows an equivalent circuit of the pixel 20 provided in a portion orthogonal to the gate line Gn and the drain line Dn. The pixel 20 includes a TFT (similar to the thin film transistor A) as a pixel driving element, a liquid crystal cell LC, and an auxiliary procedure CS. The gate of the TFT is connected to the gate wiring Gn, and the drain of the TFT is connected to the drain wiring Dn. The display electrode (pixel electrode) of the liquid crystal cell LC and the auxiliary capacitance (storage capacitance or additional capacitance) CS are connected to the source of the TFT.

The liquid crystal cell LC and the auxiliary capacitance CS form a signal storage element. The voltage Vcom is applied to the common electrode (electrode opposite to the display electrode) of the liquid crystal cell LC. On the other hand, in the auxiliary capacitor CS, a constant voltage VR is applied to the electrode on the side opposite to the side connected to the source of the TFT. The common electrode of the liquid crystal cell LC is literally a common electrode for all the pixels 20. Further, a capacitance is formed between the display electrode and the common electrode of the liquid crystal cell LC. In addition, in the auxiliary capacitance CS,
The electrode on the side opposite to the side connected to the source of the TFT may be connected to the adjacent gate wiring Gn + 1.

In the pixel 20 thus constructed,
When the gate wiring Gn is set to a positive voltage and a positive voltage is applied to the gate of the TFT, the TFT turns on. Then, the capacitance of the liquid crystal cell LC and the auxiliary capacitance CS are charged by the data signal applied to the drain wiring Dn. On the contrary, when the gate wiring Gn is set to a negative voltage and a negative voltage is applied to the gate of the TFT, the TFT is turned off, and the voltage applied to the drain wiring Dn at that time is the electrostatic capacity and the auxiliary capacity of the liquid crystal cell LC. Held by CS. As described above, by supplying a data signal to be written to the pixel 20 to the drain wiring and controlling the voltage of the gate wiring, the pixel 20 can hold an arbitrary data signal. The liquid crystal cell L depending on the data signal held by the pixel 20.
The transmittance of C changes and an image is displayed.

Here, important characteristics of the pixel 20 are a writing characteristic and a holding characteristic. The write characteristic is required to sufficiently write a desired video signal voltage to the signal storage element (the liquid crystal cell LC and the auxiliary capacitance CS) within a unit time determined from the specifications of the pixel section 19. The point is whether you can do it. What is required for the holding characteristic is whether or not the video signal voltage once written in the signal storage element can be held for a required time.

The auxiliary capacitance CS is provided in order to increase the electrostatic capacitance of the signal storage element and improve the writing characteristic and the holding characteristic. That is, the liquid crystal cell LC
However, there is a limit to the increase in capacitance due to its structure. Therefore, the auxiliary capacitance CS compensates for the shortage of the electrostatic capacitance of the liquid crystal cell LC. As described above, the polycrystalline silicon TFT manufactured according to the present embodiment can be performed by a so-called low temperature process, and a high quality polycrystalline silicon film is used as an active layer.

According to the experiments conducted by the present inventor, M of n channel
Mobility μn of OS type polycrystalline silicon TFT is 200c
It was found that it is possible to realize a high-performance transistor with m ² / V · S or more and a mobility μp in a p-channel MOS-type polycrystalline silicon TFT of 150 cm ² / V · S or more. In such a high performance TFT, for example,
= 50 cm ² / V · S, μp = 20 cm ² / V · S, which is sufficiently applicable to an NTSC television signal display LCD panel, and μn = 50 cm ² / V · S, μp =
20 cm ² / V · S, threshold voltage: 2 V (n channel), −5 V (p channel), S value (Sub-threshold sw)
ing): 0.2 V / decade, on / off ratio: 1 ×
10 ⁷ characteristics can be obtained.

Further, since the mobility is high, the driving capability of the TFT is improved, so that the size of the TFT can be reduced, and the size of the conventional transistor using amorphous silicon as the active layer (W / L = 34). / 10 μm),
The size can be reduced to ⅛ or less (W / L = 8/5 μm). Furthermore, since it is a high-quality active layer, the leak current when the transistor is off is small, and the area of the auxiliary capacitance can be reduced to 1/3 or less.

Specifically, the size is 2.4 type, the pixel pitch is 50.0 (H) μm × 1500 (V) μm, and the number of pixels is 230,000 dots (320 × 3 (RGB) × 240).
And while it has more than 3 times higher density pixels than the conventional panel, it has a high aperture ratio of 55% (compared to the conventional one: 1.5
It is possible to obtain a high brightness and a high brightness.
The above embodiment may be modified as follows, and in that case, the same operation and effect can be obtained.

1) Instead of the W silicide film 2, a semiconductor film such as an amorphous silicon film or a polycrystalline silicon film is used. These silicon films may be doped with impurities. By using a conductive film or a semiconductor film in this way, a voltage is applied to this heat absorption film, so that TF
The threshold voltage can be controlled by operating T as a 4-terminal device like a MOS transistor used in LSI, and when a glass substrate is used,
Since the ions in the substrate are electrostatically shielded, it is possible to prevent the deterioration of the characteristics of the transistor due to the ions in the glass substrate and the adverse effect on the TFT due to the potential formed by the movable ions.

2) Instead of the W silicide film 2, MoSi
Refractory metal silicides such as ₂ , TiSi ₂ , TaSi ₂ , CoSi ₂ and others, W, Mo, Co, Cr, Ti, T
A refractory metal such as a may be used. Further, when the operating temperature is low (about 450 ° C. or lower), a so-called low melting point metal such as Al or Au may be used. Since these metal films including the W silicide film have the property of not transmitting light, they have the following effects.

A) Since the light is prevented from being scattered and unnecessary light which obliquely enters the liquid crystal cell is blocked, the contrast of the LCD device is increased. b) Since the light that enters the TFT is blocked, the leak current due to the light is reduced to improve the characteristics of the TFT and prevent the deterioration of the TFT itself due to the light.

3) In step 4, the amorphous silicon film is formed by a low pressure CVD method using, for example, monosilane gas,
Deposit at a temperature of 580 ° C. As a result, the amorphous silicon film 4a becomes a film containing microcrystals. By polycrystallizing the amorphous silicon film containing microcrystals by the solid phase growth method, the crystal grain size decreases and the mobility slightly decreases, but the crystal growth can be completed in a short time.

4) In step 4, the amorphous silicon film 4
a is atmospheric pressure C regardless of the low pressure CVD method or the plasma CVD method.
VD method, photo-excited CVD method, vapor deposition method, EB (Electron Bea
m) It is formed by any one of a group consisting of a vapor deposition method, an MBE (Molecular Beam Epitaxy) method, and a sputtering method. 5) The threshold voltage (Vth) of the polycrystalline silicon TFT is controlled by doping the portion of the polycrystalline silicon film 4 corresponding to the channel region with impurities. In the polycrystalline silicon TFT formed by the solid phase growth method, the threshold voltage tends to shift in the depletion direction in the N-channel transistor and the threshold voltage tends to shift in the enhancement direction in the P-channel transistor. Further, when the hydrogenation treatment is performed, the tendency becomes more remarkable. To suppress the shift of the threshold voltage, the channel region may be doped with impurities.

6) The following steps are carried out instead of the above step 5. Step 5a: By performing a heat treatment at a temperature of about 600 ° C. for about 20 hours in a nitrogen (N ₂ ) atmosphere with an electric furnace,
The polycrystalline silicon film 4 is formed by solid phase growing the amorphous silicon film 4a. 7) The polycrystalline silicon film 4 formed in the step 5a has many defects such as dislocations in the crystals forming the film, and there is a possibility that an amorphous portion remains between the crystals, so that the leakage current is There are many fears.

Therefore, after the step 5a, the substrate 1 is rapidly heated by the RTA method or the laser annealing method to improve the film quality of the polycrystalline silicon film 2. 8) PVD other than the sputtering method in step 1 and step 7
Method (vacuum evaporation method, ion plating method, ion beam deposition method, cluster ion beam method, etc.)
Is used to form the W silicide films 2 and 6b. Also in this case, for the same reason as in the case of the above-described sputtering, setting the composition of the W silicide (WSi _X) to X> 2.

9) In steps 1 and 7, the CVD method is used.
Then, the W silicide films 2 and 6b are formed. Its source
As the gas, tungsten hexafluoride (WF₆) And Shira
(SiH_Four) May be used. The film forming temperature is 350 to
The temperature is around 450 ° C. In this case also,
For the same reason as in the case of the method, W silicide (WS
i _X) Is set to X> 2. CVD method is PVD method
The step coverage is better than that of the W silicide film.
The film thickness of can be made more uniform.

10) Not only the planar type but also the polycrystalline silicon TFT of any structure such as an inverted planar type, a staggered type and an inverted staggered type. 11) Not only for polycrystalline silicon TFTs, but also for insulated gate semiconductor devices in general. In addition, photoelectric conversion elements such as solar cells and optical sensors, bipolar transistors, static induction transistors (SIT: Static Induction Transistor).
It is applied to all semiconductor devices using a polycrystalline silicon film such as or).

[0071]

The present invention has the following excellent effects. 1) Due to the presence of the heat absorption film, it is possible to obtain a semiconductor device having a uniform activated state of the impurity region and excellent quality. 2) A semiconductor device having a good quality semiconductor film can be obtained in a short time.

3) A display device such as an LCD device having excellent display performance can be provided by using a semiconductor device having uniform characteristics and excellent quality as a pixel driving element or a peripheral driving circuit element.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining a manufacturing process of an embodiment embodying the present invention.

FIG. 6 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view for explaining a manufacturing process of an embodiment embodying the present invention.

FIG. 8 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 9 is a cross-sectional view for explaining a manufacturing process of an embodiment embodying the present invention.

FIG. 10 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 11 is a schematic cross-sectional view for explaining the method of manufacturing the pixel portion of the LCD.

FIG. 12 is a block diagram of an active matrix LCD.

FIG. 13 is an equivalent circuit diagram of a pixel.

FIG. 14 is a configuration diagram of an excimer laser annealing device.

FIG. 15 is a configuration diagram of an RTA device.

FIG. 16 is a cross-sectional view for explaining the manufacturing process of the conventional example.

FIG. 17 is a cross-sectional view for explaining the manufacturing process of the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 W silicide film (heat absorbing film) 3 Insulating thin film (insulating film) 4 Polycrystalline silicon film (semiconductor film) 5 LTO film (gate insulating film) 6 Gate electrode 9 Impurity region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 29/78 627G (72) Inventor Yoshihiro Morimoto 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Denki Co., Ltd. (72) Inventor Kiyoshi Yoneda 2-5-5 Keihan Hondori, Moriguchi City, Osaka Sanyo Denki Co., Ltd.

Claims (17)

[Claims] 1. A heat absorbing film formed on a substrate, a semiconductor film formed on the heat absorbing film, a gate electrode formed on the semiconductor film via a gate insulating film, A semiconductor device, comprising: an impurity region formed in a semiconductor film. 2. The semiconductor device according to claim 1, wherein an insulating film is formed between the heat absorption film and the semiconductor film. 3. The semiconductor device according to claim 1, wherein the heat absorption film is provided substantially corresponding to the semiconductor film. 4. The semiconductor device according to claim 1, wherein the heat absorption film is a conductive material such as metal or a semiconductor material such as silicon. 5. The semiconductor device according to claim 1, wherein the heat absorption film has a light shielding property. 6. The semiconductor device according to claim 1, wherein the substrate is a transparent substrate. 7. A display device using the semiconductor device according to claim 1 as at least one of a pixel driving element and a peripheral driving circuit element. 8. A semiconductor device characterized in that a semiconductor film as an active layer of a transistor is provided on a substrate through a heat absorption film, and an impurity region provided in the semiconductor film is heat-treated and activated. Manufacturing method. 9. A step of forming a heat absorbing film on a transparent substrate, a step of forming a semiconductor film on the heat absorbing film, and forming a gate electrode on the semiconductor film via a gate insulating film. And a step of forming an impurity region in the semiconductor film, and a step of heat-treating the impurity region to activate it. 10. A step of forming a heat absorbing film on a transparent substrate, a step of processing the heat absorbing film into a predetermined shape, a step of covering the heat absorbing layer with an insulating film, and a transistor on the insulating film. A step of forming a semiconductor film as an active layer, a step of forming a gate electrode on the semiconductor film via a gate insulating film, a step of forming an impurity region in the semiconductor film, and a step of forming the impurity region A method of manufacturing a semiconductor device, comprising the step of activating by heat treatment. 11. The method of manufacturing a semiconductor device according to claim 8, wherein the semiconductor film is formed by polycrystallizing an amorphous silicon film by heat treatment. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the heat treatment is performed by a laser annealing method. 13. The method of manufacturing a semiconductor device according to claim 8, wherein the heat absorption film is a conductive material such as metal or a semiconductor material such as silicon. 14. The method of manufacturing a semiconductor device according to claim 8, wherein the heat absorption film has a light shielding property. 15. The RTA method (Rapid Th) is used as the heat treatment.
ermal Annealing) is used.
15. The method for manufacturing a semiconductor device according to any one of items 14 to 14. 16. The method of manufacturing a semiconductor device according to claim 15, wherein a xenon arc lamp is used as a heat source for the RTA method. 17. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 8 is used as at least one of a pixel driving element and a peripheral driving circuit element. A method for manufacturing a characteristic display device.