JPH0944396A - Method for accessing set of storage positions in memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To access a set of storage places in a memory more efficiently than conventional by removing an unnecessary clock cycle during the access to adjacent storage places in an SDRAM. SOLUTION: A start address 1 and a number 2 of access words are given to a burst grouping circuit 3. This circuit 3 divides the access addresses into groups adapted to SDRAM burst and sends them to a group rearrangement circuit 4. This circuit 4 rearranges groups of SDRAM burst and sends them to a memory access circuit 5. The memory access circuit 5 accesses the SDRAM 6 to read/write memory data 7 from/in the SDRAM 6. This method is used to obtain the effect that extra clock cycles due to SDRAM '2n rule' are not required for access to desired data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a JEDEC standard SD for accessing adjacent data in a memory, for example.
The present invention relates to a method for accessing a set of storage locations in memory, which can be used in methods such as digital video image memory access rearrangement to reduce overhead due to RAM "2n rule", and in particular applicable to the realization of video processing system image memory.

[0002]

BACKGROUND OF THE INVENTION Many digital video image processing systems require an image memory used to store all or part of a digital video image. For example MPEG
-1 ("CD11172-Encoding of video and related audio for digital storage media up to about 1.5 Mbps"
International Organization for Standardization, ISO MPEG document ISO-IEC / JTC1 / S
C2 / WG8, 1992) and MPEG-2 ("IS
13818-Generic coding of moving images and related audio "International Standards Organization, ISO MPEG document ISO-IEC / JTC1 / SC2
/ WG11, 1994) require such memory to decode compressed video bitstreams, as do many other digital video processing systems.
Often digital video images are stored in raster scan order. In that case, the pixels are stored in memory in the same order as they would be scanned in a standard picture tube: left to right, top to bottom. One memory word may include a part of pixels or one or more pixels depending on the bit width of the memory and pixel data. See FIG. MPEG-
Many digital video systems, such as 1 and MPEG-2 encoders and decoders, require access to blocks of KxL pixels. When the data is stored in raster scan order, the blocks consist of a set of L contiguous locations. Each set is used to store at least K pixels. Those blocks need to both read and write to the image memory. See FIG.

Generally, RAM, DRAM and SDRAM are used to realize an image memory of a digital video system. To compare each type, each read timing can be described. When reading a RAM, the address of the desired pixel data is added to the address row, and after a while the data appears on the data row. See FIG. When reading a DRAM, you must first add the row address and then the column address to the address row,
After a while the data appears in the data row. After setting the first row address, a new column address can be added to the address row to provide the desired data output. See FIG. 7. When reading SDRAM ("JEDEC
Standard No. 21-C, Release 4, Individual Memory Configuration, 3.
Section 11, Synchronous Dynamic Random Access Memory (SD
RAM))), first the row address (start command) and then the column address (read command) must be added to the address line. See FIG. The commands and resulting data timing are directly related to the clock signal. Some time after applying the read command (1 to several clocks depending on the SDRAM mode used), a burst of data (eg 4 words) appears on the data row. It is possible to end a burst early by starting another read before the burst is complete.
Further, the SDRAM internally generates the address of the burst data by at least two methods of sequential and interleave. Image memories are generally best accessed using sequential addressing. In this case, for the 8-word burst, the 3 least significant bits of the address are 01-2-3-4-5-6-7
Follow the ring pattern. For example, if the applied column address has 3 least significant bits equal to 2, then the address used to access the data for the burst is 2-
It occurs in the order of 3-4-5-6-7-0-1. Despite the added complexity of using SDRAM, it offers desirable performance / cost ratios for digital video processing systems, especially for use in consumer applications such as MPEG-2 decoders. For this reason, many digital video processing systems currently and in the future manufactured by S
The DRAM is used as an image memory or other necessary data storage device.

[0004]

Digital video processing systems generally require a very high bandwidth data path to the image memory. As will be described below, it is an object of the present invention to eliminate unnecessary clock cycles during access to pixels in an image memory implemented using SDRAM. That is, it is an object of the present invention to eliminate unnecessary clock cycles during access to adjacent memory locations in SDRAM. This allows system designers to use low speed / low cost SDRAM to achieve the required data transfer rates required by the application.

Standard JEDEC SDRAMs have a so-called "2n rule" limitation on the timing of consecutive column addresses that applies to SDRAMs. That is, a new column address can be presented to the SDRAM every other clock cycle after the first read or write command.

However, this requires access to data that requires two or more bursts, and if the first burst is an odd access, until the 2n rule is satisfied before the second burst begins. It means that it has a problem that it has to wait for an extra clock cycle. See FIG.

In digital video processing systems, an odd number of data words are accessed within a burst, followed by one or more bursts of even data words, and possibly another burst of odd data words. It will be quite normal that this will be necessary. For example, a low cost MPEG-2 decoder would be made for consumer applications using one SDRAM with 16 Mbits. Due to the large data bandwidth requirements of MPEG-2, this memory is typically 2 banks x 512 kwords x 16 bits in order to allow the use of a 16 bit data bus. In this case, two pixels of 8 bits each occupy one data word. Continuous S
The DRAM address holds continuous pixel data. See FIG. FIG. 10 is a diagram illustrating an example of a raster scan memory mapping of a video image in SDRAM. In MPEG-2, for example, a reference macroblock of 17 pixels × 17 rows needs to be read in order to predict a macroblock being decoded. Since 17 pixels occupy 9 words (2 pixels / word), for a burst length of 8 words, at least 2 read commands are required to read 9 words for each row of the macroblock reference.

In view of such problems of the prior art, the present invention stores in SDRAM when one burst accessing an odd number of words is followed by one or more additional bursts of access. The extra clock cycles needed to access the data
It is an object to provide a method for accessing a collection of memory locations in memory. This is what is normally required in digital video processing systems.

[0009]

SUMMARY OF THE INVENTION The present invention of claim 1 is a method of accessing a set of locations in memory, wherein the locations in the set of locations are stored in one or more locations. Accessing a set of memory locations in memory comprising grouping into location groups, arranging the memory location groups into a sequence according to a predetermined rule, and accessing the memory location groups in the sequence. Is the way to do it.

The present invention according to claim 2 is a method of accessing a set of memory locations in a memory, wherein the memory is a synchronous dynamic random access memory (SDRAM).

The present invention according to claim 3 is a method of accessing a set of storage locations in a memory, wherein the set of storage locations comprises a selection of memory storage locations in the same memory page and bank.

The present invention as claimed in claim 4 is characterized in that each of the memory location groups comprises a selection of memory memory locations accessible by a burst transfer having a length equal to or less than N memory locations. A method of accessing a collection of storage locations.

In the present invention of claim 5, the N is the SD
A method of accessing a set of memory locations consisting of RAM transfer burst lengths.

According to the present invention of claim 6, the grouping is
A method of accessing a set of memory locations in memory is to select memory locations within each group such that the group having an odd number of memory locations is minimized.

According to the present invention of claim 7, the sequence is
A method of accessing a set of memory locations in memory in which every group of memory locations having an even memory location is followed by zero or more groups having an odd memory location.

The present invention of claim 8 is a method of accessing a set of storage locations in a memory, the access including reading and / or writing.

The present invention according to claim 9 relates to a storage location in memory comprising a set of adjacent memory storage locations having more storage locations than can be accessed using one SDRAM burst transfer. A way to access a set.

According to the tenth aspect of the present invention, the arranging step includes a step of determining the parity of the address of the first memory location, and if the parity is an even number, the arrangement of the sequence is the same as the order of the address of the memory location. And the group containing the first memory location is the last group of the sequence if the parity is odd, and the group of memory locations in the memory is accessed.

According to the present invention of claim 11, in the step of determining the parity of the address, if the least significant bit of the address is 0, the parity is an even number, and if the least significant bit of the address is 1. For example, the parity is an odd number, and a step of accessing a set of memory locations in memory.

In order to solve the above problems, the present invention invented a method for accessing a storage location in SDRAM.

Reading or writing to a set of storage locations within the same bank or page of an SDRAM according to the present invention, for example, groups the storage locations within the set of storage locations into a group of one or more storage locations. Where each of the storage location groups is an SDR.
A memory storage location that can be accessed using a burst transfer that is less than or equal to the length of the AM burst.
ry locations), the grouping comprises selecting storage locations within each group such that no more than two groups have an odd storage location.
Following this grouping procedure, the memory location groups are arranged such that all memory location groups having even memory locations are followed by groups having odd memory locations. The array can be determined by determining the parity of the address of the first memory location if the memory location set consists of a set of more contiguous memory memory locations than can be accessed using a single SDRAM burst transfer. . That is, if the parity is even, the sequence order is the same as the address order of the memory locations, and if the parity is odd, the group containing the first memory location is the last group of the sequence. This parity is even if the address of the first memory location is even, and odd if it is odd. By accessing the storage location group in the sequence, the standard JEDEC SDRA
According to the "2n rule" of M, whenever there are zero to one memory location groups with an odd memory location, no extra additional clock cycles are needed during the access of said memory location in memory.

The present invention eliminates the SDRAM "2n rule" overhead, for example, by rearranging memory accesses so that there are even clocks between read (write) commands. If an access burst with an odd number of accesses is required, the burst with the odd number of data is done last so that all the bursts with the even number of accesses can be done first. Because of the even number of accesses, the contiguous column address associated with the read (write) command can be applied to the SDRAM in even numbered clock cycles after the first command. Therefore, the "2n rule" is satisfied without accessing unnecessary memory locations. When accessing a contiguous set of memory locations,
The least significant bit of the first address indicates whether the group including the first address is the first to last group accessing the SDRAM. The size of a standard SDRAM burst is 4 to 8 accesses. If the first address is odd, an odd address remains in the SDRAM burst. Therefore, at the first address, it is determined whether the access group to which the first address belongs has an even or odd number of accesses.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of accessing an SDRAM as an embodiment according to the present invention will be described below with reference to the drawings.

FIG. 1 is an example of the structure of an apparatus for carrying out the method of this embodiment. In FIG. 1, 1 is a start address, 2 is the number of words to be accessed, 3 is a burst grouping circuit, 4 is a group rearrangement circuit, 5 is a memory access circuit, 6 is SDRAM, 7 is memory data input / output.
Is the output. The start address 1 and the access word number 2 are added to the burst grouping circuit 3. The burst grouping circuit 3 groups the access addresses into groups suitable for SDRAM bursts and sends them to the group rearrangement circuit 4. The group rearrangement circuit 4 rearranges the groups of SDRAM bursts and transfers them to the memory access circuit
Send to The memory access circuit 5 stores the memory data 7 in SD
S to read from or write to RAM6
Access the DRAM 6.

The operation of this embodiment will be described with reference to FIG. 3, which shows an operation example of each block in FIG. In the example shown in FIG. 3, the number of access words 2 is equal to 9, the burst length is 8 and the SDRAM CAS latency is 3.

"Step 1" of FIG. 3 shows an operation example of the burst grouping circuit 3. "Step 1" in Figure 3
Below are eight lists of nine hexadecimal numbers. The nine numbers correspond to the four least significant bits of the desired access address. 8 lists SD address how
It shows all combinations that need to be grouped into groups suitable for RAM bursts. In SDRAM, a burst length of 8 means that all SDRAM addresses that have the same bit except the 3 least significant bits can be accessed within a single burst transfer of 8 words. For example, in the first list, the 4 least significant bits are 0
To 8 addresses. It can be grouped into one group from 0 to 7 and another group consisting of 8. “Step 2” in FIG. 3 shows an operation example of the group rearrangement circuit 4. Under "step 2" in FIG. 3, there are eight lists of the same nine numbers as under "step 1". Under "Step 2", in each list, rearrange the two groups so that the first group contains an even number. Under "Step 3", SDRAM burst command and data timing examples are shown for each list of access addresses.

As shown in their timing diagrams under "Step 3", all SDRAM read commands (R
D) is applied at intervals consistent with the SDRAM "2n Rule". This rule specifies that the new column address in the RD command can only be applied every second clock after the first RD command. Moreover, their timing diagrams show that the data is accessed in 9 clock cycles. In other words, unnecessary data is not accessed while accessing the nine desired addresses. Therefore, the effect obtained by using the method of the present invention in this example is that the extra clock cycles due to the SDRAM "2n rule" are not required to access the desired data. FIG. 9 shows the timing of the RD command and data when the memory is accessed without using the method of the present invention. That is, it is a timing diagram according to the conventional method. In this case, some access lists are S
Accessing the DRAM requires at least 9 clocks or more.

The embodiment of FIG. 1 shows that the list of access addresses is identified using a starting address of 1 and an access word number of 2. It is also possible to identify the list of access addresses using methods such as using the start and end addresses in the list or any other method that completely identifies the access address to be accessed.

In one embodiment according to the present invention shown in FIG.
However, the present invention uses a specific CAS latency.
The waiting time is not limited. For example, a CAS latency of 1, 2, 3 or any other latency is possible.
In one embodiment according to the present invention shown in FIG. 3, a burst length of 8 is used, but the present invention is not limited to a particular burst length. Any burst length is possible, for example 4, 8 or any other burst length. Although the embodiment of the present invention shown in FIG. 3 describes the timing of read access, the present invention is not limited to reading. Write access to SDRAM using the present invention is also possible.

As another embodiment of the present invention, SDRA
Another example of a method of accessing M will be described below with reference to the drawings.

FIG. 2 shows another example of the structure of an apparatus for carrying out the method of this embodiment. In FIG. 2, 8 is a start address, 9 is the number of words to be accessed, 10 is a burst grouping circuit, 11 is a parity check circuit, 12 is a group rearrangement circuit, 13 is a memory access circuit, and 14 is SDRA.
M, 15 memory data input / output circuits, 16 is a parity. The start address 8 and the access word number 9 are added to the burst grouping circuit 10. Burst grouping circuit 10 groups access addresses into groups suitable for SDRAM bursts and sends them to group reordering circuit 12. The start address 8 is added to the parity check circuit 11. The parity check circuit 11 determines the parity 16 of the start address 8 and sets the parity 16 to the group rearrangement circuit 12
Send to Group rearrangement circuit 12 is a parity check circuit
Parity 16 from 11 is used to reorder the group of SDRAM bursts and send it to the memory access circuit 13.
The memory access circuit 13 transfers the memory data 15 to the SDRAM 14
SDRAM to read from or write to
Access 14.

The operation of this embodiment will be described with reference to FIG.
In this example, the number of access words 9 is equal to 9, the burst length is 8 and the SDRAM CAS latency is 3. “Step 1” in FIG. 3 is the burst grouping circuit 10
The operation example of is shown. For this example, the function of the burst grouping circuit 10 is the same as the burst grouping circuit 3 of the first embodiment. “Step 2” in FIG. 3 shows an operation example of the group rearrangement circuit 12. For this example, the function of the group rearrangement circuit 12 is the same as the group rearrangement circuit 4 of the first embodiment. Under “Step 2”,
For each list, rearrange the two groups so that the first group contains an even number. For this example, parity check circuit 11 determines whether the first group contains start address 8. The parity check circuit 11 of this example determines the parity 16 of the start address 8. Since the standard JEDEC SDRAM requires an even burst length of 4 to 8, the parity 16 of the starting address 8 also indicates whether there are even or odd accesses in the group containing the starting address 8. The starting address 8 has even parity if it is even and odd parity if it is odd. One way this can be determined is from the least significant bit of start address 8. If the least significant bit is 0, the start address 8 will be even. If the least significant bit is 1, the start address 8 is odd. The determined parity 16 indicates whether there is an even or odd access within the group including the start address 8. If the parity 16 is even, the parity check circuit 11 sends the parity 16 to the group rearrangement circuit 12. If the parity 16 is even, the group rearrangement circuit 12 does not change the order of the groups under "step 1". If parity 16 is odd,
The group rearrangement circuit 12 rearranges the order of the groups so that the group including the start address 8 becomes the final group. Below "Step 3", example timings for SDRAM burst commands and data are shown for each list of access addresses.

As shown in their timing diagrams under "Step 3", all SDRAM read commands (R
D) is applied at intervals consistent with the SDRAM "2n Rule". This rule specifies that the new column address in the RD command can only be applied every second clock after the first RD command. Moreover, their timing diagrams show that the data is accessed in 9 clock cycles. In other words, unnecessary data is not accessed while accessing the nine desired addresses. Therefore, the effect obtained by using the method of the present invention in this example is that the extra clock cycles due to the SDRAM "2n rule" are not required to access the desired data. FIG. 9 shows the timing of the RD command and data when the memory is accessed without using the method of the present invention. That is, it is a timing diagram according to the conventional method. In this case, some access lists require at least 9 clocks to access the SDRAM.

The embodiment of FIG. 2 shows that the list of access addresses is identified using a starting address of 8 and an access word number of 9. It is also possible to identify the list of access addresses using methods such as using the start and end addresses in the list or any other method that completely identifies the access address to be accessed.

In one embodiment according to the present invention shown in FIG.
However, the present invention uses a specific CAS latency.
The waiting time is not limited. For example, a CAS latency of 1, 2, 3 or any other latency is possible.
In the embodiment of the present invention shown in FIG. 3, a burst length of 8 is used, but the present invention described in the embodiment of FIG. 2 is not limited to a particular burst length. Any burst length is possible, for example 4, 8 or any other burst length. Although the embodiment of the present invention shown in FIG. 3 describes the timing of read access, the present invention is not limited to reading. Write access to SDRAM using this method is also possible.

Thus, according to the above embodiment, the extra clock cycle required to access the data stored in the SDRAM is eliminated by using the multiple burst access in which the first burst has an odd number of accesses. effective. This allows the same number of data words to be transferred in fewer clock cycles, increasing the efficiency of the memory data bus. This allows low speed, low cost SDRAM to be used in SDRAM based systems such as digital video processing systems, thus reducing costs.

[0037]

As is apparent from the above description, the present invention has an advantage that, when accessing a set of memory locations in a memory, it can be accessed more efficiently than before.

Yet another aspect of the present invention is for accessing data stored in SDRAM when a burst of accessing an odd number of words is followed by a burst of one or more additional accesses. It has the advantage of being able to eliminate the extra clock cycles required and making access more efficient than in the past.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating an embodiment according to the present invention.

FIG. 2 is a block diagram illustrating another embodiment according to the present invention.

FIG. 3 is a diagram illustrating an embodiment of steps constituting a method of the present invention.

FIG. 4 is a diagram illustrating raster scan memory mapping of video images.

FIG. 5 is a diagram showing how some video processing systems access pixel blocks in image memory.

FIG. 6 is a simplified timing diagram of an example of RAM read timing.

FIG. 7 is a simplified timing diagram of an example of DRAM read timing.

FIG. 8 is a simplified timing diagram of an example of SDRAM read timing.

FIG. 9 is a diagram illustrating an example showing a problem to be solved by the present invention.

FIG. 10 is a diagram illustrating an example of a raster scan memory mapping of a video image in SDRAM.

[Explanation of symbols]

 1 Start Address 2 Number of Words to Access 3 Burst Grouping Circuit 4 Group Reordering Circuit 5 Memory Access Circuit 6 SDRAM 7 Memory Data 8 Starting Address 9 Number of Words to Access 10 Burst Grouping Circuit 11 Parity Check Circuit 12 Group Rearrangement Circuit 13 Memory access circuit 14 SDRAM 15 Memory data 16 Parity

Claims (11)

[Claims] 1. A method of accessing a set of locations in memory, the steps of grouping the locations in the set of locations into one or more groups of locations. A method of accessing a set of memory locations in memory, comprising: arranging groups into a sequence according to a predetermined rule; and accessing the memory location groups in the sequence. 2. The method of accessing a set of memory locations in a memory as recited in claim 1, wherein the memory comprises a synchronous dynamic random access memory (SDRAM). 3. The method of accessing a set of memory locations in memory according to claim 2, wherein the set of memory locations comprises a selection of memory memory locations in the same memory page and bank. 4. The memory location group of claim 2, wherein each of the memory location groups comprises a selection of memory memory locations accessible using a burst transfer of length less than or equal to N memory locations. A method of accessing a set of storage locations in memory as described in 3. 5. The method of accessing a set of memory locations in memory of claim 4, wherein N comprises the SDRAM transfer burst length. 6. The method of claim 3, 4 or 5, wherein the grouping is to select memory locations within each group such that a group having an odd memory location is minimized. A method of accessing a collection of memory locations. 7. The sequence is characterized in that every group of memory locations having an even memory location is followed by zero or more groups having an odd memory location. 7. A method of accessing a set of storage locations in memory as described in 6. 8. A method of accessing a set of memory locations in a memory according to any one of claims 1 to 7, characterized in that the accessing comprises reading and / or writing. 9. The set of storage locations is a single SDRA.
Accessing a set of memory locations in a memory according to any one of claims 2 to 8, characterized in that it comprises a set of contiguous memory memory locations having more memory locations than can be accessed using M burst transfers. how to. 10. The step of arranging comprises the step of determining the parity of the address of the first memory location; the step of arranging the sequence being the same as the order of the addresses of the memory locations if the parity is an even number; The group containing the first memory location being the last group of the sequence if the parity is odd. How to access the collection. 11. The step of determining the parity of the address comprises: if the least significant bit of the address is 0, the parity is even; and if the least significant bit of the address is 1, the parity is odd. 11. The method of accessing a set of storage locations in memory according to claim 10, comprising: