JPH09331250A - Charge pump circuit and pll frequency synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the fluctuation of the output current of a charge pump circuit caused by the power supply voltage or temperature fluctuation by causing the circuit to sweep or suck a current in accordance with the phase difference between a comparative signal front the output signal of a voltage-controlled oscillator(VCO) and an inputted reference signal. SOLUTION: A frequency divider 20 divides the frequency of the output signal of a VCO 18 at a variable frequency dividing ratio and inputs a comparative signal fp to a phase comparator 12. The comparator 12 compares the phase of the signal fp with that of a reference signal fr inputted from a reference oscillator 10 and outputs a prescribed voltage corresponding to the phase difference between both signals to a charge pump circuit 14. The circuit 14 sweeps or sucks a current in accordance with the input and outputs the swept or sucked current to a loop filter 16. The filter 16 outputs a control voltage which controls the transmitting frequency of the VOC 18 so as to correct the phase difference. When the circuit 14 makes the current sweeping or suction in such a way, the fluctuation of the output current of the circuit 14 on the sucked current side caused by the power supply voltage or temperature fluctuation can be suppressed remarkably.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit that performs a push-pull operation according to an input signal, and a PLL frequency synthesizer using the charge pump circuit.

[0002]

2. Description of the Related Art A PLL frequency synthesizer is a device that synchronizes the phase of an oscillating circuit with the phase of a high-precision reference signal to create another high-precision frequency, and can switch the frequency arbitrarily. It is used in local oscillators such as wireless communication devices.

The PLL frequency synthesizer is provided with a voltage controlled oscillator (hereinafter referred to as VCO) which changes its oscillation frequency according to the applied voltage to obtain a desired frequency. The VCO is connected to a frequency divider that divides its output signal by a variable frequency division ratio. VC divided by frequency divider
The output signal of O is used as a comparison signal for controlling the oscillation frequency of the VCO. The frequency divider is connected to a phase comparator that compares the phase of a reference signal from a reference oscillator that generates a reference frequency with the comparison signal that is the output of the frequency divider. The phase comparator compares the phases of the reference signal and the comparison signal input to the phase comparator and generates a predetermined output according to the phase difference. The phase comparator is connected to a charge pump circuit that sweeps out current, sinks current, or assumes a high impedance state according to the output of the phase comparator. A loop filter (hereinafter referred to as LF) that integrates the output of the charge pump circuit and outputs a voltage is connected to the charge pump circuit. The output of the loop filter is used as a control voltage for the VCO and controls the oscillation frequency of the VCO so as to correct the phase difference.

By thus constructing a frequency synthesizer using a PLL (Phase Locked Loop), the output signal of the VCO can be converged to a desired frequency. In the above PLL frequency synthesizer, the charge pump circuit shown in FIG.
There is a circuit as shown in FIG. 1 (for example, JP-A-6-338).
787).

The charge pump circuit shown in FIG.
Input terminal 23 connected to the first output terminal of the phase comparator
a and an input terminal 23b connected to the second output terminal of the phase comparator are provided. PNP transistor Tr
The base of 01 is connected to the input terminal 23a via the resistor R01. Between the base and the power supply voltage Vcc,
The resistor R02 is connected. PNP transistor Tr
The emitter of 01 is connected to the power supply voltage Vcc, and the collector of 01 is connected to the output terminal 24 of the charge pump circuit.

The base of the NPN transistor Tr02 is
It is connected to the input terminal 23b via the resistor R03.
A resistor R04 is connected between the base and the ground potential. The emitter of the NPN transistor Tr2 is grounded,
The collector is connected to the output terminal 24 of the charge pump circuit. Here, in a steady state in which a high level voltage is input from the input terminal 23a and a low level voltage is input from the input terminal 23b, the PNP transistor Tr01.
And the NPN transistor Tr02 are both off, and the output of the charge pump circuit is in a high impedance state. That is, no signal is output from the output terminal 24, and the LF connected to the next stage is held as it is.

When a low-level pulse is input from the input terminal 23a in this state, the PNP transistor Tr01
Becomes an operating state, and a sweep current pulse is output from the power supply voltage Vcc toward the output terminal 24. On the other hand, when a high level pulse is input from the input terminal 23b, N
The PN transistor Tr02 becomes active, and current is absorbed from the output terminal 24 toward the ground potential. As the output of the charge pump circuit, a suction current pulse is output.

In this way, the PNP transistor Tr
The charge pump circuit is configured by a push-pull circuit in which the current is swept out by 01 and the current is absorbed by the NPN transistor Tr02.

[0009]

The main characteristics required for the PLL frequency synthesizer are the following three characteristics. First is the frequency switching characteristic. The oscillation frequency fo of the VCO is expressed as fo = N × fr, where N is the frequency division ratio of the frequency divider and fr is the frequency of the reference signal. Therefore, when fr is constant, the oscillation frequency of the VCO can be switched by changing the frequency division ratio N of the frequency divider. In a wireless communication device such as a mobile phone, one frequency corresponds to one channel. Therefore, in order to switch channels at high speed, it is necessary to switch the oscillation frequency of the VCO at high speed.

Second, there is a reference leak characteristic.
The phase comparator has a cycle of 1 even in a state where the phases of the reference signal and the comparison signal match because of the characteristics of the logic circuit forming the phase comparator or to eliminate the dead zone of the phase comparator.
The phase comparison between the reference signal and the comparison signal is performed for each / fr,
Outputs a pulse with a very short width.

This pulse is attenuated by LF via the charge pump circuit and input to the control terminal of the VCO. Therefore, the output oscillation frequency of the VCO is the cycle 1 / fr
Therefore, a peak appears in the frequency of fo ± n × fr (n = 1, 2, 3, ...) With respect to the oscillation frequency fo in the output spectrum of the VCO. This peak is what is called a reference leak. Since this peak interferes with the adjacent channel, it must be suppressed as much as possible.

Third, there is a C / N characteristic. What is C / N?
This is the ratio of the output signal of the VCO to the noise near the oscillation frequency, and this ratio must be set large in order to perform stable communication. Here, assuming that the loop filter has a structure in which a connection element in which a resistor R _L and a capacitor C _L1 are connected in series and a capacitor C _L2 are connected in parallel as shown in FIG. 12, a PLL synthesizer The characteristics are

[0013]

[Equation 1] It is represented as In the equation, N is the frequency division ratio after frequency switching, and f _lock is the frequency [Hz] (± f
₍ Convergence is determined by _lock ), Δf _VCO is the hopping frequency [H
z], K _VCO is a VCO conversion gain [Hz / V], I _cp is a charge pump output current [A], t _lock is a frequency switching time [sec], ζ is a damping factor, and ωn is a loop band.

As is clear from the above equation, the frequency switching time t _lock that determines the frequency switching characteristic, the loop bandwidth ωn that affects the reference leak and C / N, and the damping factor ζ are the loop filter constants R _L and C _L1. ,
VCO conversion gain K _VCO , charge pump output current I _cp
Be affected by. Therefore, in order to stabilize the characteristics of the PLL frequency synthesizer, it is desirable to stably supply the output current I _cp of the charge pump circuit.

However, in the conventional charge pump circuit shown in FIG. 11, the input signal from the phase comparator is input to the resistor R0.
1 or R03 through transistor Tr01 or Tr0
The collector current of this transistor is used as the output current of the charge pump circuit, so when the base potential changes due to fluctuations in the power supply voltage, etc., the collector current, which becomes the output current due to the amplifying action of the transistor, increases significantly. There was something to do.

That is, as shown in FIG. 13, in the conventional charge pump circuit, the DC current amplification factor h _fe is large.
The fluctuation of the output current on the sink current side using the PN transistor was particularly large. For this reason, there has been a demand for a charge pump circuit capable of forming a PLL frequency synthesizer having a stable characteristic with a small fluctuation in output current with respect to fluctuations in power supply voltage and temperature.

An object of the present invention is to provide a charge pump circuit whose output current is not easily affected by fluctuations in power supply voltage and environmental temperature and which has a small circuit scale. Another object of the present invention is to provide a PLL frequency synthesizer using such a charge pump circuit.

[0018]

The above-mentioned object is to provide a sweep current generating means for generating a sweep current according to a first input signal, and a sink current generating means for generating a sink current according to a second input signal. A charge pump circuit for performing a push-pull operation, wherein the sink current generating means supplies a current based on the second input signal.
A current mirror circuit that has a current generating means and a second current generating means that forms a pair with the first current generating means and outputs the sink current that is substantially equal to the current based on the second input current. This is achieved by a charge pump circuit characterized in that By configuring the charge pump circuit in this way, it is possible to significantly suppress the fluctuation of the output current on the sink current side due to the fluctuation of the power supply voltage or the temperature.

In the above charge pump circuit, the sweep-out current generating means forms a pair with the first current generating means for flowing a current based on the first input signal, and the first current generating means. It is desirable to have a current mirror circuit having a second current generating unit that outputs the sweep current that is substantially equal to the current based on the first input current. By configuring the charge pump circuit in this manner, it is possible to significantly suppress the fluctuation of the output current on the sweep current side due to the fluctuation of the power supply voltage or the temperature.

In the above charge pump circuit, the sink current generating means or the sweep current generating means is a base of a transistor forming the first current generating means and a base forming a transistor forming the second current generating means. It is desirable to further have a base current compensation means for compensating the current. By configuring the charge pump circuit in this way, it is possible to correct the base current of the transistor that configures the current mirror circuit.

Further, in the above charge pump circuit, it is preferable that the second current generating means constituting the sink current generating means or the sweep current generating means has a plurality of transistors connected in parallel.
By configuring the charge pump circuit in this way, the output current can be adjusted to a desired value. Further, in the above charge pump circuit, the first current generating means constituting the sink current generating means or the sweep current generating means is connected to an emitter of a transistor constituting the first current generating means, and outputs The second current generating means, which has a first resistance for controlling a current and constitutes the sink current generating means or the sweep current generating means, is connected to an emitter of a transistor constituting the second current generating means. It is desirable to have a second resistor that controls the output current. By configuring the charge pump circuit in this way, the output current can be adjusted to a desired value.

Further, a voltage controlled oscillator whose oscillation frequency is controlled by an applied voltage, a frequency divider for dividing an output oscillation signal of the voltage controlled oscillator, a reference oscillation signal output from a reference oscillator, and the frequency divider. A phase comparator that compares the phase difference with the output oscillation signal of the voltage controlled oscillator divided by a frequency divider, and a phase comparator that generates an output pulse according to the phase difference, and a predetermined value based on the output pulse of the phase comparator. The charge pump circuit for generating a current output, and a loop filter for outputting a voltage signal according to the output of the charge pump circuit to the voltage controlled oscillator.
It is also achieved by the LL frequency synthesizer. By configuring the PLL frequency synthesizer in this way, the operational stability of the charge pump circuit with respect to fluctuations in the power supply voltage and temperature can be improved, so that a P having a stable frequency switching time and a stable VCO output can be obtained.
An LL frequency synthesizer can be obtained.

[0023]

DETAILED DESCRIPTION OF THE INVENTION A charge pump circuit and a PLL frequency synthesizer according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a PLL frequency synthesizer according to this embodiment, FIG. 2 is a circuit diagram showing a charge pump circuit according to this embodiment, and FIG. 3 is a power supply voltage dependence of a sink current and a sweep current in the charge pump circuit according to this embodiment. 4 is a timing chart for explaining the operation of the PLL frequency synthesizer according to the present embodiment.

The PLL frequency synthesizer according to this embodiment is provided with a voltage controlled oscillator (VCO) 18 whose oscillation frequency is changed by the applied voltage to obtain a desired frequency. The VCO 18 is connected to a frequency divider 20 that divides its output signal by a variable frequency division ratio. Frequency divider 20
The output signal of the VCO 18 divided by
Is used as a comparison signal fp for controlling the oscillation frequency of. The frequency divider 20 compares the reference signal fr from the reference oscillator 10 that generates a reference frequency with the phase of the comparison signal fp that is the output of the frequency divider 20.
It is connected to the. The phase comparator 12 compares the phases of the input reference signal fr and the comparison signal fp, and generates a predetermined output according to the phase difference between them. A charge pump circuit 14 is connected to the phase comparator 12 for sweeping out current, absorbing current, or taking a high impedance state according to the output of the phase comparator 12. The charge pump circuit 14 is connected with a loop filter (LF) 16 that integrates the output of the charge pump circuit 14 and outputs a voltage according to the phase difference. The output of the loop filter 16 is used as a control voltage for the VCO 18, and controls the oscillation frequency of the VCO so as to correct the phase difference.

Thus, the PLL frequency synthesizer for converging the output of the VCO to a desired frequency is constructed. In the above PLL frequency synthesizer, the charge pump circuit 14 is composed of the circuit shown in FIG. The charge pump circuit 14 has an input terminal 23a connected to the output terminal 22a of the phase comparator 12.
And an input terminal 23b connected to the output terminal 22b of the phase comparator 12.

The base of the PNP transistor Tr1 is connected to the input terminal 23a of the phase comparator 12 via the resistor R2. A resistor R1 is connected between the base and the power supply voltage Vcc. The emitter of the PNP transistor Tr1 is connected to the power supply voltage Vcc, and the collector is connected to the output terminal 24 of the charge pump circuit 14. A current mirror circuit 26 is connected to the input terminal 23b via a resistor R3, and a current equal to the current flowing from the input terminal 23b can be sucked from the output terminal 24 of the charge pump circuit 14. .

In this way, the charge pump circuit 14 is constructed in which the PNP transistor Tr1 outputs the sweep current and the current mirror circuit 26 outputs the sink current. As a specific example of the circuit of FIG. 1B, for example, the charge pump circuit shown in FIG. 2A can be applied.

The output terminal 22b of the phase comparator 12 is connected to the base and collector of an NPN transistor Tr2 via a resistor R3, and the emitter is grounded. NP
The base of the N-transistor Tr2 is connected to the base of the NPN transistor Tr3. The collector of the NPN transistor Tr3 is connected to the output terminal 24 of the charge pump circuit 14, and the emitter is grounded. Thus, the current mirror circuit 26 including the two NPN transistors Tr2 and Tr3 is configured.

By thus configuring the circuit on the side of the sink current with the current mirror circuit 26, the fluctuation of the output current when the power supply voltage fluctuates is only the current resulting from the fluctuation of the voltage applied to the resistor R3. . The amount of change in the current on the input side when the signal input from the output terminal 22b of the phase comparator 12 changes is almost equal to the amount of change in the current due to the change in the voltage applied to the resistor R3. By using the current mirror circuit that can make the output currents almost equal, the fluctuation of the input current is directly reflected as the fluctuation of the output current. Therefore, the fluctuation of the input current is reflected in the output current without being amplified, and only the fluctuation of the voltage applied to the resistor R3 becomes the fluctuation of the output current.

Therefore, as compared with the conventional charge pump circuit in which the current amplification factor h _fe of the transistor influences the fluctuation of the current on the output side, the fluctuation of the output current due to the fluctuation of the power supply voltage can be greatly reduced. . Further, in the conventional charge pump circuit, if the transistor has a temperature characteristic, the output current fluctuates due to a change in the ambient temperature, but by using the current mirror circuit, the fluctuation of the output current due to the temperature fluctuation is also canceled. be able to.

As in the charge pump circuit shown in FIG. 2B, a resistor R4 is provided between the emitter of the NPN transistor Tr1 and the ground potential, and an NPN transistor Tr2 is provided.
A resistor R5 may be provided between the emitter and the ground potential. By thus providing the resistors R4 and R5, the sink current value can be adjusted to a desired value.

FIG. 3 is a graph showing the power supply voltage dependence of the sink current and the sweep current in the charge pump circuit shown in FIG. 2 (b). In the figure, ○ indicates the sweep current, and ● indicates the sink current. As shown in FIG. 3, in the charge pump circuit according to the present embodiment, as shown in FIG.
Compared with the case of the conventional charge pump circuit shown in 3,
The dependency of the sink current on the power supply voltage can be reduced. That is, even if the power supply voltage changes, the change in output current can be suppressed to a small level. This allows
It is possible to stabilize the characteristics of the PLL frequency synthesizer.

Next, the operation of the PLL frequency synthesizer according to this embodiment will be described with reference to FIG. In the figure,
(A) represents the reference signal fr input to the phase comparator 12, (b) represents the comparison signal fp which is the output of the frequency divider 20, and (c) and (d) represent the output from the phase comparator 12. Represents the output signal, (e) represents the output of the charge pump circuit 14,
(F) represents the output voltage of the LF 16.

The phase comparator 12 receives the reference signal fr output from the reference oscillator 10 and the comparison signal fp obtained by dividing the output signal fo of the VCO by a predetermined division ratio. The phase comparator 12 outputs a desired pulse according to the phase difference between these signals. The phase comparator 12 outputs a high level voltage from the output terminal 22a and a low level voltage from the output terminal 22b in a steady state. When the phase of the comparison signal fp is delayed with respect to the reference signal fr, a low-level voltage pulse having a width corresponding to the phase delay is output from the output terminal 22a (phase delay state in the figure),
If the phase of the comparison signal fp is advanced with respect to the reference signal fr, a high level voltage pulse having a width corresponding to the advance of the phase is output from the output terminal 22b (phase advanced state in the figure).

In the charge pump circuit 14 of the next stage, both the PNP transistor Tr1 and the NPN transistor Tr2 are off in the above steady state, and the output of the charge pump circuit 14 is in a high impedance state. That is, no current is output from the output terminal 24. In this state, when a low-level pulse is input from the input terminal 23a of the charge pump circuit 14 connected to the output terminal 22a of the phase comparator 12, the PNP transistor Tr1 is activated and the power supply voltage Vcc goes to the output terminal 24. And a sweep-out current pulse is output (phase delay state in the figure).

On the other hand, when a high level pulse is output from the input terminal 23b of the charge pump circuit 14 connected to the output terminal 22b of the phase comparator 12, the NPN transistor Tr2 is activated and the resistor R3 receives (Vcc-
Only V _BE ) / R3 flows. V _BE is the base-emitter voltage of the NPN transistor Tr2. At the same time, a substantially equal collector current flows through the other NPN transistor Tr3 forming the current mirror, and the current is absorbed from the output terminal 24 toward the ground potential.
As the output of the charge pump circuit 14, a suction current pulse is output (phase leading state in the figure).

In the state where the phases match each other, both output terminals 22a of the phase comparator 12 are provided because of the characteristics of the logic circuit constituting the phase comparator 12 or in order to eliminate the dead zone of the phase comparator 12. , 22b output a voltage pulse having a very short pulse width. Output terminal 22 of phase comparator 12
When this short pulse is input from the input terminals 23a and 23b of the charge pump circuit connected to a and 22b, P
Both the NP transistor Tr1 and the current mirror circuit 26 are in the operating state, and a current flows from the power supply voltage Vcc toward the ground potential. At this time, the PNP transistor Tr
No current pulse is output from the charge pump circuit 14 by setting the currents flowing through 1 and the NPN transistor Tr3 to be equal and making the switching timings equal (phase matching state in the figure).

In the LF16 at the next stage, the output signal from the charge pump circuit 14 is smoothed and converted into a voltage, and this voltage output is transmitted to the VCO 18. For example, when a sweep current pulse is output from the output terminal 24, the LF16
The electric charge is accumulated in the capacitor forming the output voltage and the output voltage increases (phase delay state in the figure), and as a result, the frequency of the output signal fo of the VCO 18 increases. This causes the VCO 18 to operate so as to compensate for the phase delay.

On the other hand, when the sink current pulse is output from the output terminal 24, the electric charge is released from the capacitor forming the LF 16 and the output voltage decreases (phase lead state in the figure), and as a result, the output of the VCO 18 is output. The frequency of the signal fo decreases. As a result, the VCO 18 operates so as to compensate the phase lead. Reference signal fr and comparison signal fp
, The charge pump circuit 1
A high level signal is input to the fourth input terminal 23a, a low level signal is input to the input terminal 23b, and the output of the charge pump circuit 14 is in a high impedance state. That is, neither the sink current nor the sweep current is output from the output terminal 24. Thus, the output voltage of the LF 16 is maintained at the previous value and the frequency of the VCO 18 does not change (phase matching state in the figure).

The output signal fo of the VCO 18 is the VCO 18
Frequency divider 20 provided between the output of the
As a result, the frequency is reduced to 1 / N and is fed back as the comparison signal fp of the phase comparator 12. By configuring the PLL frequency synthesizer in this way, the operation stability of the charge pump circuit with respect to fluctuations in the power supply voltage and temperature can be improved, so that a stable frequency switching time and a stable VCO output can be obtained. it can.

In the conventional charge pump circuit shown in FIG. 11, assuming that the current flowing through the bias resistor R04 is sufficiently small, the current consumed when the sink current flows is only the collector current flowing through the NPN transistor Tr02. On the other hand, in the charge pump circuit according to the present embodiment, the current mirror circuit 2 is provided on the sink current side.
Since it is configured by 6, the collector current flows through the two transistors Tr2 and Tr3 when the sink current flows.

Therefore, using the charge pump circuit 26 according to this embodiment may increase power consumption by a factor of about two. However, the charge pump circuit 1
When 4 is used for the PLL frequency synthesizer, the increase in the current consumption by the charge pump circuit does not pose a problem since it operates only when switching the oscillation frequency or for a short time between the phase matching states.

Therefore, the charge pump circuit according to the present embodiment, which can obtain the stability of the operation against the fluctuation of the power supply voltage and the like, is particularly useful when used in the PLL frequency synthesizer. As described above, according to the present embodiment, since the sink current side of the charge pump circuit is configured by the current mirror circuit 26, the fluctuation of the output current due to the fluctuation of the power supply voltage or the temperature can be significantly suppressed.

By constructing a PLL frequency synthesizer using this charge pump circuit 14, a stable frequency switching time and a stable VCO output can be obtained. In the above embodiment, the NPN
An example in which the charge pump circuit 14 is configured by the current mirror circuit 26 configured by the transistors Tr2 and Tr3 has been shown, but the circuit is not limited to the circuit shown in FIG. For example, the above effect can be obtained also by configuring the charge pump circuit by the circuits shown in FIGS.

In the charge pump circuit shown in FIG. 5A, the base is connected to the collector of the NPN transistor Tr2, the emitters are connected to the bases of the NPN transistors Tr2 and Tr3, and the collector is connected to the power supply voltage Vcc. Tr4 is newly provided.
This circuit is a so-called base current compensation type current mirror circuit.
By adding 4, the NPN transistor Tr2,
The base current of Tr3 can be corrected.

The charge pump circuit shown in FIG.
The charge pump circuit shown in FIG. 2B is provided with an NPN transistor Tr4 for compensating the base current. By doing so, the output current can be adjusted to a desired value while compensating for the base currents of Tr2 and Tr3. In the charge pump circuit shown in FIG. 6A, a plurality of output transistors are provided for one input transistor of the current mirror circuit. That is, a plurality of NPN transistors Trn connected in parallel with the NPN transistor Tr3 are provided. By thus providing a plurality of NPN transistors for output, the sink current can be increased.

The charge pump circuit shown in FIG.
In the charge pump circuit shown in FIG. 6A, transistors Tr2, Tr3, ... T forming a current mirror circuit.
Resistors R4 and R5 are provided between the emitter of rn and the ground potential. By doing so, the output current of the charge pump circuit can be adjusted to a desired value. The charge pump circuit shown in FIG. 7A is an NPN for compensating the base current in the charge pump circuit of FIG.
The transistor Tr4 is added. By doing so, the sink current can be increased while correcting the base currents of Tr2, Tr3, ... Trn.

The charge pump circuit shown in FIG. 7B is
An NPN transistor Tr4 for compensating the base current is added to the charge pump circuit of FIG. 6 (b). By doing so, the sink current can be adjusted to a desired value while correcting the base currents of Tr2, Tr3, ... Trn. Next, the charge pump circuit according to the second embodiment of the present invention will be explained with reference to FIG.
The same components as those of the charge pump circuit according to the first embodiment are designated by the same reference numerals to omit or simplify the description.

FIG. 9 shows the charge pump circuit according to this embodiment.
It is a circuit diagram which shows a path. In the first embodiment, the char
Current mirror circuit on the suction current side of the dipump circuit
By configuring with a circuit, output due to fluctuations in power supply voltage, etc.
The fluctuation of the force current pulse was suppressed. Thus sink current
The current mirror circuit is used only on the side
The PNP transistor Tr1 forming the circuit on the current side is
Generally, DC current gain h _feIs small, so NPN transition
Compared with the circuit on the suction current side composed of
Is the fluctuation of output current due to fluctuations of power supply voltage or temperature small?
(See FIG. 13).

Therefore, when the DC current amplification factor h _{fe of} the PNP transistor forming the circuit is large, the output current pulse on the sweep current side fluctuates, and P
This also causes deterioration of the characteristics of the LL synthesizer.
The present embodiment provides a charge pump circuit that can obtain a stable output current pulse even on the sweep current side.

The charge pump circuit according to the present embodiment is
It is characterized in that both the suction current side and the sweep current side are configured by a current mirror circuit. That is, the current mirror circuit 30 is connected to the input terminal 23a connected to the output terminal 22b of the phase comparator 12 via the resistor R1, and a current equal to the current swept out from the input terminal 22a is supplied to the charge pump. It can be swept out from the output terminal 24 of the circuit 14.

A current mirror circuit 26 is connected to the input terminal 23b connected to the output terminal 22b of the phase comparator 12 via the resistor R3, and the output terminal 22b is connected to the output terminal 22b.
A current equal to the current flowing in from can be sucked from the output terminal 24 of the charge pump circuit 14. Thus, the charge pump circuit 14 that outputs the sweep current by the current mirror circuit 30 and outputs the sink current by the current mirror circuit 26 is configured.

In this way, the circuit on the sweep current side is covered.
By using the rent mirror circuit 30, the power supply voltage
The fluctuation of the output current due to the fluctuation of
There is only current due to pressure fluctuations. Therefore, the first implementation
Similar to the one shown in the form, transistor current amplification
Rate h _feIs a traditional channel that affects the fluctuation of the output current.
Output due to fluctuations in power supply voltage
It is possible to significantly reduce fluctuations in current.

Also, the fluctuation of the output current due to the temperature fluctuation is
It can be canceled by using a current mirror circuit. Note that as a specific example of the circuit illustrated in FIG. 8A, the charge pump circuit illustrated in FIG. 8B can be applied, for example. The input terminal 23a has a resistor R1
The base and collector of the NPN transistor Tr5 are connected to each other via the, and the emitter is connected to the power supply voltage Vcc. The base of the NPN transistor Tr6 is connected to the base of the NPN transistor Tr5. The collector of the NPN transistor Tr6 is the charge pump circuit 14
Of the power supply voltage Vcc.
It is connected to the. Thus, the current mirror circuit 30 including the two NPN transistors Tr5 and Tr6 is configured.

The base and collector of the NPN transistor Tr2 are connected to the input terminal 23b via the resistor R3, and the emitter is connected to the ground potential. NP
The base of the N-transistor Tr2 is connected to the base of the NPN transistor Tr3. The collector of the NPN transistor Tr3 is connected to the output terminal 24 of the charge pump circuit 14, and the emitter is connected to the ground potential. Thus, the two NPN transistors Tr2, Tr
A current mirror circuit 26 of 3 is configured.

As described above, according to this embodiment, the current mirror circuit 2 is connected to the sink current side of the charge pump circuit.
6 and the sweep current side is constituted by the current mirror circuit 30, it is possible to greatly suppress the fluctuation of the output current due to the fluctuation of the power supply voltage or the temperature in any operating state. In addition, the charge pump circuit 14
By configuring a PLL frequency synthesizer using, it is possible to obtain a stable frequency switching time and VCO output.

The charge pump circuit shown in FIG. 8B has the simplest circuit configuration.
A circuit having the structure shown in FIG. 9 or 10 can also be applied. In the charge pump circuit shown in FIG. 9A, a resistor R6 is provided between the PNP transistor Tr5 forming the current mirror circuit and the power supply voltage, and a resistor R7 is provided between the PNP transistor Tr6 and the power supply voltage. By thus inserting the resistors R6 and R7, the output current on the sweep current side can be adjusted to a desired value.

The charge pump circuit shown in FIG. 9B is
A plurality of output transistors are provided for one input transistor of the current mirror circuit. That is, a plurality of NPN transistors Trm connected in parallel to the PNP transistor Tr6 are provided. By providing a plurality of PNP transistors for output in this way, the sweep current can be increased.

In the charge pump circuit shown in FIG. 10A, the PNP transistor Tr is added to the circuit shown in FIG. 9A.
A base is connected to the collector of P5, a emitter is connected to the bases of PNP transistors Tr5 and Tr6, and a PNP transistor Tr7 whose collector is connected to the ground potential is newly provided. Thus, PN for base current compensation
By adding the P transistor Tr7, the base currents of the NPN transistors Tr5 and Tr6 can be corrected.

In the charge pump circuit shown in FIG. 10B, in the circuit shown in FIG. 10A, the current mirror circuit is provided with a plurality of output transistors. By providing a plurality of PNP transistors for output in this way, the sweep current can be increased. The present invention is not limited to the above embodiment, and various modifications are possible.

The above embodiment shows an example of a circuit that can realize the present invention with a simpler configuration, and the present invention is not limited to the above embodiment. Also, the first
Alternatively, the PLL frequency synthesizer according to the second embodiment is
It can be applied to mobile phones, cordless phones, GPS of navigation systems, wireless communication devices, and the like.

[0062]

As described above, according to the present invention, the sweep-out current generating means for generating the sweep-out current in response to the first input signal and the suction current generation for generating the sink current in response to the second input signal. A charge pump circuit for performing a push-pull operation, comprising: a first current generating means for flowing a current based on a second input signal; and a first current generating means paired with the first current generating means. And a current mirror circuit having a second current generating means that outputs a sink current that is substantially equal to the current based on the second input current. Therefore, the output current on the sink current side due to fluctuations in the power supply voltage and temperature is reduced. Fluctuations can be greatly suppressed.

In the above charge pump circuit, the sweep-out current generating means is paired with the first current generating means for flowing a current based on the first input signal, and the first current generating means is paired with the first current generating means. If a current mirror circuit having a second current generating means that outputs a sweep current that is substantially equal to the current based on the input current is used, fluctuations in the output current on the sweep current side due to fluctuations in the power supply voltage and temperature can be greatly suppressed. be able to.

Further, in the above charge pump circuit, the sink current generating means or the sweep current generating means and the transistor forming the first current generating means and the second current generating means are provided.
If a base current compensating means for compensating the base current of the transistor forming the current generating means is further provided, the base current of the transistor forming the current mirror circuit can be corrected.

Further, in the above charge pump circuit, if the second current generating means constituting the sink current generating means or the sweep current generating means is constituted by a plurality of transistors connected in parallel, the output current is desired. The value can be adjusted. In the above charge pump circuit, the output current is controlled by being connected to the first current generating means forming the sink current generating means or the sweep current generating means and being connected to the emitter of the transistor forming the first current generating means. A second resistor that is provided with a first resistor and is connected to a second current generating unit that constitutes a sink current generating unit or a sweep current generating unit and is connected to an emitter of a transistor that constitutes a second current generating unit to control an output current.
If the resistance of 1 is provided, the output current can be adjusted to a desired value. In addition, the voltage controlled oscillator whose oscillation frequency is controlled by the applied voltage, the frequency divider that divides the output oscillation signal of the voltage controlled oscillator, the reference oscillation signal that is output from the reference oscillator, and the frequency divider that divides the frequency. A phase comparator that compares the phase difference with the output oscillation signal of the voltage controlled oscillator and generates an output pulse according to the phase difference, and the above-mentioned charge that generates a predetermined current output based on the output pulse of the phase comparator By constructing a PLL frequency synthesizer with a pump circuit and a loop filter that outputs a voltage signal according to the output of the charge pump circuit to a voltage controlled oscillator, the stability of operation of the charge pump circuit against fluctuations in power supply voltage and temperature is improved. Therefore, it is possible to obtain a PLL frequency synthesizer having a stable frequency switching time and a stable VCO output. Kill.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a PLL frequency synthesizer according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a charge pump circuit according to a first embodiment of the present invention.

FIG. 3 is a graph showing the power supply voltage dependence of the sink current and the sweep current in the charge pump circuit according to the first embodiment of the present invention.

FIG. 4 is a timing diagram illustrating the operation of the PLL frequency synthesizer according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram (No. 1) showing a charge pump circuit according to a modification of the first embodiment of the present invention.

FIG. 6 is a circuit diagram (No. 2) showing the charge pump circuit according to the modification of the first embodiment of the present invention.

FIG. 7 is a circuit diagram (No. 3) showing the charge pump circuit according to the modification of the first embodiment of the present invention.

FIG. 8 is a circuit diagram showing a charge pump circuit according to a second embodiment of the present invention.

FIG. 9 is a circuit diagram (part 1) showing a charge pump circuit according to a modification of the second embodiment of the present invention.

FIG. 10 is a circuit diagram (No. 2) showing the charge pump circuit according to the modification of the second embodiment of the present invention.

FIG. 11 is a circuit diagram showing a conventional charge pump circuit.

FIG. 12 is a circuit diagram showing an example of a loop filter.

FIG. 13 is a graph showing the power supply voltage dependence of the sink current and the sweep current in the conventional charge pump circuit.

[Explanation of symbols]

 10 ... Reference oscillator 12 ... Phase comparator 14 ... Charge pump circuit 16 ... LF 18 ... VCO 20 ... Divider 22 ... Output terminal 23 ... Input terminal 24 ... Output terminal 26 ... Current mirror circuit 30 ... Current mirror circuit

Claims (6)

[Claims] 1. A push-pull operation comprising: a sweep current generating means for generating a sweep current according to a first input signal; and a sink current generating means for generating a sink current according to a second input signal. In the charge pump circuit, the sink current generating means forms a pair with the first current generating means for flowing a current based on the second input signal, and the second current generating means, A charge pump circuit comprising: a current mirror circuit having a second current generating unit that outputs the sink current that is substantially equal to the current based on the input current. 2. The charge pump circuit according to claim 1, wherein the sweep-out current generating means has a pair of first current generating means for flowing a current based on the first input signal, and the first current generating means. And a current mirror circuit having a second current generating unit that outputs the sweep-out current that is substantially equal to the current based on the first input current. 3. The charge pump circuit according to claim 1, wherein the sink current generating unit or the sweep current generating unit includes a transistor forming the first current generating unit and the second current generating unit. A charge pump circuit further comprising a base current compensating means for compensating for a base current of a constituent transistor. 4. The charge pump circuit according to claim 1, wherein the second current generating means forming the sink current generating means or the sweep current generating means is connected in parallel. A charge pump circuit including the transistor of. 5. The charge pump circuit according to claim 1, wherein the first current generating means forming the sink current generating means or the sweep current generating means includes the first current generating means. The second current generating means, which is connected to the emitter of the transistor forming the means, has a first resistor for controlling the output current, and constitutes the sink current generating means or the sweep current generating means, And a second resistor connected to the emitter of the transistor constituting the current generating means for controlling the output current. 6. A voltage-controlled oscillator whose oscillation frequency is controlled by an applied voltage, a frequency divider that divides an output oscillation signal of the voltage-controlled oscillator, a reference oscillation signal output from a reference oscillator, and the frequency divider. A phase comparator that compares the phase difference with the output oscillation signal of the voltage controlled oscillator divided by a frequency divider, and a phase comparator that generates an output pulse according to the phase difference, and a predetermined value based on the output pulse of the phase comparator. The charge pump circuit according to claim 1, which generates a current output, and a loop filter which outputs a voltage signal according to the output of the charge pump circuit to the voltage controlled oscillator. PLL frequency synthesizer.