JPH09331027A - Semiconductor device and its fabrication - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a fabrication method in which the reliability of anti-fuse layer is enhanced before and after writing by suppressing fluctuation in the writing voltage of anti-fuse. SOLUTION: An anti-fuse layer is formed by sputtering to have a thin part. The anti-fuse layer is separated into an end anti-fuse layer 3081 on the bottom of a contact hole 307 and a central anti-fuse layer 3082. The end anti-fuse layer 3081 is thinner than the central anti-fuse layer 3082 and it is extremely thin at the part abutting on the side wall of the anti-fuse layer. In such an anti-fuse layer, when a voltage is applied between second and third wiring layers 305, 309 to be formed latter for the purpose of writing, the field strength is concentrated at the thin part, i.e., the end anti-fuse layer 3081 where silicification takes place to decrease the resistance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an antifuse structure and a method of manufacturing the same.

[0002]

Antifuses are important structures used in non-volatile semiconductor memory devices. The structure is such that an insulating film capable of reacting with the wiring material is sandwiched between two wiring layers such as metal, and the principle is to apply a predetermined voltage between the two wiring layers of a certain bit so that one Is to lower the resistance by reacting the part with the wiring material, and the importance of its function is to use the difference in resistance between the high resistance bit and the low resistance bit because it remains an insulating film. Can be used as a storage device. FIG. 2 is a cross-sectional view of a conventional semiconductor device including an anti-fuse structure formed between two wiring layers. Hereinafter, the structure of a semiconductor device including an anti-fuse structure according to the related art will be described with reference to FIG.
Reference numeral 200 is a non-insulating substrate such as a silicon substrate. 202
Is a first insulating layer. Reference numeral 203 denotes a first wiring layer,
Reference numeral 4 is a second insulating layer. Reference numeral 205 denotes a second wiring layer which serves as a lower electrode of the antifuse, and after forming the third insulating layer 206, the connection hole 207 is formed by a combination of a wet etching method, a dry etching method, or the like. Reference numeral 208 denotes an antifuse layer, which is composed of a high resistance a-Si layer or the like. The antifuse layer 208 has a structure sandwiched between the second wiring layer 205 and the third wiring layer 209 which is an upper electrode. By applying a voltage between the second wiring layer 205 and the third wiring layer 209 of a certain bit whose low resistance state is to be stored,
A part of the antifuse layer 208 reacts with the wiring layer to reduce the resistance. This reaction is mainly irreversible, and once the resistance of part of the antifuse layer 208 is once lowered, the resistance of the other parts of the antifuse layer 208 is not lowered, and subsequent conduction is the part where the resistance is lowered. Happens only through. Hereinafter, the bit whose resistance has been reduced in this way is referred to as a written bit, and the resistance reduction of a certain bit is expressed as writing, and when writing, the bit between the second wiring layer 205 and the third wiring layer 209 is written. The voltage applied to is called the write voltage.

[0003]

In the conventional semiconductor device including the antifuse structure, the bottom area of the connection hole 207 has a certain spread (for example, a circle having a diameter of 0.8 μm). Due to the structure of a transistor or the like formed between the first insulating layer 202 and the non-insulating substrate 200, or the first wiring layer 203, the base of the antifuse formation region has random steps, and writing is performed. Since the states of electric field concentration are subtly different for each bit to be tried, there is a problem in that variations in write voltage and variations in post-write resistance are caused. Writing to a certain bit using a-Si as the antifuse layer is the heat generated by applying a voltage to the wiring layer made of, for example, a metal while sandwiching the high resistance a-Si and the wiring between the a-Si and the wiring. This is to cause a silicidation reaction with the metal forming the layer to reduce the resistance. This writing is performed by an electric field strength above a certain level due to an applied voltage above a certain level, and generally occurs in a very small area only at the bottom edge portion of the contact hole. For example, comparing an antifuse formed on a flat surface with an antifuse formed on a slope due to a step difference in level, the difference between the angle formed between the wall surface of the connection hole and the wiring layer at the bottom of the connection hole causes The effective electric field strength applied to the antifuse layer a-Si formed on the upper side changes, and the voltage required for writing differs. However, since the write voltage applied from the outside is simple, it is set to a constant value by using a pattern with a high write voltage as a reference. After resistance becomes lower than other bits. In this way, variations in effective write voltage and post-writing resistance occur. Further, due to the variation in the voltage required for writing, in a bit for which the voltage required for writing is low, the effective electric field strength applied to the antifuse layer a-Si is high even before writing, so that the stress due to the electric field increases, and Even the reliability in the insulated state deteriorates.

There is a known example that attempts to solve this variation in the write voltage by selecting the base. For example, in Japanese Unexamined Patent Publication No. 05-129439, the position of the opening of the first insulating film and the position of the second opening must be changed in a plane so that the base of the antifuse layer is flat, and thus the voltage required for writing is constant. ing. With this, there is no degree of freedom with respect to the underlying layer, and there are large design restrictions, so that a semiconductor device compatible with high integration cannot be produced.

In another known example, the problem of the variation of the write voltage is solved by limiting the area related to the writing in a certain bit. For example, Japanese Unexamined Patent Publication No. 05-121557 is to limit a place where a reaction with an antifuse layer occurs by cutting off a part of an upper electrode or a lower electrode. This is a photo
This is not realistic because it increases the number of etching steps and cannot concentrate electric field concentration at the cut metal edge of the wiring.

The present invention is intended to solve the problems caused by these variations in the write voltage. The object of the present invention is to reduce the variations in the write voltage by a simple method, and in the insulating state before the writing of the a-Si film. Another object of the present invention is to provide a semiconductor device having improved reliability.

[0007]

In order to solve the above-mentioned problems, the semiconductor device of the present invention is characterized as follows.

A semiconductor device including at least one or more antifuse structures is characterized in that the antifuse forming region includes a structure for specifying a data write portion of the antifuse.

The structure for specifying the data write portion of the antifuse is characterized in that the electric field strength of the write voltage is concentrated.

The structure for concentrating the electric field strength of the write voltage is such that the film thickness of the data writing portion of the antifuse is thinner than the film thickness of the antifuse forming region other than the data writing portion. Is characterized by.

In order to solve the above problems, the method of manufacturing a semiconductor device of the present invention is characterized by the following.

A method of manufacturing a semiconductor device including at least one or more antifuse structures includes the step of forming a structure for specifying a data writing portion of the antifuse in the antifuse forming region.

The step of forming the structure for specifying the data write portion of the antifuse is a step of forming a structure for concentrating the electric field strength of the write voltage.

In the step of forming the structure for concentrating the electric field strength of the write voltage, the film thickness of the data writing part of the antifuse is made thinner than the film thickness of the antifuse forming region other than the data writing part. It is characterized in that it is a process of creating.

The step of forming the film thickness of the data writing portion of the antifuse to be thinner than the film thickness of the antifuse forming region other than the data writing portion is an antifuse forming step using a sputtering method. Is characterized by.

[0016]

1 is a sectional view of a semiconductor device including an antifuse structure formed between two wiring layers according to an embodiment of the present invention. Further, FIG. 3 is a sectional view of a main portion of a semiconductor device including an antifuse structure formed between two wiring layers according to the embodiment of the present invention. A structure of a semiconductor device including an antifuse structure according to an embodiment of the present invention will be described below with reference to FIG. 1, and a main part will be described with reference to FIG. Reference numeral 100 is a non-insulating substrate such as a silicon substrate. Reference numeral 101 denotes an element isolation structure or a conceptual structure of a portion such as a transistor that serves as a step difference in the base of the antifuse. 102 is a first insulating layer. A first wiring layer 103 is made of a material such as polycrystalline silicon. The first wiring layer 103 may have a single-layer structure of polycrystalline silicon or a two-layer structure of polycrystalline silicon and a metal or a metal silicide to reduce resistance. 104 is a second insulating layer. A second wiring layer 105 serves as a lower electrode of the antifuse. In the embodiment of the present invention, a TiN layer is formed on the Al—Cu layer by a sputtering method. 106 is the third
Insulating layer, Si by CVD (Chemical Vapor Deposition) method
O2 was used. Reference numeral 107 denotes a connection hole for connecting the second wiring layer 105 and the third wiring layer 109, and in the embodiment of the present invention, it is formed by using a dry etching method.
The method of forming the connection hole 107 is not limited to this, and for example, a wet etching method using a hydrofluoric acid aqueous solution, a dry etching method using CF4 gas, or a combination of the wet etching method and the dry etching method may be used. . Although the post-etching shape according to the embodiment of the present invention is a vertical shape, the post-etching shape may be any shape such as a vertical shape, a tapered shape, or a shape having a chamfer on the upper portion of the connection hole. Third insulating layer 106
If the upper portion of the connection hole 107 is chamfered by a wet etching method or another etching method, there is an effect that the coverage right above the chamfered portion of the third wiring layer 109 is improved. Reference numeral 108 denotes an antifuse layer, which has a high resistance aS formed by a sputtering method.
It consists of i layers. This is the most important part of the embodiment of the present invention. As seen in FIG. 3, the antifuse layer, depicted as 108 in FIG. 1, is divided into an end antifuse layer 3081 at the bottom of the contact hole 307 and a central antifuse layer 3082. The end antifuse layer 3081 has a smaller film thickness than the central antifuse layer 3082, and is extremely thin particularly in the portion in contact with the side wall of the antifuse layer. In the embodiment of the present invention, this film thickness is the central antifuse layer 3
It was as thin as 65% of the film thickness of 082. In the embodiment of the present invention, this ratio is not limited. Since the sputtering method is used to form the high resistance a-Si layer, it is important that the film thickness of the antifuse layer at the end is smaller than the film thickness of the antifuse layer at the center. In the antifuse layer thus obtained, the third fuse formed later
When a voltage is applied between the wiring layer 309 and the second wiring layer 305 to perform writing, the electric field strength is concentrated on a thin portion, that is, the end antifuse layer 3081 centering on the bottom edge, In this portion, silicidation occurs and the resistance is reduced. Since it is a sectional view in FIG.
Although 81 is drawn as if there were two places, it actually forms the circumference (circumference) of the bottom of the connection hole 307. Therefore, in practice, a part of the circumference of 3081 is silicified by applying a voltage. The area spread of the portion where the silicidation occurs is limited to the circumferential direction, that is, the spread to the end antifuse layer 3081 having a relatively same film thickness, and the area is dramatically smaller than the conventional one. became. Further, since the spreading direction is limited, the variation in the area is also reduced, so that the variation in the write voltage between bits and the variation in the resistance after writing are also reduced. Returning to FIG. 1, the description will be continued. When the ion species such as Ar is implanted after the formation of the antifuse layer 108, the resistance of the antifuse layer is increased, and the reliability in the insulating state before writing is improved. The antifuse layer 108 has a structure sandwiched between the second wiring layer 105 and the third wiring layer 109 as described in the same configuration in FIG. 1
The third wiring layer 09 is formed by the sputtering method in the embodiment of the present invention. Further, the detailed structure was such that the lower layer was a barrier layer and the upper layer was a conductor layer. So far, the structure of the semiconductor device according to the embodiment of the present invention has been described, but the materials, forming methods, and the like described therein are not limited thereto. For example, antifuse layer 1
08 may be formed by a long distance sputtering method. By using this method, a thicker portion and a thinner portion can be formed in the end antifuse layer 3081, which is remarkable especially in the chip at the edge of the wafer. The electric field at the time of writing tends to concentrate in the thin portion, and therefore, the thin portion of the antifuse layer 3081 selectively becomes the data writing portion.

Further, as the design rule of the nonvolatile semiconductor memory device using the antifuse becomes finer, it is expected that the connection hole 107 in which the antifuse layer 108 is formed becomes smaller. The antifuse layer 10 at the upper edge of the contact hole 107
It is desirable that the coverage of No. 8 be improved, but the coverage at the bottom of the connection hole 107 is preferably small. Normally, stable coverage can be obtained by improving coverage, but coverage is worse at the bottom, and if a thin portion is formed in the antifuse layer 108, the electric field concentrated at that portion becomes stronger, and data writing is performed. The effect of identifying the part is enhanced. By using the long-distance sputtering method among the sputtering methods, it is possible to obtain the effect of specifying the data writing portion. As a method of forming a thin portion in the antifuse layer 108, another method such as a patterning method is also suitable. In the embodiment of the present invention, the data writing portion of the antifuse can be specified by devising the film forming method in the antifuse layer.

[0018]

According to the semiconductor device of the present invention, the variation of the write voltage can be reduced by specifying the data write portion of the antifuse by a simple method. Also,
In the present invention, another effect was obtained as a secondary effect. In the antifuse, there was a leak current before writing, but the reduction of the leak current could be achieved because the area of the data writing portion became smaller. for that reason,
The reliability of the antifuse layer before writing is improved. In addition, it is not necessary to select an etching method at the time of forming the connection hole, and the existing sputtering method can be used, and it is possible to suppress variations in the write voltage between the antifuse bits and the resistance after writing. The characteristics and reliability before writing and the characteristics and reliability after writing did not vary, and it was possible to greatly contribute to the provision of a good nonvolatile semiconductor memory device.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a conventional semiconductor device.

FIG. 3 is a sectional view showing a main part of the structure of the semiconductor device according to the embodiment of the present invention.

[Explanation of symbols]

 100, 200 ... Non-insulating substrate 101 ... Conceptual structure of underlying step 102, 202 ... First insulating layer 103, 203 ... First wiring layer 104, 204 ... Second insulating layer 105, 205, 305 ... Second wiring layer 106, 206, 306 ... Third insulating layer 107, 207, 307 ... Connection hole 108, 208, 308 ... Antifuse layer 109, 209, 309・ ・ ・ Third wiring layer 3081 ・ ・ ・ End antifuse layer 3082 ・ ・ ・ Center antifuse layer

Claims (7)

[Claims] 1. A semiconductor device including at least one or more antifuse structures, wherein the antifuse formation region includes a structure for specifying a data write portion of the antifuse. 2. The semiconductor device according to claim 1, wherein the structure for specifying the data write portion of the antifuse is a structure for concentrating the electric field strength of the write voltage. 3. The structure for concentrating the electric field strength of the write voltage has a structure in which a film thickness of a data writing portion of the antifuse is thinner than a film thickness of the antifuse forming region other than the data writing portion. The semiconductor device according to claim 1, wherein the semiconductor device is present. 4. A method of manufacturing a semiconductor device including at least one or more antifuse structures, including a step of forming a structure for specifying a data writing portion of the antifuse in the antifuse forming region. Of manufacturing a semiconductor device. 5. The semiconductor according to claim 4, wherein the step of forming the structure for specifying the data write portion of the antifuse is a step of forming a structure for concentrating the electric field strength of the write voltage. Device manufacturing method. 6. The step of forming a structure for concentrating the electric field strength of the write voltage is such that the film thickness of the data writing portion of the antifuse is made smaller than the film thickness of the antifuse forming region other than the data writing portion. 6. The method for manufacturing a semiconductor device according to claim 4, wherein the step is a step of making it thin. 7. The step of forming the film thickness of the data writing portion of the antifuse smaller than the film thickness of the antifuse forming region other than the data writing portion is an antifuse forming step using a sputtering method. The method for manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is provided.