JPH09322578A - Speed control signal generation circuit of motor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control motor rotary speed accurately based on a low-frequency signal accompanying motor rotation. SOLUTION: The output of Hall elements 22a-22c is converted into a rectangular wave by Hall comparators 30a-30c and is inputted to speed discrete circuits 32a-32c. The speed discrete circuits 32a-32c compare the period of input waveform with a set time separately and output acceleration pulses and deceleration pulses for the difference. Then, these acceleration pulses and deceleration pulses are added by a synthesis circuit 34 and are integrated by an output control part, and an output drive circuit 28 controls motor drive current according to the integral value, thus controlling rotary speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor speed control signal generation circuit for detecting rotation of a motor by a detection element and generating a speed control signal based on the detected speed detection signal.

[0002]

2. Description of the Related Art Conventionally, various means have been adopted to control the rotation speed of a motor to a predetermined value. For example,
A speed control circuit that supplies DC power to a three-phase AC motor controls ON / OFF of six switching transistors to supply a desired three-phase AC current to the motor. Then, the amount of current supplied to the motor at the time of this switching is controlled to control the rotation speed of the motor to a desired value.

Here, in order to control the rotation speed, it is necessary to detect the rotation speed of the motor. The detection of the counter electromotive force associated with the rotation of the motor is used to detect the rotation speed of the motor. That is, the switching transistor is turned on / off to make the motor drive current into a switching waveform (rectangular wave), and the back electromotive force generated when the motor is rotated is detected. Then, the zero cross of the detected back electromotive force is detected to create an FG pulse, and the driving force of the motor is controlled by the obtained FG pulse.

No special sensor is required for the detection of the FG pulse due to the counter electromotive force, and therefore, there is no problem based on the mounting position of the sensor. Further, the frequency of the detected FG pulse corresponds to the switching frequency, and therefore has a higher frequency than the detection signal of the hall element detecting the normal motor rotation phase. Therefore, this FG
Suitable motor rotation speed control can be performed using the pulse.

Here, the speed discriminating circuit compares the cycle of the input FG pulse with the set time and generates an acceleration command or a deceleration pulse according to the difference from the set time.
Therefore, the motor rotation speed can be controlled to a desired rotation speed by controlling the magnitude of the motor drive current according to the acceleration pulse or the deceleration pulse.

An example of the structure of such a speed discriminating circuit is shown in FIG. The FG pulse generated according to the number of rotations of the motor is a 1/2 frequency divider 1 which outputs a signal ½ FG signal and an inverted ½ FG signal (in the figure, an upper half FG signal and an inverted ½ FG signal) whose phases are opposite to each other. Bar indicates inversion). The obtained 1 / 2FG signal and inverted 1 / 2FG signal are input to the trigger pulse generation circuit 2.

The trigger pulse generation circuit 2 generates trigger pulses T1 and T2 from the 1 / 2FG signal and the inverted 1 / 2FG signal, and the inverted CK0 obtained by inverting the reference clock CK0 supplied through the inverter 14. That is, the trigger pulse generation circuit 2 outputs the trigger pulse T1 which becomes “0” only for one clock of the inverted CK0 when the 1 / 2FG signal rises, and only for the one clock of the inverted CK0 when the inverted 1 / 2FG signal rises. The trigger pulse T2 which becomes "0" is output.

The trigger pulse T1 is applied to the flip-flop 3
Is input to The flip-flop 3 is composed of two NAND gates 4 and 5, and a trigger pulse T1 is applied to one input of the NAND gate 4. The inverted Q1 which is the inverted output of the flip-flop 3 which is the output of the NAND gate 5 is input to the first counter 6. The reference clock CK0 is also supplied to the first counter, which is reset at the falling edge of the inversion Q1 of the flip-flop 3 to start counting the clock CK0. When the count value reaches a predetermined value, one clock is fed. Then, the count-up signal R1 which becomes "0" is output. And this signal R1
Is input to one input terminal of the NAND gate 5 of the flip-flop 3.

Therefore, the fall of the 1 / 2FG signal causes the trigger pulse T1 to be "0", which sets the inversion Q1 of the flip-flop 3 to "0". Then, by the "0" of the inversion Q1, the first counter 6
Is reset and counts the clock CK0, and when it reaches a predetermined value, R1 becomes "0", and this is supplied to the NAND gate 5 of the flip-flop 3, and the inversion Q1 becomes "1". Ends.

The trigger pulse T2 is also supplied to the flip-flop 7. The flip-flop 7 is composed of NAND gates 8 and 9, and the inverted output Q 2 thereof is supplied to the second counter 10. The clock CK0 is supplied to the second counter 10, and the clock CK0 is counted up while the inversion Q2 is "0", and the count-up signal R is reached when it reaches a predetermined value.
“0” is output to 2. Therefore, the flip-flop 7 and the second counter 10 are
The same operation as the first counter 6 is performed. However, the first counter 6 starts counting in response to the rising edge of the 1 / 2FG signal, and the second counter 10 starts counting in response to the falling edge of the 1 / 2FG signal.

The Q1 output which is the output of the NAND gate 4 of the flip-flop 3 and the Q2 output which is the output of the NAND gate 8 of the flip-flop 7 are input to the gate circuit 11. The gate circuit 11 is composed of two AND gates 12 and 13. The output Q1 of the flip-flop 3 and the output Q2 of the flip-flop 7 are input to the AND gate 12, and the inverted Q1 of the flip-flop 3 and the inverted Q2 of the flip-flop 7 are input to the AND gate 12.

Therefore, as shown in FIG.
The trigger pulse T1 is "0" due to the fall of the G signal.
And, by this, the inversion Q1 instantly becomes "0",
When the first counter 6 starts counting and when it counts up, R1 instantly becomes "0", whereby the inversion Q1 returns to "1" and the counting of the first counter 6 ends. Set time until this count up (indicated by K)
Is shorter than one cycle of FG (indicated by A), inversion Q
2 remains "1". Therefore, AND gate 13
The period "1" from the end of counting to the fall of the next inverted 1 / 2FG signal is output as the slow signal S. This is because if the set time until the count-up shown by K in the figure is the time of the target one cycle, it means that the cycle of the detected FG is longer than this, and the rotation speed is slow.

Also, when the second counter 10 counts up within the FG cycle, the AND gate 1
A slow signal S (acceleration command) is output from 3. In this way, the slow signal S regarding the difference between the one period A of the FG pulse and the set time K is output from the AND gate 13 during the time when neither of the two counters 6 and 10 is performing the counting operation.

On the other hand, when the cycle A of the FG is shorter than the set time K, while one of the counters 6 and 10 is counting, the other counter starts the counting operation. Therefore, "1" is output from the AND gate 12 while both counters 6 and 10 are operating. Therefore, the output of the AND gate 12 is F
It is output as a fast signal F (deceleration command) regarding the difference between one cycle A of the G pulse and the set time K.

In this way, by using the two counters, the signal S concerning the difference between the rotation speed and the target speed,
F can be obtained, and the motor rotation speed can be controlled to the set value by controlling the motor drive current with this signal.

[0016]

However, in the above-mentioned conventional example, since the FG signal is obtained from the back electromotive force waveform of the motor, the motor drive current has a switching waveform capable of obtaining the back electromotive force. Then, when the motor drive current is switched to a switching waveform, kickback occurs in the output, so a snubber circuit for removing switching noise is required, and the high-frequency current does not adversely affect other circuits. It was necessary to take measures against the parasitic capacitance on the pattern.

It is also conceivable that kickback will affect the back electromotive waveform and FG pulses will be generated at erroneous timing. To solve this, in a comparator that detects the zero cross of the FG pulse, A mask circuit for removing the back is required.

Further, if the switching of the switching transistor is made to be soft switching and the motor drive current is made a sine curve, the above problem can be solved, but an appropriate counter electromotive force due to the rotation of the motor cannot be obtained and the counter electromotive force is not obtained. Since the zero cross of is deviated, an appropriate FG cannot be obtained and accurate rotation drive control of the motor cannot be performed.

On the other hand, if the rotation speed can be controlled on the basis of the low-frequency rotation phase signal, the output of the Hall element can be used, and the above-mentioned problems due to the generation of high-frequency noise can be solved. You can

The present invention has been made in view of the above problems, and an object of the present invention is to provide a motor speed control signal generation circuit capable of generating a motor rotation speed signal of sufficient accuracy even with a relatively low frequency signal. .

[0021]

SUMMARY OF THE INVENTION The present invention is a motor speed control generation circuit for generating a speed control signal based on a speed detection signal indicating a rotation speed of a motor. A plurality of individual speed control signal generating means for respectively generating individual speed control signals for controlling the rotation speed of the motor, and a plurality of individual speed control signals from the individual speed control signal generating means are combined to form a single And a synthesizing unit for obtaining a speed control signal.

First, a plurality of speed detection signals indicating the rotation speed of the motor are obtained from the outputs of a plurality of Hall elements. Then, the plurality of speed detection signals are compared with the set speed, and the speed control signal is obtained based on the difference. If the detected speed is slow, an acceleration command corresponding to this is obtained, and if the detected speed is faster, a deceleration command is obtained. Here, in the case of the output from the Hall element, the cycle of change of the output represents the rotation speed. Therefore, the cycle is counted, and the individual speed control signal can be obtained depending on whether the cycle is earlier or later than the set time.

Then, by combining the obtained plurality of speed control signals with, for example, an adder circuit, a signal obtained by combining the plurality of individual speed control signals can be obtained. Therefore, the speed control signal after combining has increased accuracy in accordance with the number of individual speed control signal generating means, and a signal of a relatively low frequency is used like the output of the Hall element. Also, the motor rotation speed can be controlled with sufficient accuracy.

Further, if the detection signal from the Hall element is used, it is not necessary to increase the counter electromotive force at the time of current switching when driving the motor, and soft switching can be performed to suppress the generation of high frequency noise. It's easy.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention (hereinafter referred to as embodiments) will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of this embodiment. The motor 20 includes three-phase coils 20a, 2
0b, 20c and these coils 20a, 20b, 2
A predetermined current is supplied to 0c to rotate a rotor (not shown). Then, the portion facing the rotor is 120
Three Hall elements 22a and 22 are provided at different positions.
b and 22c are provided to obtain a three-phase Hall waveform corresponding to the rotation phase of the rotor. That is, the current change of the hall elements 22a, 22b, 22c due to the rotation of the rotor is amplified by the hall amplifiers 24a, 24b, 24c and output as a hall waveform.

The outputs of the Hall amplifiers 24a, 24b and 24c are supplied to the matrix circuit 26. The matrix circuit 26 determines the phase of the motor drive current to be supplied to the coils 20a, 20b, 20c of the motor 20, based on the Hall waveform associated with the rotation phase of the rotor. And
The signal from the matrix circuit 26 is output to the output drive circuit 28.
Is supplied to.

The output drive circuit 28 has three arms each consisting of two switching transistors connected in series, and controls on / off of a total of six switching transistors by signals from the matrix circuit 26. As a result, each coil 20a, 20b, 20c of the motor 20 is
A three-phase motor drive current flows through the motor 20 to drive the motor 20.

Here, the hall elements 22a, 22b, 22
The output of c is the Hall comparators 30a, 30b, 30.
It is input to c and converted into a rectangular wave here. The outputs from the three Hall comparators 30a, 30b, 30c are
The signals are 120 ° out of phase with each other according to the number of rotations of the motor 20.

In the present embodiment, the three output signals from the Hall comparators 30a, 30b and 30c are respectively speed discriminating circuits 32a and 32.
b, 32c.

The speed discriminating circuits 32a, 32b,
32c is exactly the same as the configuration of FIG. 4 described above, and when the cycle of the input signal is longer than the preset time, the slow signal S indicating that the rotation speed is slow is output, When the cycle is shorter than the preset time, the fast signal F indicating that the rotation speed is fast is output. That is, the speed discriminating circuits 32a, 32b, 3
2c receives the signals from the Hall comparators 30a, 30b, 30c in place of the FG signal in FIG. 4, and outputs a fast signal when the cycle of the input signal is earlier than a predetermined cycle and a slow signal when the cycle is slower than a predetermined cycle.

It is also possible to change the set rotation speed of the motor and control the rotation speed of the motor 20 to the set rotation speed by determining the set rotation speed to be counted up by the counter by the motor rotation speed command.

Three speed discriminating circuits 32a, 32
The output signals of b and 32c are supplied to the combining circuit 34.
This synthesizing circuit 34 includes three speed discriminating circuits 32.
This is a circuit that sums the output signals from a, 32b, and 32c, and the signals obtained by adding all are obtained at the output of the combining circuit 34. That is, three speed discriminating circuits 32a, 3
2b and 32c measure the cycle of input signals having different phases (different by 120 °) at different timings. Therefore, the three speed discriminating circuits 32a, 3
2b, 32c output slow signal S (acceleration command),
The fast signal F (deceleration command) is generated at different timings. Therefore, by adding these, the three speed discriminating circuits 32a, 32b, 32c are added.
Will be output from the synthesizing circuit 34 as it is.

The output of the synthesis circuit 34 is the output control circuit 36.
Where it is integrated and converted into an analog speed control signal. That is, by integrating the signals S and F,
An analog signal corresponding to the difference from the set speed is obtained, and the amount of current when each switching transistor in the output drive circuit 28 is on is controlled by this. That is, S
When there are many signals, change the motor drive current greatly,
This increases the output torque of the motor and increases the rotation speed. When the F signal is large, the motor drive current is changed to a small value, the motor output torque is decreased, and the rotation speed is decreased. As a result, the rotation speed of the motor is controlled to the set rotation speed.

As described above, in this embodiment, the slow signal S and the fast signal F are independently obtained from the respective outputs of the three Hall elements 22. Therefore, it is possible to obtain a signal with a precision three times higher than that in the case where the signals S and F are simply obtained from the output of one Hall element. In addition, the hall element 22
Even if the installation positions of a, 22b, and 22c are slightly deviated, since the speed control signal is obtained by the addition result of these, there is no adverse effect on the rotation speed control.

In particular, according to this embodiment, the Hall element 2
Since the rotation speed control is performed using the signals from 2a, 22b, and 22c, even if the switching in the output drive circuit is soft switched, the rotation speed control is not adversely affected. Therefore, it is possible to omit measures against high frequency noise. Moreover, since the output of the Hall element is used, it is not necessary to provide a special sensor or the like.

In the present embodiment, the output from the Hall element is used as the rotation speed detection signal, but any signal that indicates the rotation phase of the motor can be used, and each phase of the motor can be used. Back electromotive force can also be used. Further, it is also possible to use outputs from other magnetic and optical encoders. Further, by providing a plurality of speed discriminating circuits for these outputs, the control accuracy can be increased.

"Structure example of speed discriminating circuit" FIG. 2 shows a structure example of the speed discriminating circuits 32a, 32b, 32c different from that of FIG. In this example, one counter is provided and the slow signal S and the fast signal F are output.

Hall comparators 30a, 30b, 30
The input signal indicating the rotation phase from any one of c is input to the first edge detection circuit 40. The first edge detection circuit 40 detects the falling edge of the input signal by using the clock CLK signal having a predetermined high frequency, and outputs a loading pulse having a pulse width of one clock. This load pulse is input to the second edge detection circuit 42. The second edge detection circuit 42 outputs a reset pulse for resetting the counter having the pulse width of the next one clock in response to the load pulse from the first edge detection circuit 40. The reset pulse is supplied to the counter 44 via the OR gate 62. The counter 44 clears the count value to "0" according to the reset pulse "1", and starts the counting operation according to the reset pulse "0". That is, the counter 44
Is also supplied with a clock CLK, and counts the clock CLK when the reset pulse is "0".

Each bit of the counter 44 corresponds to the inverter 4
It is connected to the data holding circuit 48 via 6. Although only one inverter 46 is shown in the figure, the output of each bit of the counter 44 is inverted, and this is connected to each bit of the data holding circuit 48. The load pulse L from the first edge detection circuit 40 is supplied to the data holding circuit 48, and the data holding circuit 48 takes in the inverted value of each bit of the counter 44 by the load pulse L.

Here, the counter 44 counts up when all the bits are "1". By inverting the value of each bit of the counter 44, the difference between the current count value and the count-up value can be calculated. . If the count-up values are not all "1", the inverted value is added to the count-up value to obtain the difference, which is stored in the data holding circuit 48.
It should be taken into. In this way, the data holding circuit 4
Reference numeral 8 captures the count value of the counter 44 for each cycle of the input signal.

The output of the counter 44 is also supplied to the count-up detector 50. The count-up detection unit 50 outputs a count-up pulse when the count value of the counter 44 reaches the count-up value.

The count-up pulse is supplied to the data holding circuit 48 as a reset pulse, and the data in the data holding circuit 48 is reset to "0" by the count-up pulse. The count-up pulse is also supplied to the flip-flop 54 via the inverter 52.

The flip-flop 54 comprises two NAND gates 56 and 58, and the inverted count-up pulse is inputted to one input terminal of the NAND gate 56. On the other hand, the reset pulse which is the output of the second edge detection circuit 42 is inverted and input to the other NAND gate 58 of the flip-flop 54 by the inverter 60. The output of the NAND gate 56 is supplied to the counter 44 as a reset signal via the OR gate 62.

Therefore, normally, the flip-flop 5
Since "1" is input to the two input terminals of 4, and the inverted signal of the reset signal from the second edge detection circuit becomes "0" every cycle, its output becomes "0". There is.

When the count-up pulse is generated, "0" is input to one end of the NAND gate 56 and its output is set to "1". And this state
The period continues until “1” is output from the second edge detection circuit 42 and “0” is input to the NAND gate 58.

Therefore, the flip-flop 54 becomes "1" only from the count up of the counter 44 to the end point of one cycle of the input pulse. Therefore, this is output as the slow signal S.

The output signal of the second edge detection circuit 42 and the output signal of the NAND gate 56 are supplied to the reset terminal of the counter 44 via the OR gate 62. Therefore, during the period when the slow signal is output, the counter
Counting is prohibited and is maintained at "0", and when the slow signal S becomes "0", counting is started.

The output of the counter 44 and the output of the data holding circuit 48 are input to the coincidence detection circuit 64. Then, when the output of the counter 44 and the output of the data holding circuit 48 match in all bits, the match detection circuit 64 determines that
"1" is output.

The output of the coincidence detection circuit 64 is input to the set terminal of the flip-flop 66. The reset signal from the second edge detection circuit 42 is input to the reset terminal of the flip-flop 66.

Therefore, the flip-flop 66 is reset to "0" at each input cycle, and the counter 44 is reset.
When the count value of is equal to the value held in the data holding circuit 48, "1" is set. Therefore, the signal from the inverting output terminal of the flip-flop 66 outputs "1" only from the beginning of one cycle of the input signal until the count value of the counter 44 matches the count value of the data holding circuit 48. It

It is preferable that the coincidence detecting circuit 64 holds the output "1" for several clocks of the clock signal CLK after detecting the coincidence. As a result, even if a reset signal is input to the flip-flop 66 immediately after the match detection, “1” can be prevented from being output to the inverted output. Therefore, when the value held in the data holding circuit 48 is “0”, the second edge detection circuit 42
It is possible to prevent the flip-flop 66 from being reset to "0" by the reset signal from.

Then, the counter 44 has its count value reset by the reset signal from the second edge detection circuit 42 and starts counting. On the other hand, the difference between the count value and the count-up value when reset is held in the data holding circuit 48. Therefore, the period in which the output of the flip-flop 66 is "1" corresponds to the period up to the count-up left when the counter 44 was reset last time, and this is output as the fast signal F.

A timing chart of such an operation is shown in FIG. In this way, when the counter 44 counts up, the slow signal S is output from the flip-flop 54 until the next count. That is, when one cycle of the input signal is longer than the set count period of the counter, it is output as the slow signal S for the difference period. Note that counting of the counter 44 is prohibited while the slow signal S is being output.

On the other hand, when one cycle of the input signal is completed before counting up, the difference data (the remaining number until the counting up) at that time is held in the data holding circuit 48 and the counter 44. Is reset and starts counting immediately. At this time, the fast signal F output from the flip-flop 66 is output by the reset signal.
Is set to “1”. Then, when the count value of the counter 44 matches the data held in the data holding circuit 48, the fast signal F is returned to "0". Therefore, when the cycle of the input signal is shorter than the set count period of the counter, the fast signal F for this difference is output.

In this way, one counter can be used to generate the slow signal S and the fast signal F similar to the case of using two counters. Therefore, by using a speed discriminating circuit with such a configuration, the number of elements can be reduced, the circuit can be simplified, and the cost of the device can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment.

FIG. 2 is a block diagram showing a configuration example of a speed discriminating circuit.

FIG. 3 is a timing chart showing an operation of the speed discriminating circuit having the configuration of FIG.

FIG. 4 is a block diagram showing a configuration of a conventional speed discriminating circuit.

FIG. 5 is a timing chart showing an operation of a conventional speed discriminating circuit.

[Explanation of symbols]

20 motors, 22a, 22b, 22c Hall elements,
24a, 24b, 24c Hall amplifier, 26 matrix circuit, 28 output drive circuit, 30a, 30b, 30c
Hall comparator, 32a, 32b, 32c speed discriminating circuit, 34 combining circuit, 36 output control circuit.

Claims (3)

[Claims] 1. A speed control generation circuit for a motor that generates a speed control signal based on a speed detection signal indicating a rotation speed of the motor, for controlling the rotation speed of the motor based on each of the plurality of speed detection signals. A plurality of individual speed control signal generating means for respectively generating the individual speed control signals, and a combining means for combining a plurality of individual speed control signals from the individual speed control signal generating means to obtain a single speed control signal. A speed control signal generation circuit for a motor, comprising: 2. The circuit according to claim 1, wherein the individual speed control signal generating means respectively generate an individual speed control signal based on speed detection signals from a plurality of Hall elements. Control signal generation circuit. 3. The circuit according to claim 1, wherein the synthesizing means includes an adder circuit that adds a plurality of individual speed control signals.