JPH09321176A - Semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the earth capacity of a semiconductor package as suppressing the increase of the electric capacity between its signal wires and to reduce simultaneously both its switching and crosstalk noises, in the semiconductor package for mounting thereon semiconductor devices integrated with many elements and operated in high-frequency regions by low voltages. SOLUTION: In this package 1, a signal wiring (4) having a plurality of signal wires 4-1, 4-2..., ground wirings 5 and power supply wirings are formed on the surface (or in the inside) of an insulation board 3. The insulation board 3 has each high-permittivity portion 6 interposed between the signal and ground wirings 4, 5 and a low-permittivity portion 7 interposed between the signal wires 4-1, 4-2 to make the electric capacity between the signal wires 4-1, 4-2 smaller than the one between the signal and ground wirings 4, 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package having improved noise resistance.

[0002]

2. Description of the Related Art Various packages made of an insulating material such as ceramics or resin, on which semiconductor elements such as LSI, ULSI, VLSI are mounted, are highly integrated due to high integration of semiconductor elements, high speed, and large chips. Higher density, higher speed,
There is a tendency for higher heat dissipation. In addition, the applications of these semiconductors are wide ranging from industrial use such as workstations, personal computers, minicomputers, and large computers to electronic devices such as portable devices, printers, copiers, cameras, televisions, and video, The performance of semiconductors is also improving.

A high-performance, highly-integrated semiconductor device package can be connected to the semiconductor device at multiple terminals with a narrow pitch, has a high wiring density, and has good heat dissipation.
It is required to be able to handle high-speed signals, to have multiple terminals and a narrow pitch for the package terminals themselves. In order to satisfy the multi-terminal and narrow pitch of the package, the package structure has changed from the conventional pin insertion type to the QFP (Quad
d Flat Package) and BGA (Ball Grid Array) etc. have been changed to surface mount type.

Among the surface mount types, the BGA package using solder bumps as input / output terminals of the package can shorten the connection distance by the terminals and can suppress reflection and delay of high-speed signals due to the inductance of the connection portion. Therefore, it is expected as a package of high performance and highly integrated semiconductor devices. In addition to shortening the connection distance by solder bumps, BGA also facilitates narrowing pitch and multiple terminals by forming bumps. Furthermore, narrowing pitch and multiple terminals by forming bumps reduces the package size itself, thus reducing the printed circuit board. It is expected that the mounting density will be improved, the electrical characteristics will be improved by reducing inductance and resistance, and the high frequency characteristics will be improved by making the package smaller.

On the other hand, with respect to the semiconductor element itself, there is an increasing demand for higher speed and lower power consumption, and in order to meet such demand, the power supply voltage and the threshold voltage tend to be lowered. There is. Of these, it is desired to reduce the power supply voltage while maintaining a high operating frequency such as 100 MHz. However, since lowering the power supply voltage leads to lower noise resistance,
It is required to improve the noise resistance of a package in which a semiconductor element having a reduced voltage is mounted. here,
In order to improve the noise resistance of the package, firstly, the inductance of the signal line in the package is reduced.
It is known that increasing the capacitance to ground of the signal line in the package is effective. Among these, to reduce the inductance of the signal line, it is effective to reduce the package size and the inductance effect in the input / output terminal portion. The BGA package described above satisfies these required characteristics, and is attracting attention as a package structure with improved noise resistance.

However, the BGA package having the conventional structure is
It does not necessarily satisfy the noise resistance sufficiently. For example, in a high frequency operation type semiconductor element, the margin for the simultaneous switching noise resistance is reduced due to the lowering of the power supply voltage, and the noise resistance of the package is further improved. There is a demand for improvement. Therefore, increasing the capacitance to ground of the above-mentioned signal line in the package has been studied.

In order to increase the capacitance of the signal line in the package to the ground, it is possible to use an insulating material having a large dielectric constant, for example. In a package using such an insulating material having a high dielectric constant, the signal line is used. Since the capacitance between them also increases, there arises a problem that crosstalk noise increases. In addition, the increase in the dielectric constant of the package as a whole causes a signal delay, and particularly in a high frequency operation type semiconductor element, the output waveform is blunted.

[0008]

As described above, with the recent trend toward higher integration of semiconductor elements, higher speed operation, and lowering of power supply voltage and threshold voltage, the required characteristics of semiconductor packages have been improved. Is getting tougher year by year. Especially,
There is a problem of lowering noise resistance due to lower power supply voltage. For example, it is considered to increase the capacitance to ground of the signal line in the package to reduce the simultaneous switching noise. The capacitance between the signal lines also increases with the increase in the capacitance to ground, and as a result, there arises a problem that crosstalk noise increases. Further, the signal delay also increases. Recently, semiconductor elements with an operating frequency of several 100 MHz or more have also appeared, and when mounting semiconductor elements with such an operating frequency, it is particularly necessary to reduce crosstalk noise and simultaneous switching noise of signal lines. Getting important.

From the above, in a semiconductor package having a highly integrated, high-frequency operation, and low-voltage semiconductor element, the capacitance to ground is increased while suppressing the increase in the electrical capacitance between the signal lines. Therefore, it is an object to reduce both the simultaneous switching noise and the crosstalk noise.

The present invention has been made in order to cope with the high integration, high frequency operation, low voltage, etc. of the semiconductor element as described above, and suppresses the increase in the electric capacity between the signal lines while suppressing the capacitance to ground. It is an object of the present invention to provide a semiconductor package capable of simultaneously reducing various types of noise by increasing the noise.

[0011]

As described in claim 1, a semiconductor package according to the present invention is provided on an insulating substrate and at least one of the surface and the inside of the insulating substrate, and has a desired wiring pattern. A plurality of signal wirings arranged according to the above, and a ground wiring and a power supply wiring provided on at least one of the surface and the inside of the insulating substrate, wherein the insulating substrate is the plurality of signals. A high dielectric constant portion arranged between the signal wiring and the ground wiring or the power supply wiring so that the electric capacitance between the wirings becomes smaller than the electric capacity between the signal wiring and the ground wiring or the power supply wiring. , A low dielectric constant portion disposed between the plurality of signal wirings.

The insulating substrate in the semiconductor package of the present invention may be either a surface wiring substrate or a multilayer substrate having internal wiring, and has a wiring layer on both the surface and the inside of the insulating substrate. It may be.

When the insulating substrate is a surface wiring substrate, as described in claim 2, the insulating substrate and a plurality of signal wirings arranged on the surface of the insulating substrate according to a desired wiring pattern. And a semiconductor package including a ground wiring and a power supply wiring provided on the surface of the insulating substrate, wherein the insulating substrate has an electric capacitance between the plurality of signal wirings and the signal wiring and the ground wiring or A high dielectric constant portion arranged between the signal wiring and the ground wiring or the power wiring adjacent to the signal wiring so as to be smaller than the electric capacity between the signal wiring and the plurality of signal wirings adjacent to each other. And a low dielectric constant portion which has been formed.

When the insulating substrate is a multilayer substrate having an internal wiring layer, the insulating multilayer substrate having a plurality of insulating layers laminated and integrated, and the insulating substrate In a semiconductor package comprising a plurality of signal wirings arranged according to a wiring pattern on an insulating layer of a conductive multilayer substrate, and a ground wiring and a power supply wiring provided on another insulating layer of the insulating multilayer substrate, The insulating layer sandwiched between the signal wire and the ground wire or the power wire is such that the electric capacity between the plurality of signal wires is smaller than the electric capacity between the signal wire and the ground wire or the power wire. A high dielectric constant portion arranged between the signal wiring and the ground wiring or the power supply wiring, and a low dielectric constant portion arranged between the plurality of signal wirings. It is intended to.

In the semiconductor package of the present invention,
Since the insulating substrate has a high dielectric constant portion arranged between the signal wiring and the ground wiring or the power supply wiring and a low dielectric constant portion arranged between a plurality of adjacent signal wirings, It is possible to increase the capacitance to ground and suppress the increase in electrical capacitance between the signal wirings. Therefore, it is possible to reduce simultaneous switching noise and suppress an increase in crosstalk noise.

[0016]

Embodiments of the present invention will be described below.

FIG. 1 is a sectional view showing the structure of a main part of a semiconductor package according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram thereof. The semiconductor package 1 shown in these figures has an insulating substrate 3 on the surface of which a wiring layer 2 is provided. The wiring layer 2 on this surface is an insulating substrate 3
Are electrically connected to first and second input / output electrodes (not shown) provided on at least one of the main surfaces. An input / output terminal such as a pin terminal or a bump terminal is connected to one of the first and second input / output electrodes (not shown) to form the semiconductor package 1.

The above-mentioned wiring layer 2 has a signal wiring 4 and a ground wiring 5. Although illustration is omitted, power supply wiring is also provided on the surface of the insulating substrate 3. The signal wiring 4 is formed in a desired wiring pattern, and the plurality of signal lines 4-1 and 4-2 arranged according to this wiring pattern.
…have. Also, there are a plurality of ground wirings 5.

The insulating substrate 3 has a high dielectric constant portion 6 arranged between each of the signal lines 4-1 and 4-2 and the ground wiring 5 adjacent thereto, and the adjacent signal lines 4-1 and 4-2. And a low dielectric constant portion 7 disposed between the two. These high-dielectric-constant portion 6 and low-dielectric-constant portion 7 basically have an effective dielectric constant ε _SG between the signal wiring 4 and the ground wiring 5 and an adjacent signal line 4-
Effective dielectric constant ε _SS between 1 and 4-2 is ε _SG > ε _SS
Anything that satisfies the relationship

Here, in the semiconductor package 1 constituted by the insulating substrate 3 having the wiring layer 2 as described above, the simultaneous switching noise is caused by the electric capacitance (ground capacitance) C between the signal wiring 4 and the ground wiring 5. is affected by the _SG, the simultaneous switching noise larger the capacitance to ground C _SG becomes small. On the other hand, the crosstalk noise is affected by the electric capacitance (inter-signal line capacitance) C _SS between the signal lines 4-1, 4-2, ..., And the smaller the inter-signal line capacitance C _SS , the smaller the crosstalk noise. The signal line capacitance C _SS is the electric capacitance C _S-S1 , C _S-S2 , ... C between the signal lines 4-1, 4-2, ...
Sum of _S-Sn , that is, C _SS = C _S-S1 + C _S-S2 ... + C _S-Sn
It is represented by

Therefore, in the above-mentioned insulating substrate 3, by arranging the high dielectric constant portion 6 between each signal line 4-1, 4-2 and the ground wiring 5, the capacitance to ground C _SG is increased. Therefore, simultaneous switching noise can be reduced. At this time, if the insulating substrate 3 is entirely made of a high dielectric constant material, the electric capacitance C between the signal lines 4-1, 4-2, ...
_{Since S-S1} , C _S-S2 , ..., C _S-Sn also increase, and as a result, the inter-signal line capacitance C _SS increases, the crosstalk noise increases conversely. On the other hand, in the semiconductor package 1 of this embodiment, the signal lines 4-1 and
The low dielectric constant portion 7 is arranged between 4-2, thereby suppressing an increase in the signal line capacitance C _SS , and further, increasing the signal line capacitance C _SS.
This makes it possible to reduce _SS . Therefore, for example, even when a semiconductor element with high integration, high frequency operation, and low voltage is mounted, it is possible to reduce crosstalk noise after realizing reduction of simultaneous switching noise.

FIG. 3 shows the electric capacitance C _SG between the signal line 4 and the ground line 5 and the electric capacitance C between the signal lines 4-1 and 4-2.
Details of _SS are shown. The signal line-ground capacitance (to ground) C _SG can be expressed as C _SG = C _ga + C _gss + C _gsu . Here, C _ga is the electric capacitance component of the line of electric force passing through the air between the signal wiring 4 and the ground wiring 5, and C _gss is the electric capacitance component between the electrodes of the signal wiring 4 and the ground wiring 5,
C _gsu is an electric capacitance component of a line of electric force passing through the substrate 4 between the signal wiring 4 and the ground wiring 5. On the other hand, the signal line capacitance C _SS can be expressed as C _SS = C _sa + C _sss + C _ssu, and C _sa , C _sss , and C _ssu are the same.

C _gss and C _sss are determined by the thickness of the electrodes, the spacing, and the dielectric constant of the dielectric material present therein. Generally, the larger the thickness, the smaller the interval, and the larger the dielectric constant, the larger the electric capacity. Also, C _gsu and C
_ssu is determined by the width of the electrodes, the spacing, and the permittivity of the dielectric that exists there, and the tendency of the magnitude of the capacitance is still the smaller the spacing between the electrodes and the larger the permittivity (the electrode width is the package design Same as above).

Therefore, the high dielectric constant portion 6 having a large dielectric constant is arranged between each of the signal lines 4-1 and 4-2 and the ground wiring 5 adjacent thereto, and the adjacent signal lines 4-1 and 4-2 are arranged. By arranging the low dielectric constant portion 7 having a small dielectric constant between the two, the signal wiring 4 and the signal wiring 4 can be held while suppressing the electric capacitance (capacity between signal lines C _SS ) between the adjacent signal lines 4-1 and 4-2. It is possible to increase only the electric capacitance (to the ground capacitance C _SG ) between the ground wirings 5.

In the above description, the case where the simultaneous switching noise and the crosstalk noise are simultaneously reduced has been described. For example, a standard insulating substrate made of one kind of insulating material is used as a reference, and each signal line and the ground wiring are connected to each other. A high dielectric constant portion 6 having a higher dielectric constant than the reference insulating layer is arranged to reduce simultaneous switching noise, or a low dielectric constant portion 7 having a lower dielectric constant than the reference insulating layer 7 is provided between signal lines.
It is also possible to reduce the crosstalk noise by arranging. As described above, the high dielectric constant portion 6 and the low dielectric constant portion 7 are at least ε _SG > ε when compared with each other.
Anything that satisfies the _SS will do.

Further, in the above embodiment, the signal lines 4-1 and 4 are provided.
This is a case where the high dielectric constant portion 6 is arranged between the -2 and the ground wiring 5, but the same effect can be obtained even if the high dielectric constant portion 6 is arranged between the high dielectric constant portion 6 and the power supply wiring. That is, the simultaneous switching noise can be reduced by disposing the high dielectric constant portion between the signal line and the ground wiring or the power supply wiring. Up to this point, the respective configurations and actions have been described by focusing on the simultaneous switching noise and the crosstalk noise, but it is desired to further suppress the signal delay in the semiconductor package 1. Signal delay is the total capacity C _total
Controlled by (= C _SG + C _SS ), the larger the total capacity C _total , the larger the signal delay. Therefore, it is preferable to set the dielectric constant of the high dielectric constant portion 6 so as to increase the capacitance C _SG to ground within the allowable range of the signal delay.

FIG. 4 shows a simulation result of simultaneous switching noise (ΔI) and rounding of the output waveform when the capacitance C _SG to ground is used as a parameter (from 90% of the output waveform.
(Defined as the time to fall to 10%). The model used for the calculation has a package size of 50 x 50 mm and a signal line length of 30 mm.
And The equivalent circuit (simulation model) of this package is shown in FIG. L _s , R _s , C _gs , R _GND , L
_GND is the inductance of the signal line of the package,
They are electrical resistance, capacitance to ground, electrical resistance of ground, and inductance. It is also assumed that 8 circuits switch at the same time. The constants used for the calculation are L _s = 8.2nH, R _s =
It was 2.2Ω and the power supply voltage was 3.3V.

From FIG. 4, the capacitance to ground of the signal line C _SG (C
It can be seen that the noise becomes smaller as _gs ) becomes larger, but the rounding of the output waveform becomes larger. That is, the signal delay increases. In FIG. 4, the point is the case where the dielectric constant of the material between the signal-signal line and the signal-ground line is the same, and the point is the case where the latter is about 15 times the former. In obtaining the noise suppressing effect, the dielectric constant between the signal wiring 4 and the ground wiring 5, that is, the dielectric constant ε _SG of the high dielectric constant portion 6, and the dielectric constant between the signal lines 4-1 and 4-2, that is, the low dielectric constant portion. The ratio ε _SG / ε _{SS to} the dielectric constant ε _{SS of} 7 is preferably 1.5 or more, and is preferably 10 or less in order to suppress an increase in signal delay. That is, the dielectric constant ratio ε _SG / ε _SS
Is preferably 1.5 ≦ ε _SG / ε _SS ≦ 10.

Next, a specific configuration example of the semiconductor package 1 of the above-described embodiment will be described.

A semiconductor package 1 whose essential parts are shown in FIG.
First, the insulating substrate 3 is made of the high dielectric constant material 8, and the portions of the high dielectric constant material 8 corresponding to the respective wirings are removed by etching to form the recesses 9 (FIG. 6A). Next, the low dielectric constant material 10 is embedded in the recess 9 removed by etching (FIG. 6-b). Then, the signal wiring 4 and the ground wiring 5 are formed in desired patterns on the low dielectric constant material 10. In this case, the insulating substrate 3 made of the high dielectric constant material 8 becomes the high dielectric constant portion, and the low dielectric constant material 10 becomes the low dielectric constant portion. Note that, as shown in FIG. 7, the low dielectric constant material 10 may be arranged only in the portion corresponding to between the signal lines 4-1 and 4-2.

The high dielectric constant material 8 and the low dielectric constant material 1 described above.
As a combination with 0, for example, insulation of alumina (relative permittivity = about 10), aluminum nitride (relative permittivity = about 8), silicon nitride (relative permittivity = about 9), etc. as the high permittivity material 8 Ceramics material, polyimide resin (relative permittivity = about 3.5), epoxy resin (relative permittivity = about 5), Teflon resin (relative permittivity = 2 ~)
3), BT resin (relative permittivity = about 4), PPE resin (relative permittivity = about 3), and other combinations of insulating resin materials.

Further, since the above-mentioned insulating ceramic material and insulating resin material can reduce the dielectric constant by providing a cavity (pore or the like) therein, a high-density insulating material as the high dielectric constant material 8 can be obtained. Combination of a conductive ceramic material and a low-density insulating ceramic material as the low dielectric constant material 10, a combination of a high-density insulating resin material and a low-density insulating resin material, and a high-density insulating ceramic A combination of a material and a low-density insulating resin material can be applied. Further, among the insulating ceramic materials and the insulating resin materials, since the dielectric constants differ depending on the materials, a combination thereof can also be used.

FIG. 8 shows a second package of the semiconductor package 1.
3 is a cross-sectional view showing the main parts of a specific configuration example of FIG. In the semiconductor package whose main part is shown in FIG. 8, first, the insulating substrate 3 is made of the low dielectric constant material 10, and the signal wiring 4 and the ground wiring 5 are respectively provided on the insulating substrate 3 made of the low dielectric constant material 10. A desired circuit pattern is formed (FIG. 8-a). An example of such a low dielectric constant material with a circuit pattern is a TAB tape. After that, the high dielectric constant material 8 is patterned between the signal wiring 4 and the ground wiring 5 by means such as a printing technique (FIG. 8B). In the semiconductor package having such a structure, C in FIG.
The relationship of _gss > C _sss is established, and therefore the condition of C _SG > C _SS is satisfied. As shown in FIG. 9, a coat layer 11 may be further provided on the top by resin molding, potting, or the like.

Since the semiconductor package 1 according to each of the above-described specific configuration examples has the high dielectric constant portion and the low dielectric constant portion that satisfy the relationship of ε _SG > ε _SS , simultaneous switching noise It is possible to reduce the crosstalk noise after realizing the reduction. Further, by controlling the dielectric constant of the high dielectric constant portion, it is possible to suppress an increase in signal delay. Therefore, since malfunctions due to these signal noises can be suppressed, the operating frequency especially
It becomes possible to stably operate a low voltage drive type semiconductor element exceeding 100 MHz.

As described above, the semiconductor package 1 is used as a PGA package by bonding the pin terminals, or as a BGA package by bonding the bump terminals. Among these, the BGA package, which can reduce the package size and the inductance effect in the terminal portion, is particularly preferable because the BGA package can further improve the noise resistance.

Next, another embodiment of the semiconductor package of the present invention will be described.

FIG. 10 is a sectional view showing the structure of the main part of a semiconductor package according to another embodiment of the present invention.
1 is its equivalent circuit diagram. The semiconductor package 12 shown in these figures has a plurality of insulating layers 13a, 13b, 13
It has an insulating multilayer substrate 13 in which c ... Are laminated and integrated, and inside layer wiring 14 is provided in this insulating multilayer substrate 13. The inner-layer wiring 14 is electrically connected to first and second input / output electrodes (not shown) provided on at least one main surface of the insulating multilayer substrate 13 through via holes (not shown). It is connected. One of the first and second input / output electrodes (not shown) is connected to one of input / output terminals such as pin terminals and bump terminals to form the semiconductor package 12.

The inner layer wiring 14 includes the signal wiring 4 formed on the insulating layer 13b of the insulating multilayer substrate 13 and the other insulating layer 1
3c and the ground wiring 5 formed on it. Although illustration is omitted, power supply wiring is also provided in the insulating multilayer substrate 13. The signal wiring 4 is formed in a desired wiring pattern and has a plurality of signal lines 4-1, 4-2, 4-3, ... Arranged according to this wiring pattern.

Here, the insulating layer 13b in which the signal wiring 4 is formed on the upper side and the ground wiring 5 is arranged on the lower side, that is, the insulating layer 13b sandwiched between the signal wiring 4 and the ground wiring 5 is used for each signal. Wires 4-1, 4-2, 4-3 and ground wiring 5
And the high-dielectric constant portion 6 disposed between the signal lines 4-1 and 4
-2, 4-3, and a low dielectric constant portion 7 disposed between them.
These high-dielectric-constant portion 6 and low-dielectric-constant portion 7 are basically similar to the above-described embodiment in that the effective dielectric constant ε _SG between the signal wiring 4 and the ground wiring 5 and each signal line 6-. 1, 6-
The effective dielectric constant ε _SS between 2 and 6-3 is ε _SG > ε _SS
Anything that satisfies the relationship

In the semiconductor package 12 constructed by disposing the inner layer wiring 14 in the insulating multi-layer substrate 13 described above,
Insulating layer 13b sandwiched between the signal wiring 4 and the ground wiring 5
In, in each signal line 4-1, 4-2, 4-3 and ground wiring 5
Since the high dielectric constant portion 6 is arranged between the and, and the capacitance to ground C _SG is increased, the simultaneous switching noise can be reduced as in the above-described embodiment. Further, the low dielectric constant portion 7 is arranged between the signal lines 4-1, 4-2, and 4-3 to suppress the increase of the signal line capacitance C _SS , and further, to suppress the signal line capacitance C _SS. It is possible to reduce. Therefore, similar to the above-described embodiment, for example, even when a semiconductor element having high integration, high frequency operation, and low voltage is mounted, simultaneous switching noise is reduced and then crosstalk noise is reduced. It becomes possible.

Table 1 shows that when the permittivity of the low permittivity part 7 is kept constant at 3, and the permittivity of the high permittivity part 6 is changed to 3, 9, 40, the pair per unit length is changed. The ground capacitance C _SG and the signal line capacitance C _SS are shown. The high dielectric constant portion 6 and the low dielectric constant portion 7 had a thickness of 20 μm and a width of 50 μm. Table 1 also shows the inductance L and the resistance R of the signal line 4 in this case. The signal line 4 is made of C having a thickness of 5 μm.
u wiring.

[0042]

[Table 1] As is clear from Table 1, by increasing the dielectric constant of the high dielectric constant portion 6, only the capacitance to ground C _SG can be increased. That is, for example, even when the power supply voltage is lowered, it is possible to reduce the simultaneous switching noise without increasing the crosstalk noise.

In the above description, the case where the simultaneous switching noise and the crosstalk noise are simultaneously reduced has been described. However, similar to the above-described embodiment, the simultaneous multi-layer substrate made of one type of insulating material is used as the reference. It is possible to reduce switching noise and crosstalk noise. Further, the same effect can be obtained even if the high dielectric constant portion 6 is arranged between the high dielectric constant portion 6 and the power supply wiring.

Further, the suppression of the signal delay is the same as in the above-described embodiment, and the dielectric constant of the high dielectric constant portion 6 is set so that the capacitance C _SG to ground is increased within the allowable range of the signal delay. Is preferred. Specifically, similar to the above-described embodiment, in order to obtain the noise suppressing effect, the dielectric constant between the signal wiring 4 and the ground wiring 5, that is, the dielectric constant ε _SG of the high dielectric constant portion 6, and each signal line 4-. Dielectric constant between 1, 4-2 and 4-3, that is, the ratio to the dielectric constant ε _SS of the low dielectric constant portion 7 ε _SG / ε
_SS is preferably 1.5 or more, and is preferably 10 or less in order to suppress an increase in signal delay.

Next, a specific configuration example of the semiconductor package 12 of the above-described embodiment will be described.

FIG. 12 is a cross-sectional view showing the main parts of the first specific structural example of the semiconductor package 12. In addition,
FIG. 12 illustrates only the signal wiring 4, the insulating layer 13b, and the ground wiring 5, and the same applies to the drawings showing other specific configuration examples described below. In the semiconductor package 12 whose main part is shown in FIG. 12, first, the insulating layer 13b is made of the high dielectric constant material 8 and the signal wiring 4 is formed thereon in a desired pattern. Signal lines 4-1, 4-2, 4
The portion located between -3 is removed by etching to form the recess 9 (FIG. 12-a). After that, the low dielectric constant material 10 is embedded in the recess 9 removed by etching (FIG. 12-b). The signal wiring 4 may be formed after the low dielectric constant material 10 is embedded. In this case, the high dielectric constant material 8 becomes the high dielectric constant portion, and the low dielectric constant material 10 becomes the low dielectric constant portion. As the high dielectric constant material 8 and the low dielectric constant material 10,
A combination similar to the combination exemplified in the above-described embodiment can be used.

If there is no problem in terms of the structure and strength of the insulating multi-layer substrate 13, the recess 9 formed by etching can be directly used as the low dielectric constant portion as shown in FIG. In this case, the insulating layer 13b is not limited to the one formed of the high dielectric constant material 8, and various insulating materials can be used.

FIG. 14 is a cross-sectional view showing the main parts of a second specific structural example of the semiconductor package 12. FIG.
In the semiconductor package 12 whose main part is shown in FIG. 1, the high dielectric constant material 8 arranged on the ground wiring 5 side and the low dielectric constant material 10 arranged on the ground dielectric line 5 constitute an insulating layer 13b. Specific materials of the high dielectric constant material 8 and the low dielectric constant material 10 are as described above.

In such a configuration, each signal line 4-
The dielectric constant ε _SS between 1, 4-2 and 4-3 is determined by the low dielectric constant material 10, and the dielectric constant ε _SG between the signal wiring 4 and the ground wiring 5 is the high dielectric constant material 8 and the low dielectric constant material 10. Therefore, the relationship of ε _SG > ε _SS can be satisfied.

FIG. 15 is a sectional view schematically showing a main part of a third concrete structural example of the semiconductor package 12. In the semiconductor package 12 whose main part is shown in FIG. 15, the insulating layer 13b is formed of an insulating material 15 having anisotropy in dielectric constant. The dielectric anisotropy insulating material 15, the vertical direction - is different from the dielectric constant epsilon _L permittivity epsilon _T and lateral (signal line ground line direction) (the signal line between direction), the dielectric constant epsilon _T
It is formed to have a dielectric constant ε _L. Examples of such a dielectric anisotropy insulating material 15 include a single crystal film of aluminum nitride, boron nitride, or the like, a polymer material stretched in the lateral direction to have anisotropy, or the like. Even in such a configuration, the relationship of ε _SG > ε _SS can be satisfied.

Since the semiconductor package 12 according to each of the above-described specific configuration examples has the high dielectric constant portion and the low dielectric constant portion that satisfy the relationship of ε _SG > ε _SS , the simultaneous switching noise of It is possible to reduce the crosstalk noise after realizing the reduction. Further, by controlling the dielectric constant of the high dielectric constant portion, it is possible to suppress an increase in signal delay. Therefore, since malfunctions due to these signal noises can be suppressed, it becomes possible to stably operate a low voltage drive type semiconductor element having an operating frequency exceeding 100 MHz.

As described above, the semiconductor package 12 is used as a PGA package by bonding the pin terminals, or as a BGA package by bonding the bump terminals. Among these, the BGA package, which can reduce the package size and the inductance effect in the terminal portion, is particularly preferable because the BGA package can further improve the noise resistance.

[0053]

As described above, according to the semiconductor package of the present invention, it is possible to increase the capacitance to ground while suppressing the increase in the electrical capacitance between the signal lines. Therefore, simultaneous switching noise and crosstalk are prevented. It is possible to reduce noise together. Therefore, high integration of semiconductor devices,
It is possible to provide a semiconductor package that is compatible with high frequency operation and low voltage.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a configuration of a main part of a semiconductor package according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the semiconductor package shown in FIG.

FIG. 3 is a diagram showing components of electric capacitance of the semiconductor package shown in FIG.

FIG. 4 is a diagram showing the relationship (simulation result) between the capacitance to ground and noise and the rounding of the output waveform of the semiconductor package shown in FIG. 1.

5 is a diagram showing a package model for calculating the simulation result shown in FIG.

6 is a cross-sectional view of a main part showing a first specific configuration example of the semiconductor package shown in FIG.

FIG. 7 is a cross-sectional view of essential parts showing a modified example of the specific configuration example shown in FIG. 6.

8 is a cross-sectional view of a main part showing a second specific configuration example of the semiconductor package shown in FIG.

FIG. 9 is a cross-sectional view of essential parts showing a modified example of the specific configuration example shown in FIG. 8.

FIG. 10 is a cross-sectional view showing a configuration of a main part of a semiconductor package according to another embodiment of the present invention.

11 is an equivalent circuit diagram of the semiconductor package shown in FIG.

12 is a sectional view of a key portion showing a first specific structural example of the semiconductor package shown in FIG.

13 is a cross-sectional view of essential parts showing a modification of the specific configuration example shown in FIG.

14 is a sectional view of a key portion showing a second specific configuration example of the semiconductor package shown in FIG.

15 is a sectional view of a key portion showing a third specific structural example of the semiconductor package shown in FIG.

[Explanation of symbols]

 1, 12 ... Semiconductor package 2 ... Insulating substrate 4 ... Signal wiring 4-1, 4-2, 4-3 ... Signal wiring 5 ... Ground wiring 6 ... High dielectric constant part 7 ... Low dielectric constant Part 8 ... High dielectric constant material 10 ... Low dielectric constant material 13 ... Insulating multi-layer substrate 13a, 13b, 13c ... Insulating layer

Claims (3)

[Claims] 1. An insulating substrate, a plurality of signal wirings provided on at least one of the surface and the inside of the insulating substrate and arranged according to a desired wiring pattern, and at least the surface and the inside of the insulating substrate. In a semiconductor package including a ground wire and a power wire provided on one side, the insulating substrate has an electrical capacitance between the signal wires and the ground wire or the power wire. It has a high dielectric constant portion arranged between the signal wiring and the ground wiring or the power supply wiring so as to be smaller than the capacitance, and a low dielectric constant portion arranged between the plurality of signal wirings. And semiconductor packages. 2. An insulating substrate, a plurality of signal wirings arranged on the surface of the insulating substrate according to a desired wiring pattern, and a ground wiring and a power supply wiring provided on the surface of the insulating substrate. In the semiconductor package, the insulating substrate is adjacent to the signal wiring such that the capacitance between the plurality of signal wirings is smaller than the capacitance between the signal wiring and the ground wiring or the power supply wiring. And a low dielectric constant portion disposed between the plurality of adjacent signal wirings, and a high dielectric constant portion disposed between the ground wiring and the power supply wiring. 3. An insulating multilayer substrate having a plurality of insulating layers laminated and integrated, and a plurality of signal wirings arranged on the insulating layer of the insulating multilayer substrate according to a wiring pattern,
In a semiconductor package including a ground wiring and a power wiring provided on another insulating layer of the insulating multilayer substrate, the insulating layer sandwiched between the signal wiring and the ground wiring or the power wiring is A high dielectric constant arranged between the signal wiring and the ground wiring or the power supply wiring so that the electric capacitance between the signal wiring and the signal wiring is smaller than the electric capacity between the signal wiring and the ground wiring or the power supply wiring. And a low dielectric constant portion disposed between the plurality of signal wirings, a semiconductor package.