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JPH09293759A - Semiconductor device mounting method and circuit mounting board used therefor - Google Patents

Semiconductor device mounting method and circuit mounting board used therefor

Info

Publication number
JPH09293759A
JPH09293759A JP8106788A JP10678896A JPH09293759A JP H09293759 A JPH09293759 A JP H09293759A JP 8106788 A JP8106788 A JP 8106788A JP 10678896 A JP10678896 A JP 10678896A JP H09293759 A JPH09293759 A JP H09293759A
Authority
JP
Japan
Prior art keywords
semiconductor element
mounting
bumps
resin
conductive material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8106788A
Other languages
Japanese (ja)
Inventor
Kenji Yoshimi
健二 吉見
Masaaki Okunaka
正昭 奥中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8106788A priority Critical patent/JPH09293759A/en
Publication of JPH09293759A publication Critical patent/JPH09293759A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To realize a bare chip mounting method which can be carried out independent of bumps that are not uniform in height. SOLUTION: Bumps 9 provided onto the connection terminal 4 of a semiconductor device 1 are formed of a conductive material which is easily plastically deformed so as to eliminate the influence of a lack of uniformity in their height. When the semiconductor device 1 is pressed down against a circuit mounting board 2, the high bumps 9 are deformed, so that the low bumps 8 can be bonded enough. Uncured thermosetting resin or photosetting resin 10 is used so as to firmly bond the device 1 and the circuit mounting board 2 together.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は半導体素子の回路基
板上への実装方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor device on a circuit board.

【0002】[0002]

【従来の技術】近年、ノートパソコン、携帯電話、PH
S,PDAなどの携帯情報端末機器、またムービ、カメ
ラなどの携帯映像機器などにおいて高密度実装のニーズ
が益々高くなっている。これに対応すべく、半導体素子
の実装は従来のパッケージ品を実装する方法から、素子
を直接基板に実装する、いわゆるベアチップ実装方式が
主流になりつつある。
2. Description of the Related Art In recent years, laptop computers, mobile phones, PH
There is an increasing need for high-density mounting in mobile information terminal devices such as S and PDAs, and mobile video devices such as movies and cameras. In order to cope with this, the so-called bare chip mounting method in which the element is directly mounted on the substrate is becoming the mainstream for mounting the semiconductor element from the conventional method for mounting the packaged product.

【0003】回路基板上に半導体素子を直接実装するた
めの方法として、従来、(1)基板にまず半導体素子をフ
ェースアップで接着し、次いで基板の接続端子と半導体
素子の接続端子を金あるいはアルミニウムのワイヤで接
続するワイヤボンディング方式(図1)、(2)接続端子
にはんだバンプを形成した半導体素子をフェースダウン
で基板に搭載し、次いでリフロにより接続する。最後に
半導体素子と基板との間に樹脂を充填する方法(図
2)、(3)基板に異方性導電フィルム(樹脂中に導電粒
子を分散させたもの)を貼り付け、次いで接続端子に金
バンプを形成した半導体素子をフェースダウンで加熱圧
着する方法(図3)がある。
Conventionally, as a method for directly mounting a semiconductor element on a circuit board, (1) a semiconductor element is first bonded face-up to a substrate, and then a connection terminal of the board and a connection terminal of the semiconductor element are made of gold or aluminum. (2) Wire bonding method for connecting with wires (2), (2) A semiconductor element having solder bumps formed on connection terminals is mounted face down on a substrate and then connected by reflow. Finally, a method of filling a resin between the semiconductor element and the substrate (Fig. 2), (3) Attaching an anisotropic conductive film (having conductive particles dispersed in resin) to the substrate, and then connecting terminals There is a method (FIG. 3) of face-down thermocompression bonding of a semiconductor element on which gold bumps are formed.

【0004】[0004]

【発明が解決しようとする課題】上記した、回路基板上
への半導体実装方法のうち(1)のワイヤボンディング
方式は、半導体パッケージのインナリードボンディング
で実績のある方法で確立した技術であるが、基板上に半
導体素子の搭載エリアの外側に接続端子を設ける必要が
あるため実質上の占有面積は大きくなってしまい、高密
度実装の面からみれば他の二つの方式より劣る。また、
(2)のはんだバンプ方式は、信頼性確保のためには半
導体素子と基板との間に樹脂充填が必要であるため実装
のための工数がかかる問題点を有するとともに、はんだ
を接続部材とするため狭接続ピッチ、多ピンの半導体素
子の接続に対応できない欠点がある。(3)の異方性導
電フィルム方式は、実装工数も少なく、狭接続ピッチ、
多ピンの半導体素子の接続に対応できる方法ではある
が、半導体素子に形成した金バンプの高さばらつきが大
きい場合に全バンプを均一に接続することが困難となる
問題がある。
Among the above-described semiconductor mounting methods on a circuit board, the wire bonding method (1) is a technique established by a proven method for inner lead bonding of a semiconductor package. Since it is necessary to provide the connection terminals on the outside of the mounting area of the semiconductor element on the substrate, the actual occupied area becomes large, which is inferior to the other two methods in terms of high-density mounting. Also,
The solder bump method of (2) has a problem that a man-hour for mounting is required because resin filling is required between the semiconductor element and the substrate for ensuring reliability, and solder is used as a connecting member. Therefore, there is a drawback that it is not possible to cope with a narrow connection pitch and connection of a multi-pin semiconductor element. The anisotropic conductive film method of (3) has a small mounting man-hour, a narrow connection pitch,
Although this method can be applied to the connection of multi-pin semiconductor elements, there is a problem that it is difficult to connect all the bumps uniformly when the height variation of the gold bumps formed on the semiconductor element is large.

【0005】[0005]

【課題を解決するための手段】上記した従来法の課題を
解決するために考案した本発明の方式は、 (1)まず、半導体素子の接続端子に容易に塑性変形でき
る導電材料でバンプを形成(図4(a))。
The method of the present invention devised to solve the above-mentioned problems of the conventional method is as follows: (1) First, a bump is formed on a connection terminal of a semiconductor element with a conductive material that can be easily plastically deformed. (FIG. 4 (a)).

【0006】(2)次いで、基板上の接続端子部に未硬化
の熱硬化性樹脂あるいはそのフィルム、 または光硬化
性樹脂を供給する(図4(b))。
(2) Next, an uncured thermosetting resin or its film or a photo-curing resin is supplied to the connection terminal portion on the substrate (FIG. 4 (b)).

【0007】(3)半導体素子と基板とを位置合わせした
のち加熱圧着する(図4(c))。
(3) The semiconductor element and the substrate are aligned and then thermocompression bonded (FIG. 4 (c)).

【0008】この方法は、(1)実装に必要な基板上の
占有面積は半導体素子のサイズ相当面積のみであり、従
来方式のワイヤボンディング方式より高密度実装が可能
である。また、実装工数は、従来法のはんだバンプ方式
と較べ少ない工数である。さらに、接続ピッチもはんだ
バンプ方式より小さくできる。また。バンプを容易に塑
性変形できる導電材料で形成することにより、従来法の
異方性導電性フィルム方式の問題点であった、バンプ高
さばらつきに起因する不良発生がない利点を有する。
In this method, (1) the occupied area on the substrate required for mounting is only the area corresponding to the size of the semiconductor element, and high-density mounting is possible as compared with the conventional wire bonding method. Also, the mounting man-hour is smaller than that of the conventional solder bump method. Further, the connection pitch can be made smaller than that of the solder bump method. Also. By forming the bumps with a conductive material that can be easily plastically deformed, there is an advantage that defects due to bump height variations, which are problems of the conventional anisotropic conductive film method, do not occur.

【0009】本発明に使用する、容易に塑性変形できる
導電材料としては、(1)柔軟金属、例えば、インジウ
ム、鉛(図5(a))、(2)金属皮膜を施したプラスチ
ック(図5(b))、(3)熱可塑性樹脂をバインダとす
る導電性接着剤(図5(c))、(4)導電性ポリマ(図
5(d))、が使用可能である。インジウムなどの柔軟金
属バンプはめっきとフォトリソ工程で製作する。金属皮
膜を施したプラスチックバンプは、まず素子接続端子に
金などの金属膜を蒸着、スパッタ、めっきなどの成膜法
とフォトリソ法によりパターン形成し、次にプラスチッ
ク膜を金属膜上の一部分に形成する。最後に、無電解め
っきを行なうことによりプラスチック上全面に金属皮膜
を形成する。熱可塑性樹脂をバインダとする導電性接着
剤バンプ、及び、導電性ポリマバンプは高精度印刷によ
り素子接続端子部にパターン形成する。
The conductive material which can be easily plastically deformed for use in the present invention includes (1) flexible metal such as indium, lead (FIG. 5 (a)), and (2) metal coated plastic (FIG. 5). (b)), (3) a conductive adhesive containing a thermoplastic resin as a binder (FIG. 5 (c)), and (4) a conductive polymer (FIG. 5 (d)) can be used. Flexible metal bumps such as indium are manufactured by plating and photolithography processes. For a plastic bump with a metal film, first, a metal film such as gold is deposited on the element connection terminals by patterning by a film forming method such as vapor deposition, sputtering, plating, etc. and a photolithography method, and then a plastic film is formed on a part of the metal film. To do. Finally, electroless plating is performed to form a metal film on the entire surface of the plastic. The conductive adhesive bumps using the thermoplastic resin as a binder and the conductive polymer bumps are pattern-formed on the element connection terminal portion by high-precision printing.

【0010】一般に接続バンプの総面積は半導体素子の
面積に較べ極めて小さいため、半導体素子と回路基板と
を単に加熱圧着し、バンプ部の接合力のみで接続信頼性
を確保することは難しい。そこで本発明ではバンプを形
成した半導体素子と回路基板とを強固に接合するために
素子と基板とを樹脂で接合する。十分な接続信頼性を得
るためにはこの樹脂としてエポキシ系樹脂などの熱硬化
性樹脂、あるいはアクリル系樹脂などの光硬化性樹脂を
用いる。熱可塑性樹脂では熱膨張係数が大きく、吸水率
も大きいため十分な接続信頼性が得られない。これらの
樹脂を使用する形態として、液状樹脂を基板接続端子部
にディスペンサなどで供給すことも可能であるが、フィ
ルム状未硬化樹脂を使用する方が作業性の点で優れる。
Generally, since the total area of the connection bumps is extremely smaller than the area of the semiconductor element, it is difficult to simply thermocompress the semiconductor element and the circuit board and secure the connection reliability only by the bonding force of the bump portion. Therefore, in the present invention, in order to firmly bond the semiconductor element on which the bump is formed and the circuit board, the element and the board are bonded with resin. To obtain sufficient connection reliability, a thermosetting resin such as an epoxy resin or a photocurable resin such as an acrylic resin is used as this resin. A thermoplastic resin has a large coefficient of thermal expansion and a large water absorption, so that sufficient connection reliability cannot be obtained. As a form of using these resins, a liquid resin can be supplied to the substrate connecting terminal portion by a dispenser or the like, but using a film-shaped uncured resin is superior in workability.

【0011】接合は圧着方式で行なう。未硬化の熱硬化
性樹脂を使用する場合には、加熱した加圧ヘッドを用い
ることにより加熱と加圧を同時に行なう。光硬化性樹脂
を使用する場合には、加圧時に素子と基板との空隙から
紫外線を照射する。ガラス製の基板の場合には基板裏面
から紫外線を照射する。
Bonding is performed by a pressure bonding method. When an uncured thermosetting resin is used, heating and pressing are performed simultaneously by using a heated pressing head. When a photo-curable resin is used, ultraviolet rays are radiated from the gap between the element and the substrate when applying pressure. In the case of a glass substrate, ultraviolet rays are emitted from the back surface of the substrate.

【0012】本発明の接続方法によれば、バンプ高さば
らつきのある半導体素子を材料で接続した場合、高さの
高いバンプにまず荷重が掛かるが、バンプが容易に変形
するため、高さの低いバンプがあっても接続不良となる
ことはなく(図6(a),(b),(c),(d))高歩留りで
ベアチップ実装が可能である。
According to the connection method of the present invention, when a semiconductor element having a bump height variation is connected by a material, a load is first applied to a bump having a high height, but the bump is easily deformed. Even if there are low bumps, there is no connection failure (FIGS. 6A, 6B, 6C, and 6D), and bare chip mounting is possible with high yield.

【0013】[0013]

【発明の実施の形態】以下、本発明を実施例により説明
する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to embodiments.

【0014】[実施例1]使用した部材を以下に記す。[Example 1] The members used are described below.

【0015】半導体素子 :素子サイズは4.0×4.
0mm、接続端子サイズは80×80μm、ピッチは1
30μmとした。
Semiconductor device: The device size is 4.0 × 4.
0 mm, connection terminal size 80 × 80 μm, pitch 1
It was 30 μm.

【0016】回路基板 :基板材料にガラス、接続端
子及び配線材料としてITOを使用した。接続端子のサ
イズ、ピッチは半導体素子と同一にした。
Circuit board: Glass was used as a board material, and ITO was used as a connection terminal and a wiring material. The size and pitch of the connection terminals were the same as those of the semiconductor element.

【0017】素子と基板の配線は4端子法で接続抵抗を
測定できるように設計した。半導体素子の接続端子部に
インジウムバンプをスパッタ、フォトリソ加工により形
成した。インジウムバンプの高さは平均29μmであっ
た。ひとつの素子のなかでバンプ高さの最大値は36μ
m、最小値は25μmであった。回路基板の接続端子部
に厚さ30μmの未硬化のエポキシ系樹脂フィルムを貼
り付けた。次に、素子と基板とを位置合わせしたのち、
摂氏200度、荷重50MPaで30秒加熱圧着した。
これにより、2mΩ以下のバンプ接続抵抗が得られた。
The wiring between the element and the substrate was designed so that the connection resistance could be measured by the 4-terminal method. Indium bumps were formed on the connection terminals of the semiconductor element by sputtering and photolithography. The height of the indium bumps was 29 μm on average. The maximum bump height is 36μ in one device.
m, and the minimum value was 25 μm. An uncured epoxy resin film having a thickness of 30 μm was attached to the connection terminal portion of the circuit board. Next, after aligning the element and the substrate,
It was thermocompression bonded for 30 seconds at a temperature of 200 ° C. and a load of 50 MPa.
As a result, a bump connection resistance of 2 mΩ or less was obtained.

【0018】[実施例2]部材は実施例1と同じものを
使用した。半導体素子の接続端子部に金をスパッタ、フ
ォトリソ工法で形成した。次にこの金膜上の一部分に光
硬化性低弾性樹脂のフォトリソ工法で形成した。次に接
続端子部以外をレジストで保護して低弾性樹脂の表面に
のみ無電解ニッケルめっき皮膜を形成した。バンプ全体
の高さは、平均23μmであった。ひとつの素子のなか
でバンプ高さの最大値は28μm、最小値は21μmで
あった。回路基板の接続端子部に厚さ約25μmで未硬
化の光硬化性系樹脂を塗布した。次に、素子と基板とを
位置合わせしたのち、基板の裏面から20mW/cm2
(波長365nm)の強度の紫外線を照射しながら、荷
重100MPaで60秒圧着した。これにより、10m
Ω以下のバンプ接続抵抗が得られた。
[Example 2] The same members as in Example 1 were used. Gold was formed on the connection terminal portion of the semiconductor element by a sputtering or photolithography method. Next, a photo-curable low-elasticity resin was formed on a part of the gold film by a photolithography method. Next, a portion other than the connection terminal portion was protected with a resist to form an electroless nickel plating film only on the surface of the low elasticity resin. The height of the entire bump was 23 μm on average. The maximum value of the bump height was 28 μm and the minimum value was 21 μm in one element. An uncured photocurable resin having a thickness of about 25 μm was applied to the connection terminal portion of the circuit board. Next, after aligning the element and the substrate, from the back surface of the substrate, 20 mW / cm 2
While irradiating the ultraviolet ray having the intensity of (wavelength 365 nm), the pressure was applied for 60 seconds under a load of 100 MPa. With this, 10m
A bump connection resistance of Ω or less was obtained.

【0019】[実施例3]部材は実施例1と同じものを
使用した。半導体素子の接続端子部にウレタン系樹脂を
バインダとする銀ペーストを印刷した。こてを摂氏10
0度で1時間乾燥させた。バンプ全体の高さは、平均3
6μmであった。一つの素子のなかでバンプ高さの最大
値は45μm、最小値は23μmであった。一方、回路
基板の接続端子部に厚さ45μmの未硬化のエポキシ系
樹脂フィルムを貼り付けた。次に、素子と基板とを位置
合わせしたのち、摂氏100度、荷重40MPaで30
秒加熱圧着した。これにより、2mΩ以下のバンプ接続
抵抗が得られた。
[Example 3] The same members as in Example 1 were used. Silver paste containing urethane resin as a binder was printed on the connection terminals of the semiconductor element. 10 degrees Celsius
It was dried at 0 degrees for 1 hour. Average height of bumps is 3
It was 6 μm. The maximum value of the bump height in one device was 45 μm, and the minimum value was 23 μm. On the other hand, an uncured epoxy resin film having a thickness of 45 μm was attached to the connection terminal portion of the circuit board. Next, after aligning the element and the substrate, 30 degrees Celsius and a load of 40 MPa are used.
It was heated and pressed for seconds. As a result, a bump connection resistance of 2 mΩ or less was obtained.

【0020】[実施例4]部材は実施例1と同じものを
使用した。半導体素子の接続端子部にカンファースルホ
ン酸でドープしたポリアニリン膜を、フォトリソ工法で
形成した。バンプ全体の高さは、平均21μmであっ
た。一つの素子のなかでバンプ高さの最大値は26μ
m、最小値は19μmであった。回路基板の接続端子部
に厚さ約20μmで未硬化の光硬化性系樹脂を塗布し
た。次に、素子と基板とを位置合わせしたのち、基板の
裏面から20mW/cm2(波長365nm)の強度の
紫外線を照射しながら、荷重20MPaで60秒圧着し
た。これにより、10mΩ以下のバンプ接続抵抗が得ら
れた。
[Example 4] The same members as in Example 1 were used. A polyaniline film doped with camphorsulfonic acid was formed on the connection terminal portion of the semiconductor element by a photolithography method. The height of the entire bump was 21 μm on average. The maximum bump height is 26μ in one device.
m, and the minimum value was 19 μm. An uncured photocurable resin having a thickness of about 20 μm was applied to the connection terminal portion of the circuit board. Next, after aligning the element and the substrate, pressure was applied for 60 seconds under a load of 20 MPa while irradiating ultraviolet rays having an intensity of 20 mW / cm 2 (wavelength 365 nm) from the back surface of the substrate. As a result, a bump connection resistance of 10 mΩ or less was obtained.

【0021】[0021]

【発明の効果】本発明によれば、半導体素子を回路基板
上に直接実装するベアチップ実装方法において従来法で
の問題点を解決することが可能であり、高密度、高歩留
り、短工程で素子を搭載する方法を提供することができ
る。
According to the present invention, it is possible to solve the problems of the conventional method in a bare chip mounting method for directly mounting a semiconductor element on a circuit board, and to achieve high density, high yield, and short steps of the element. Can be provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来法のワイヤバンピング法を示す説明図。FIG. 1 is an explanatory view showing a conventional wire bumping method.

【図2】従来法のはんだバンプ法を示す説明図。FIG. 2 is an explanatory diagram showing a conventional solder bump method.

【図3】従来法の異方性導電フィルム法を示す説明図。FIG. 3 is an explanatory view showing a conventional anisotropic conductive film method.

【図4】本発明の実装方法を示す説明図。FIG. 4 is an explanatory diagram showing a mounting method of the present invention.

【図5】本発明のバンプ構造を示す説明図。FIG. 5 is an explanatory diagram showing a bump structure of the present invention.

【図6】本発明のバンプ接続構造を示す説明図。FIG. 6 is an explanatory view showing a bump connection structure of the present invention.

【符号の説明】[Explanation of symbols]

1…半導体素子、 2…回路基板、 4…回路基板の接続端子、 9…容易に塑性変形できる導電材料で形成したバンプ、 10…未硬化の熱硬化性樹脂または光硬化性樹脂。 DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Circuit board, 4 ... Connection terminal of circuit board, 9 ... Bump formed by the conductive material which can be easily plastically deformed, 10 ... Unhardened thermosetting resin or photocurable resin.

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】接続端子部に容易に塑性変形する導電材料
でバンプを形成した半導体素子と回路基板とを、未硬化
の熱硬化性樹脂または光硬化樹脂を介在させて加熱圧
着、または紫外線照射併用圧着により接続することを特
徴とする半導体素子の実装方法。
1. A semiconductor element having a bump formed with a conductive material which is easily plastically deformed on a connection terminal portion and a circuit board are subjected to thermocompression bonding or ultraviolet irradiation with an uncured thermosetting resin or photocurable resin interposed. A method for mounting a semiconductor element, characterized in that they are connected by joint crimping.
【請求項2】上記導電材料がインジウム、鉛から選ばれ
た金属である請求項1に記載の半導体素子の実装方法。
2. The method for mounting a semiconductor element according to claim 1, wherein the conductive material is a metal selected from indium and lead.
【請求項3】上記導電材料がプラスチックに金属皮膜を
形成した構造を有する請求項1に記載の半導体素子の実
装方法。
3. The method for mounting a semiconductor element according to claim 1, wherein the conductive material has a structure in which a metal film is formed on plastic.
【請求項4】上記導電材料が熱可塑性樹脂をバインダと
する導電性接着剤である請求項1に記載の半導体素子の
実装方法。
4. The method for mounting a semiconductor element according to claim 1, wherein the conductive material is a conductive adhesive containing a thermoplastic resin as a binder.
【請求項5】上記導電材料が導電性ポリマである請求項
1に記載の半導体素子の実装方法。
5. The method for mounting a semiconductor element according to claim 1, wherein the conductive material is a conductive polymer.
【請求項6】接続端子部に容易に塑性変形する導電材料
でバンプを形成した半導体素子を回路基板に光硬化樹脂
または熱硬化性樹脂で接合したことを特徴とする回路実
装基板。
6. A circuit mounting board, wherein a semiconductor element having bumps formed of a conductive material that is easily plastically deformed on a connection terminal portion is bonded to a circuit board with a photocurable resin or a thermosetting resin.
JP8106788A 1996-04-26 1996-04-26 Semiconductor device mounting method and circuit mounting board used therefor Pending JPH09293759A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8106788A JPH09293759A (en) 1996-04-26 1996-04-26 Semiconductor device mounting method and circuit mounting board used therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8106788A JPH09293759A (en) 1996-04-26 1996-04-26 Semiconductor device mounting method and circuit mounting board used therefor

Publications (1)

Publication Number Publication Date
JPH09293759A true JPH09293759A (en) 1997-11-11

Family

ID=14442646

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8106788A Pending JPH09293759A (en) 1996-04-26 1996-04-26 Semiconductor device mounting method and circuit mounting board used therefor

Country Status (1)

Country Link
JP (1) JPH09293759A (en)

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