JPH09283659A - Ic package board and manufacture of ic package using the same - Google Patents
Ic package board and manufacture of ic package using the sameInfo
- Publication number
- JPH09283659A JPH09283659A JP8091130A JP9113096A JPH09283659A JP H09283659 A JPH09283659 A JP H09283659A JP 8091130 A JP8091130 A JP 8091130A JP 9113096 A JP9113096 A JP 9113096A JP H09283659 A JPH09283659 A JP H09283659A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- green sheet
- package
- resin
- dam
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明はIC(集積回路)パ
ッケージ用基板およびこれを用いたICパッケージの製
造方法に関する。さらに詳しく言えば、樹脂封止に適し
たICパッケージ用基板およびこれを用いた樹脂封止I
Cパッケージの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC (integrated circuit) package substrate and a method for manufacturing an IC package using the same. More specifically, an IC package substrate suitable for resin encapsulation and resin encapsulation using the same I
The present invention relates to a method of manufacturing a C package.
【0002】[0002]
【従来の技術】半導体回路の高度集積化技術の進展に伴
ない、電子機器の小型化、高性能化に拍車がかかってい
る。このため、ICパッケージについても、ICベアチ
ップの小型化に対応した小型化、高機能化が強く要望さ
れている。従来、ICパッケージの製造は、Auあるい
はAl材料を用いたワイヤーボンディング(W/Β)技
法により、ICベアチップを実装用基板あるいはリード
フレームに実装した後、ICを外部環境から保護するた
めの封止工程を経て行なわれている。2. Description of the Related Art With the progress of advanced integration technology of semiconductor circuits, miniaturization and high performance of electronic devices are being spurred. For this reason, there is a strong demand for miniaturization and higher functionality of the IC package corresponding to the miniaturization of the IC bare chip. Conventionally, an IC package has been manufactured by mounting a bare IC chip on a mounting substrate or a lead frame by a wire bonding (W / B) technique using an Au or Al material, and then sealing the IC to protect it from the external environment. It goes through the process.
【0003】ICの封止には、乾燥窒素ガスのような不
活性ガス雰囲気下で、基板にメタルキャップを抵抗溶接
したり、セラミックキャップをロウ付けして外部雰囲気
から遮断する機密封止法と、実装されたチップを樹脂で
封じる非機密封止法がある。機密封止法は耐環境性・耐
熱性に優れているが製造にコストがかかる。このため、
一般にはより安価な樹脂封止法が採られることが多く、
封止用樹脂の性能向上に伴ない樹脂封止法が適用される
製品用途も拡大している。The IC is sealed by a confidential sealing method in which a metal cap is resistance-welded to the substrate in an inert gas atmosphere such as dry nitrogen gas, or a ceramic cap is brazed to shield from the external atmosphere. , There is a non-secret sealing method that seals the mounted chip with resin. The confidential sealing method is excellent in environment resistance and heat resistance, but it is costly to manufacture. For this reason,
Generally, a cheaper resin sealing method is often adopted,
As the performance of the encapsulating resin improves, the product applications to which the resin encapsulation method is applied are expanding.
【0004】典型的な樹脂封止法にはトランスファモー
ルド法とディスペンサーによるコーティング法がある。
トランスファモールド法は、図1に断面図を用いて模式
的に示すように、基板(1) 上にICベアチップ(2) を導
電性接着剤(3) 等によって接着し、ICチップ上の回路
と基板表面のIC実装用回路パターン(4) とを導線(5)
を介して接続した後、基板上に金型(6) を圧接し、基板
と金型との間に形成されるキャビティ(7) 内に、加熱溶
融した硬化性樹脂をランナ(8) を通して矢印方向に高圧
移送する方法である。冷却後、金型を除去することによ
り、キャビティの形状に応じた樹脂封止層を得ることが
できる。なお、図では1個の基板のみを示しているが、
実際には、複数個の基板領域が形成された原基板に対し
て、各領域に対応する凹部を有する金型を用いてモール
ディングが行なわれる。Typical resin sealing methods include a transfer molding method and a coating method using a dispenser.
In the transfer molding method, the IC bare chip (2) is bonded onto the substrate (1) with a conductive adhesive (3), etc., as shown in the cross-sectional view of FIG. Conductor (5) with the circuit pattern (4) for IC mounting on the board surface
After connecting via the mold, the mold (6) is pressed onto the substrate, and the heat-curable curable resin is passed through the runner (8) in the cavity (7) formed between the substrate and the mold. It is a method of high-pressure transfer in the direction. After cooling, the mold is removed to obtain a resin sealing layer corresponding to the shape of the cavity. Although only one substrate is shown in the figure,
Actually, molding is performed on an original substrate on which a plurality of substrate regions are formed by using a mold having recesses corresponding to the respective regions.
【0005】トランスファモールド法では、金型の設計
により任意の形状に封止を行なうことが可能であり、基
板上での封止高さ(h)を均一に設定することができ
る。しかし、金型が必要であるため費用面に問題があ
り、また、ICの小型化に応じた最小寸法の金型を設計
することが難しい。さらに、これらの点から小口生産に
は不向きであるという欠点がある。また、樹脂の高圧移
送に耐えるように金型を高い圧力で圧接する必要がある
ため、薄いセラミック基板への適用が困難である。In the transfer molding method, it is possible to perform sealing in an arbitrary shape by designing the mold, and it is possible to set the sealing height (h) on the substrate uniformly. However, since a mold is required, there is a cost problem, and it is difficult to design a mold having a minimum size according to the miniaturization of IC. Further, from these points, there is a drawback that it is not suitable for small-lot production. Further, since it is necessary to press the mold with a high pressure so as to withstand the high-pressure transfer of resin, it is difficult to apply it to a thin ceramic substrate.
【0006】ディスペンサーによるコーティング法は、
溶融した液状の封止樹脂をディスペンサーを用いてIC
ベアチップ上に流し込む方法である。この方法は、金型
を必要とせず費用面で有利である。また、小口生産に適
している。しかし、図2に示す通り、封止樹脂が基板面
上に広く流れICチップ上での封止樹脂の厚みを十分に
確保できない可能性があり、また封止層(9) の高さが縁
部に向けて減少するため、チップの封止が不十分になる
可能性がある。樹脂の粘度を高くすれば封止高さを均一
に高くすることも可能であるが、高粘度樹脂では基板と
の密着性に問題がある。回路パターンを囲む形状に枠(1
0)を印刷し、これによって封止形状を整える方法も知ら
れているが(図3)、この方法では枠の厚みは高々10
0μm(0.1mm)程度であり、樹脂の種類や量によっ
ては枠を越えて樹脂が流れてしまうなど、確実性に欠け
るという問題がある。また、封止高さ/封止面積の比率
が樹脂の表面張力や硬化速度等により制限されるため、
実装基板の小型化に対応することが困難である。The coating method using a dispenser is
Melt liquid sealing resin using a dispenser
It is a method of pouring on a bare chip. This method does not require a mold and is advantageous in terms of cost. Also suitable for small lot production. However, as shown in FIG. 2, the sealing resin may spread widely on the substrate surface, and the thickness of the sealing resin on the IC chip may not be sufficiently secured, and the height of the sealing layer (9) may increase. Since it decreases toward the part, the sealing of the chip may be insufficient. It is possible to increase the sealing height uniformly by increasing the viscosity of the resin, but the high-viscosity resin has a problem in the adhesion to the substrate. A frame (1
A method of printing (0) and adjusting the sealing shape by this is also known (FIG. 3), but in this method, the thickness of the frame is at most 10
The thickness is about 0 μm (0.1 mm), and there is a problem that the resin flows beyond the frame depending on the type and amount of the resin and lacks certainty. Further, since the ratio of the sealing height / sealing area is limited by the surface tension of the resin, the curing speed, etc.,
It is difficult to respond to miniaturization of the mounting board.
【0007】[0007]
【発明が解決しようとする課題】本発明は、初期コスト
が安く小口生産に適しているディスペンサーによる樹脂
封止技術において、均一で十分な厚みを有し、かつ基板
との密着性にも優れた封止樹脂層を確実に形成するため
の改良方法を提供することを目的とする。DISCLOSURE OF THE INVENTION The present invention has a uniform and sufficient thickness and excellent adhesiveness to a substrate in the resin sealing technique using a dispenser, which has a low initial cost and is suitable for small-lot production. It is an object of the present invention to provide an improved method for surely forming a sealing resin layer.
【0008】[0008]
【課題を解決するための手段】本発明者らは以前に「セ
ラミック金属複合基板および該基板用絶縁性保護膜の形
成方法」を発明している(特公平7-50820 号)。この発
明はガラスもしくはガラスと無機フィラーと有機結合剤
とからなるセラミックグリーンシートをセラミック回路
基板に転写し、焼成することで絶縁保護膜を形成するも
のであるが、かかるグリーンシートを用いて形成される
絶緑膜を封止樹脂用のダムとして用いることにより、任
意の封止高さで確実な樹脂封止が可能となることを見出
し本発明を完成するに至った。The present inventors have previously invented "a ceramic metal composite substrate and a method for forming an insulating protective film for the substrate" (Japanese Patent Publication No. 7-50820). According to the present invention, a ceramic green sheet made of glass or glass, an inorganic filler and an organic binder is transferred to a ceramic circuit board and fired to form an insulating protective film. The present invention has been completed by finding that it is possible to perform reliable resin encapsulation at an arbitrary encapsulation height by using an insulating film as a dam for encapsulation resin.
【0009】すなわち、本発明は、以下のICパッケー
ジ用基板を提供する。 (1) IC実装用回路パターンを形成した基板上に、
前記パターンが囲まれる枠状に形成したセラミックグリ
ーンシートを位置合わせして転写、焼成して、基板上に
封止樹脂用ダムを形成してなることを特徴とするICパ
ッケージ用基板。 (2) セラミックグリーンシートが、主要成分として
のガラスを含む無機材料と有機バインダーとを含有する
ものである請求項1に記載のICパッケージ用基板。That is, the present invention provides the following IC package substrate. (1) On a substrate on which an IC mounting circuit pattern is formed,
A substrate for an IC package, characterized in that a ceramic green sheet formed in a frame shape surrounding the pattern is aligned, transferred, and fired to form a dam for a sealing resin on the substrate. (2) The substrate for an IC package according to claim 1, wherein the ceramic green sheet contains an inorganic material containing glass as a main component and an organic binder.
【0010】また、本発明は、前記1および2のICパ
ッケージ用基板を用いた、以下のICパッケージの製造
方法を提供する。 (3) IC実装用回路パターンを形成した基板上に、
前記パターンが囲まれる枠状に形成したセラミックグリ
ーンシートを位置合わせして転写、焼成して基板上にダ
ムを形成した後、ICを実装し、しかる後、前記ダムで
囲まれた領域内に硬化性樹脂を注入して実装したICを
封止することを特徴とするICパッケージの製造方法。The present invention also provides the following IC package manufacturing method using the IC package substrates 1 and 2 described above. (3) On a substrate on which an IC mounting circuit pattern is formed,
A frame-shaped ceramic green sheet that surrounds the pattern is aligned, transferred, and fired to form a dam on the substrate, then the IC is mounted, and then cured in the region surrounded by the dam. A method for manufacturing an IC package, which comprises injecting a conductive resin to seal the mounted IC.
【0011】さらに、本発明は、前記3の方法を集合基
板に適用した、以下のICパッケージの製造方法を提供
する。 (4) 合成樹脂フィルム上に格子状に形成したセラミ
ックグリーンシートを、複数のIC実装用領域を有する
基板上に、前記格子の各枠により前記領域がそれぞれ囲
まれるように位置合わせし、転写、焼成して基板上に前
記各領域を囲むダムを形成した後、各領域においてIC
の実装と硬化性樹脂の注入を行ない、領域ごとに切り分
けて個別のパッケージとすることを特徴とするICパッ
ケージの製造方法。 (5) 前記格子状に形成したセラミックグリーンシー
トに小孔径のガイド孔を設けておき、グリーンシートの
転写に際し、前記基板をガイドピンを立てた治具に固定
し、前記ガイド孔に前記ガイドピンを挿入することによ
り位置合わせを行なう前記4に記載のICパッケージの
製造方法。Furthermore, the present invention provides the following IC package manufacturing method in which the above-mentioned method 3 is applied to an aggregate substrate. (4) A ceramic green sheet formed in a grid pattern on a synthetic resin film is aligned on a substrate having a plurality of IC mounting areas so that each area is surrounded by each frame of the grid, and transferred. After firing to form a dam on the substrate surrounding each of the regions, the IC is formed in each region.
The method for manufacturing an IC package is characterized in that the mounting and the injection of a curable resin are performed, and each region is cut into individual packages. (5) A guide hole having a small hole diameter is provided in the ceramic green sheet formed in the lattice shape, and at the time of transferring the green sheet, the substrate is fixed to a jig having a guide pin, and the guide pin is inserted into the guide hole. 5. The method for manufacturing an IC package as described in 4 above, wherein the alignment is performed by inserting.
【0012】以下、本発明を構成する工程および要素に
ついて分説する。 [ICパッケージ用基板]本発明によるICパッケージ
用基板は、図4(a) 〜(b) および図5に概略を示す通
り、IC実装用回路パターン(4) が形成されたセラミッ
ク基板(1) 上に、回路パターンを囲むようにセラミック
製の枠(13)を転写法により形成したものである。The steps and elements constituting the present invention will be described below. [IC Package Substrate] The IC package substrate according to the present invention is a ceramic substrate (1) on which an IC mounting circuit pattern (4) is formed, as schematically shown in FIGS. 4 (a) to (b) and FIG. A ceramic frame (13) is formed on the upper part by a transfer method so as to surround the circuit pattern.
【0013】(a) 原基板 基板にはセラミック焼成基板が用いられる。材質は特に
限定されない。例えば、アルミナ基板、ムライト基板、
ガラスセラミックス基板、窒化アルミ基板等が挙げられ
る。単層基板でも多層基板でもよい。基板の厚みや大き
さに特に限定はない。IC実装用回路パターン(4) は、
例えば、基板表面に設けられた複数の電極であり、図4
(a) に示すように、基板を貫くスルーホール(11)やビア
ホール(図にはスルーホールの例のみを示してある。)
を介して裏面の端子(12)に接続されリードアウトする構
成とすることが好ましいが、基板表面の回路パターンか
ら基板表面に沿ってリード部分が延びる基板(図7参
照)でも本発明は適用可能である。なお、IC実装用回
路パターンの形成やスルーホール等の形成は既知の方法
にしたがって行なわれる。(A) Original Substrate A ceramic fired substrate is used as the substrate. The material is not particularly limited. For example, alumina substrate, mullite substrate,
Examples thereof include glass ceramic substrates and aluminum nitride substrates. It may be a single layer substrate or a multilayer substrate. There is no particular limitation on the thickness or size of the substrate. IC mounting circuit pattern (4)
For example, as shown in FIG.
As shown in (a), through holes (11) and via holes that penetrate the substrate (only examples of through holes are shown in the figure.)
It is preferable that the lead-out is connected to the terminal (12) on the back surface via the lead wire, but the present invention is also applicable to a board (see FIG. 7) in which lead portions extend from the circuit pattern on the board surface along the board surface. Is. The IC mounting circuit pattern and the through holes are formed according to a known method.
【0014】(b) セラミックグリーンシート (b-1) グリーンシートの調製 本発明で用いるセラミックグリーンシートは、上記の原
基板に対する接着性がよく、焼成により原基板に固着、
すなわち一体化し得るものであればよいが、特公平 7-5
0820号で提案したようなガラス系のセラミックが好まし
い。(B) Ceramic Green Sheet (b-1) Preparation of Green Sheet The ceramic green sheet used in the present invention has good adhesiveness to the above-mentioned original substrate and is fixed to the original substrate by firing.
In other words, as long as they can be integrated, it is possible
Glass-based ceramics as proposed in 0820 are preferred.
【0015】ガラスセラミックのグリーンシートは、ガ
ラス材料粉、有機バインダー、および所望により添加さ
れる無機フィラーを溶媒等と混合してなるスラリーをシ
ート状に成形することにより得られる。ガラス材料の例
としては、硼珪酸鉛(PbO・B2 O3 ・SiO2 )
系、硼珪酸亜鉛系、硼珪酸アルカリ土類金属系等のガラ
スが挙げられる。粒度等は既知の例に従えばよく、例え
ば、1〜10μm程度のものが好適に用いられる。有機
バインダーの例としては、メタクリル酸メチル、メタク
リル酸ブチル、アクリル酸メチル、アクリル酸等からな
るアクリル系バインダー、ポリビニルブチラール等が挙
げられる。その配合量は前記のガラス成分に対して3〜
30重量%程度まで、好ましくは20重量%程度までで
ある。3重量%未満ではバインダーとしての効果が十分
に発揮されない。30重量%を超えて用いても効果の改
善はなく、却って焼成時の体積収縮が大きくなるなどの
問題が生じる。The glass-ceramic green sheet is obtained by forming a slurry obtained by mixing a glass material powder, an organic binder, and an inorganic filler optionally added with a solvent into a sheet shape. An example of the glass material is lead borosilicate (PbO · B 2 O 3 · SiO 2 ).
Examples of the glass include borosilicate glass, zinc borosilicate glass, and alkaline earth metal borosilicate glass. The particle size and the like may be in accordance with a known example, and for example, a particle size of about 1 to 10 μm is preferably used. Examples of organic binders include acrylic binders made of methyl methacrylate, butyl methacrylate, methyl acrylate, acrylic acid, polyvinyl butyral, and the like. The blending amount is 3 to the above glass component.
It is up to about 30% by weight, preferably up to about 20% by weight. If it is less than 3% by weight, the effect as a binder is not sufficiently exhibited. Even if it is used in an amount of more than 30% by weight, the effect is not improved, and on the contrary, there arises a problem that volume shrinkage during firing becomes large.
【0016】所望により無機フィラーを添加し、流動性
を調節する。無機フィラーとしては、アルミナ、ムライ
ト、ジルコニア等が用いられる。その配合量は前記のガ
ラス成分に対して60重量%程度まで、好ましくは20
重量%程度までである。過剰に用いると焼成時の焼結性
が低くなり、IC組立作業時に欠けなどが発生しやすく
なり、不具合の原因となってしまう。If desired, an inorganic filler is added to adjust the fluidity. As the inorganic filler, alumina, mullite, zirconia, etc. are used. The compounding amount is up to about 60% by weight, preferably 20%, with respect to the above glass component.
Up to about wt%. If used excessively, the sinterability at the time of firing becomes low, and chips or the like are likely to occur during the IC assembling work, resulting in problems.
【0017】粒度をコントロールした上記ガラス成分お
よび所望により添加される無機フィラーならびに有機バ
インダーを、有機溶剤(例えば、トルエン、メチルエチ
ルケトン(MEK)、イソプロパノール等)、分散剤
(例えば、ポリエチレングリコール、脂肪酸エステル
等)、可塑剤(例えば、ジブチルフタレート、ポリエチ
レングリコール等)と良く混合し、低粘度のスラリーと
する。スラリー調製段階での粘度は、数百cps程度で
よい。次いで、得られたスラリーを減圧下に置いて溶剤
除去と粘度調整をも兼ねた脱泡処理を行ない、スラリー
粘度を数千〜数万cpsに調整する。The above-mentioned glass component of which the particle size is controlled, and optionally an inorganic filler and an organic binder, are mixed with an organic solvent (eg, toluene, methyl ethyl ketone (MEK), isopropanol, etc.), a dispersant (eg, polyethylene glycol, fatty acid ester, etc. ), And a plasticizer (for example, dibutyl phthalate, polyethylene glycol, etc.) are mixed well to form a low-viscosity slurry. The viscosity at the slurry preparation stage may be about several hundred cps. Next, the obtained slurry is placed under reduced pressure to perform defoaming treatment that also serves as solvent removal and viscosity adjustment, and the slurry viscosity is adjusted to several thousand to several tens of thousands cps.
【0018】脱泡し高粘度化したスラリーは、泡を巻き
込まないように注意して、好ましくは合成樹脂フィルム
上に例えばドクターブレード等を用いて塗布し、所望の
厚みのシートとする。合成樹脂フィルムの例としては、
安価なポリエチレンテレフタレート(PET)、ポリフ
ェニレンサルファイド(PPS)等が挙げられる。転写
を容易にするために表面にシリコン膜を焼付けたPET
が好ましい。フィルムの膜厚は後工程での処理の際に十
分な強度を有するように50〜200μm程度とするこ
とが好ましい。セラミックシートの厚さは形成しようと
するダムの高さに依存するが、通常は、0.04〜2mm程
度である。The defoamed and highly viscous slurry is applied onto a synthetic resin film, preferably with a doctor blade, taking care not to entrap bubbles, to obtain a sheet having a desired thickness. Examples of synthetic resin films include
Examples include inexpensive polyethylene terephthalate (PET), polyphenylene sulfide (PPS), and the like. PET with a silicon film baked on the surface to facilitate transfer
Is preferred. The thickness of the film is preferably about 50 to 200 μm so as to have sufficient strength in the treatment in the subsequent step. The thickness of the ceramic sheet depends on the height of the dam to be formed, but is usually about 0.04 to 2 mm.
【0019】(b-2) グリーンシートの成形 得られたシートは所定の形状、具体的には、前記(a) の
原基板上のIC実装領域に相当する大きさまたはそれ以
上の大きさで、前記領域を囲み得る枠状の形に成形す
る。通常は、一辺が5〜50mm程度の矩形状の窓を開
ける。窓開け方法の例としては、カッターによるカッテ
ィング、金型によるパンチング等が挙げられる。合成樹
脂フィルム上にグリーンシートを形成した状態のまま
で、フィルムごとカッティングないしパンチングを行な
ってもよいし、フィルムからグリーンシートを剥離させ
た状態でカッティングやパンチングを行なってもよい。
なお、シートの枠部分の幅(図4あるいは図5に示すダ
ムの幅)は、基板の大きさや基板上の回路の配置による
が、通常は0.5 〜10mm程度である。0.5 mm未満で
は十分な強度が得られず、転写等の処理に際して変形の
おそれがある。10mmを超える幅としても効果に顕著
な改善はない。(B-2) Molding of green sheet The obtained sheet has a predetermined shape, specifically, a size corresponding to the IC mounting area on the original substrate of (a) or a size larger than that. , A frame-like shape that can surround the area. Usually, a rectangular window having one side of 5 to 50 mm is opened. Examples of the window opening method include cutting with a cutter and punching with a mold. Cutting or punching may be performed together with the film while the green sheet is still formed on the synthetic resin film, or cutting or punching may be performed with the green sheet peeled from the film.
The width of the frame portion of the sheet (the width of the dam shown in FIG. 4 or FIG. 5) is usually about 0.5 to 10 mm, though it depends on the size of the substrate and the arrangement of the circuits on the substrate. If it is less than 0.5 mm, sufficient strength cannot be obtained, and there is a risk of deformation during processing such as transfer. Even if the width exceeds 10 mm, the effect is not significantly improved.
【0020】(b-3) 転写工程 次に、セラミックグリーンシートを、前記窓を通してI
C実装領域が表面に露出するように基板上に載置し、熱
圧着あるいは接着剤等により固定する。熱圧着は、例え
ば、30〜150℃の温度で10〜200 kg/cm2 程度
の圧力をかけることにより行なわれる。接着剤の例とし
ては、グリーンシートに用いられているバインダーやグ
リーンシート組成のスラリー等が挙げられる。(B-3) Transfer Step Next, the ceramic green sheet is passed through the window to I
It is placed on the substrate so that the C mounting area is exposed on the surface and fixed by thermocompression bonding or an adhesive. The thermocompression bonding is performed, for example, by applying a pressure of about 10 to 200 kg / cm 2 at a temperature of 30 to 150 ° C. Examples of the adhesive include binders used for green sheets, slurries having a green sheet composition, and the like.
【0021】(b-4) 焼成工程 シートを固定したセラミック基板は、酸化雰囲気下(通
常は空気雰囲気下)で400〜500℃程度に加熱して
バインダーを除去し、次いで、550℃〜850℃で焼
成する。脱バインダーと焼成とを合わせた加熱時間は3
0分〜3時間程度であり、うち焼成時間は5〜20分程
度である。上記の各工程を経ることにより、基板(1) の
IC実装回路パターン(4) を囲んでセラミック製のダム
(13)が、基板の特性に影響を与えることなく形成された
ICパッケージ用基板(15)を得ることができる(図5
(図4(b) に対応))。(B-4) Firing step The ceramic substrate on which the sheet is fixed is heated in an oxidizing atmosphere (usually in an air atmosphere) to about 400 to 500 ° C. to remove the binder, and then 550 ° C. to 850 ° C. Bake at. The total heating time for debinding and firing is 3
It is about 0 minutes to 3 hours, and the firing time is about 5 to 20 minutes. By going through each of the above steps, a ceramic dam surrounding the IC mounting circuit pattern (4) on the substrate (1)
It is possible to obtain the IC package substrate (15) in which (13) is formed without affecting the characteristics of the substrate (FIG. 5).
(Corresponding to Figure 4 (b)).
【0022】[ICパッケージの製造方法]上記のよう
にして製造したICパッケージ用基板に、ICを実装
し、さらに樹脂封止を行なうことにより封止性に優れた
ICパッケージを製造することができる(図4(b) 〜
(d) )。[Method of Manufacturing IC Package] By mounting an IC on the IC package substrate manufactured as described above and further sealing with a resin, an IC package having excellent sealing performance can be manufactured. (Fig. 4 (b) ~
(d)).
【0023】ICの実装は、既知の方法にしたがって行
なう。具体的には、ICベアチップ(2) を導電性接着剤
(3) により基板(1) に接着し、導線(5) によってICチ
ップ上の回路を基板上のIC実装用回路(4) に接続す
る。導電性接着剤の例としては、Ag系エポキシ樹脂等
が挙げられる。導線は、例えば、AuやAl等の導電性
・耐酸化性に優れた金属が用いられ、ワイヤボンディン
グ技法により接続される(図6(図4(c) に対応))。The IC is mounted according to a known method. Specifically, the IC bare chip (2) is made into a conductive adhesive.
It is adhered to the substrate (1) by (3), and the circuit on the IC chip is connected to the IC mounting circuit (4) on the substrate by the conducting wire (5). Examples of the conductive adhesive include Ag-based epoxy resin and the like. The conductive wire is made of, for example, a metal having excellent conductivity and oxidation resistance such as Au or Al, and is connected by a wire bonding technique (FIG. 6 (corresponding to FIG. 4 (c))).
【0024】IC実装後、基板(1) とダム(13)で囲まれ
た空間(14)に硬化性樹脂を流し込むことによりIC(2)
の封止を行なう。硬化性樹脂の例としては、エポキシ樹
脂、フェノール樹脂等が挙げられる。樹脂封止したIC
パッケージの断面形状を、図4(d) には裏面リードアウ
ト型のパッケージについて、図7には基板表面に金属リ
ード(4) を有するICパッケージについてそれぞれ模式
的に示す。After the IC is mounted, a curable resin is poured into the space (14) surrounded by the substrate (1) and the dam (13) so that the IC (2)
To seal. Examples of the curable resin include epoxy resin and phenol resin. IC sealed with resin
The cross-sectional shape of the package is schematically shown in FIG. 4 (d) for a backside lead-out type package and in FIG. 7 for an IC package having a metal lead (4) on the substrate surface.
【0025】[集合基板を用いたICパッケージの製造
方法]上に述べた本発明のICパッケージの製造方法を
集合基板に適用することにより、ICパッケージを効率
的に製造することができる。すなわち、図8(a) に示す
ように、1枚の基板(21)上に複数の回路パターン(22)を
形成する。これらの回路パターン(22)は、これまでの説
明で述べてきた個別の回路パターン(4) と全く同等なも
のであり、スルーホール等を介して基板裏面にリードア
ウトするものである。かかる集合基板は個別基板と同様
の材料を用い既知の技術にしたがい製造することができ
る。図8では説明の便宜上、3×3個の回路パターンを
有する例を示しているが、実際には、製品のサイズに応
じて多数の回路パターン領域を1枚の集合基板上に設け
ることができる。[IC Package Manufacturing Method Using Collective Substrate] By applying the IC package manufacturing method of the present invention described above to the collective substrate, the IC package can be efficiently manufactured. That is, as shown in FIG. 8A, a plurality of circuit patterns 22 are formed on one substrate 21. These circuit patterns (22) are exactly the same as the individual circuit patterns (4) described above, and are read out to the back surface of the substrate through through holes or the like. Such an aggregate substrate can be manufactured according to a known technique by using the same material as the individual substrate. Although FIG. 8 shows an example having 3 × 3 circuit patterns for convenience of description, in reality, a large number of circuit pattern regions can be provided on one aggregate substrate according to the size of the product. .
【0026】一方、上記基板よりも若干大きいグリーン
シート(23)を合成樹脂フィルム(24)上に形成し、回路パ
ターン(22)に対応する配置および大きさで窓(25)を、ま
た、グリーンシートの縁部に小孔(26)を複数穿ち開ける
(図8(b))。グリーンシートの製造方法、穿孔方法等は
前記と同様である。小孔の直径は2〜8mm程度が好ま
しく、後述のガイドピンを挿入した際に、回路パターン
(22)と窓(25)とが正確に対応するように配置する。On the other hand, a green sheet (23), which is slightly larger than the above substrate, is formed on the synthetic resin film (24), and a window (25) is arranged in a size and size corresponding to the circuit pattern (22), and a green sheet is also formed. A plurality of small holes (26) are punched in the edge of the sheet (Fig. 8 (b)). The green sheet manufacturing method, perforation method, etc. are the same as described above. The diameter of the small holes is preferably about 2 to 8 mm, and when the guide pin described below is inserted, the circuit pattern
Arrange so that (22) and window (25) correspond exactly.
【0027】次にグリーンシート(23)を合成樹脂フィル
ム(24)が上側に向くにように反転し、その窓部(25)が基
板の回路パターン(22)に重なるように載置する(図8
(c))。この際、基板(21)はガイドピン(28)を有する治具
(27)に固定し、グリーンシート(23)の縁部に設けた小孔
(26)にガイドピン(28)を通すことにより両者の位置合わ
せを行なう。かかる構成を取ることにより、ガイドピン
と小孔の配置によってグリーンシートと基板との位置合
わせが容易かつ正確に実現される。なお、図にはコの字
型の部材を2つ組み合わせた形状の治具を例として示し
ているが、基板を固定するに足るものであればその形状
は特に限定されない。しかる後、フィルムごとあるいは
フィルムから剥してグリーンシートを基板上に圧着ない
し接着し、治具を外し(必要に応じフィルムを剥離し)
た後、焼成を行なう。圧着ないし接着および焼成の手順
および条件は前記と同様である。冷却後、各回路パター
ン領域について、前記と同様にしてICの実装および硬
化樹脂の注入を行ない、しかる後、格子状のダムに沿っ
て基板を切り分けることにより図6と同様の(但し樹脂
封止されている。)個別基板を得ることができる。Next, the green sheet (23) is turned over so that the synthetic resin film (24) faces upward, and the window portion (25) is placed so as to overlap the circuit pattern (22) of the substrate (Fig. 8
(c)). At this time, the substrate (21) is a jig having a guide pin (28).
Small hole fixed to (27) and provided on the edge of the green sheet (23)
The guide pins (28) are passed through (26) to align them. With such a configuration, the alignment of the green sheet and the substrate can be easily and accurately realized by the arrangement of the guide pins and the small holes. Note that, although a jig having a shape in which two U-shaped members are combined is shown as an example in the drawing, the shape is not particularly limited as long as it is sufficient to fix the substrate. After that, peel off the film or from the film, press or bond the green sheet onto the substrate, and remove the jig (peeling the film if necessary)
After that, baking is performed. The procedures and conditions for pressure bonding, bonding and firing are the same as above. After cooling, the IC is mounted and the cured resin is injected into each circuit pattern area in the same manner as described above, and thereafter, the board is cut along the grid-shaped dams. It is possible to obtain an individual substrate.
【0028】[0028]
【実施例】実施例1 [セラミックグリーンシート]アルミナ10重量%(平
均粒度3.0 μm)と硼珪酸鉛系ガラス(平均粒度3.0μ
m)90重量%からなる無機材料100重量部に対して
アクリル系バインダ−(共栄社製KCl−08)10重
量部、可塑剤6重量部およびメチルエチルケトン(ME
K)35重量部をボールミルに仕込み、数時間混合させ
てスラリーを得た。このスラリーを真空脱泡機中で1万
cps程度に調整しドクターブレード法によってΡET
フィルム上に横48cmで乾燥厚み約500μmの連続
グリーンシートを調製した後、10×10cmのサイズ
に裁断した。 Example 1 [Ceramic green sheet] 10% by weight of alumina (average particle size 3.0 μm) and lead borosilicate glass (average particle size 3.0 μm)
m) 10 parts by weight of an acrylic binder (KCl-08 manufactured by Kyoeisha Co., Ltd.), 6 parts by weight of a plasticizer and 100 parts by weight of an inorganic material consisting of 90% by weight, and methyl ethyl ketone (ME).
K) 35 parts by weight were charged in a ball mill and mixed for several hours to obtain a slurry. This slurry was adjusted to about 10,000 cps in a vacuum defoaming machine, and ET was applied by the doctor blade method.
A continuous green sheet having a width of 48 cm and a dry thickness of about 500 μm was prepared on the film, and then cut into a size of 10 × 10 cm.
【0029】[基板]低温焼結基板(アルミナ50%、
ガラス50%)材料を用いて、縦8cm×横8cm×厚
み0.6 mmのIC実装用の集合基板を作製した。基板表
面には、厚膜印刷により形成した2個のIC電極からな
るIC実装用領域を25個設け、ビアホールを介してそ
れぞれ裏面にリードアウトした。[Substrate] Low temperature sintered substrate (50% alumina,
A glass (50%) material was used to fabricate a collective substrate of 8 cm long × 8 cm wide × 0.6 mm thick for IC mounting. On the front surface of the substrate, 25 IC mounting regions made up of two IC electrodes formed by thick film printing were provided, and each of them was read out to the back surface via a via hole.
【0030】[IC実装用基板の製造]前記基板のIC
実装領域に対応するように先に製造したグリーンシート
上にNC方式の穿孔機械で窓(9mm×9mm)を25
個開けた。なお、その際にグリーンシートの縁部に基板
との位置合わせ用に 2.4mmφガイド孔を4個穿ち開け
た。前記基板を 2.4mmφ高さ5mmのガイドピンを有
する図8に図示するような炭化タングステン(WC)製
治具に固定し、PETフィルム面を上に向けた前記グリ
ーンシートをガイドピンがガイド孔に挿入されるように
基板上に載置した。治具を取り外した後、この基板を温
度80℃、圧力150Kg/cm2 で熟圧着し、600
℃で30分、合計加熱時間27Ο分に調整されたベルト
炉に通路さぜてセラミックダムをIC実装基板に固着さ
せた。焼成固着後のダム高さは約300μmであった。[Manufacture of IC Mounting Substrate] IC of the Substrate
25 windows (9 mm x 9 mm) were made on the green sheet manufactured earlier by an NC punching machine so as to correspond to the mounting area.
I opened one. At that time, four 2.4 mmφ guide holes were formed at the edge of the green sheet for alignment with the substrate. The substrate is fixed to a tungsten carbide (WC) jig having a guide pin with a height of 2.4 mm and a height of 5 mm as shown in FIG. 8, and the green sheet with the PET film surface facing upward is guided by the guide pin into the guide hole. It was placed on the substrate so that it would be inserted. After removing the jig, the substrate was thermocompression-bonded at a temperature of 80 ° C. and a pressure of 150 Kg / cm 2 to 600
The ceramic dam was fixed to the IC mounting substrate by passing through a belt furnace adjusted to 30 ° C. for a total heating time of 27 Ω. The height of the dam after baking and fixing was about 300 μm.
【0031】この後ダイシンソーで基板に幅200μm
程度のブレーク溝を入れた。この基板に厚さ0.6 mmの
ΙCベアチップを導電性接着剤(日立化成(株)製EN
−4072)で接着させAuワイヤーボンデイングで基
板上の回路とIC電極とを接続させた。かくして実装を
完了したIC基板上、セラミックダムで囲まれた領域に
封止樹脂(日立化成(株)製KE6309)をディスペ
ンサーで流し込み125℃で4時間保持して硬化させ
た。After that, the width of the substrate is 200 μm with a die saw.
I made a break groove. A 0.6 mm thick ęC bare chip is attached to this substrate with a conductive adhesive (EN manufactured by Hitachi Chemical Co., Ltd.).
Then, the circuit on the substrate was connected to the IC electrode by Au wire bonding. On the thus mounted IC substrate, a sealing resin (KE6309 manufactured by Hitachi Chemical Co., Ltd.) was poured into a region surrounded by the ceramic dam with a dispenser and held at 125 ° C. for 4 hours to be cured.
【0032】前記ブレーク溝に沿って個別基板を切り分
けることにより、ベース基板厚み 0.6mm、ダム高さ
0.3mm、ダム幅 0.5mmの10mm×10mmの小型
ICパッケージを製造することができた。By cutting the individual substrate along the break groove, the thickness of the base substrate is 0.6 mm and the height of the dam is
It was possible to manufacture a small IC package of 0.3 mm and a dam width of 0.5 mm and a size of 10 mm × 10 mm.
【0033】実施例2 基板の材質を96%アルミナとしたほかは実施例1と同
様にしてIC実装用基板を調製した。実施例1と同様に
IC実装および樹脂封止を行ない、10mm×10mm
の小型ICパッケージを製造した。 Example 2 An IC mounting substrate was prepared in the same manner as in Example 1 except that the material of the substrate was 96% alumina. IC mounting and resin sealing are performed in the same manner as in Example 1, and 10 mm × 10 mm
Manufactured a small IC package.
【0034】比較例1 従来用いられている96%アルミナ製IC実装用基板上
にICを実装し、ディスペンサーを用いて封止樹脂を流
したところ、樹脂が基板上に広がり、パッケージ面の大
きさを1cm2 程度とすることは全く不可能であった。 Comparative Example 1 When an IC was mounted on a conventionally used 96% alumina IC mounting substrate and a sealing resin was poured using a dispenser, the resin spreads on the substrate and the size of the package surface is increased. It was completely impossible to set the value to about 1 cm 2 .
【0035】[0035]
【発明の効果】従来の印刷法(図3)では基板上に数百
μm程度の厚みの枠を形成しようとすると多数回の印刷
を繰り返す必要があるばかりでなく、印刷を重ねること
により枠印刷用ペーストの垂れなどがあって実際に使用
することは困難であったが、本発明の方法によれば、微
小な基板上に厚さ数百μm〜数mmのセラミック枠を容
易に形成することができるので、ほとんどすべてのIC
について確実な樹脂封止を行なうことができる。また、
従来のトランスファモールド法によれば金型の製造など
に多大な経費を必要としたが、本発明の方法は、セラミ
ックグリーンシートを転写して形成したダム内にディス
ペンサーにより樹脂を流し込むだけであるので、コスト
を大幅に減少することができるとともにかつ必要最小限
の大きさのパッケージを製造することが可能となった。
また、トランスファモールド法で必要であった高圧移送
のための特殊な装置および基板に高圧を負荷することに
対する特別な配慮等が不要である。According to the conventional printing method (FIG. 3), in order to form a frame having a thickness of about several hundreds of μm on the substrate, it is necessary not only to repeat the printing a large number of times but also to print the frame by overlapping the printing. Although it was difficult to actually use it due to the sagging of the paste for paste, etc., according to the method of the present invention, it is possible to easily form a ceramic frame having a thickness of several hundred μm to several mm on a minute substrate. Can do almost all ICs
With respect to the above, reliable resin sealing can be performed. Also,
According to the conventional transfer molding method, a large amount of cost was required for manufacturing the mold, but the method of the present invention only pours the resin by the dispenser into the dam formed by transferring the ceramic green sheet. , The cost can be significantly reduced, and the minimum required package can be manufactured.
In addition, a special device for high-pressure transfer and special consideration for applying high voltage to the substrate, which are required in the transfer molding method, are unnecessary.
【0036】さらに、本発明の方法では、低温で焼成可
能なガラス系セラミックを使用しているため、IC実装
用回路に悪影響を与えることがない。さらにまた、本発
明の方法では、集合基板が原基板として利用可能である
ため、高品質のICパッケージを効率的に製造する方法
として実用的な有用性が極めて高い。Furthermore, since the method of the present invention uses the glass-based ceramics that can be fired at a low temperature, it does not adversely affect the IC mounting circuit. Furthermore, in the method of the present invention, since the collective substrate can be used as an original substrate, it is extremely useful in practice as a method for efficiently producing a high quality IC package.
【図1】 従来法(トランスファモールド法)による樹
脂封止の実施態様を示す断面図。FIG. 1 is a sectional view showing an embodiment of resin sealing by a conventional method (transfer molding method).
【図2】 従来のコーディング法による樹脂封止の実施
態様を示す断面図。FIG. 2 is a sectional view showing an embodiment of resin sealing by a conventional coding method.
【図3】 従来のコーディング法による樹脂封止の実施
態様を示す断面図。FIG. 3 is a sectional view showing an embodiment of resin sealing by a conventional coding method.
【図4】 (a)〜 (d)は本発明によるICパッケージの
製造方法の概要を一連の断面図で示した模式図。4A to 4D are schematic views showing an outline of a method for manufacturing an IC package according to the present invention in a series of sectional views.
【図5】 本発明によるICパッケージ用基板の一例を
示す斜視図。FIG. 5 is a perspective view showing an example of an IC package substrate according to the present invention.
【図6】 本発明によるICパッケージ用基板にICを
実装した状態を示す斜視図。FIG. 6 is a perspective view showing a state in which an IC is mounted on an IC package substrate according to the present invention.
【図7】 本発明による樹脂封止ICパッケージの別の
態様を示す断面図。FIG. 7 is a sectional view showing another embodiment of the resin-sealed IC package according to the present invention.
【図8】 (a)〜 (c)は本発明による集合基板を用いた
ICパッケージの製造方法における位置合わせ工程を示
した模式図。FIG. 8A to FIG. 8C are schematic views showing a positioning process in a method for manufacturing an IC package using the aggregate substrate according to the present invention.
1……基板、2……ICベアチップ、3……導電性接着
剤、4……IC実装用回路パターン、5……導線、6…
…金型、7……キャビティ−、8……ランナ−、9……
樹脂封止層、10……厚膜印刷枠、11……スルーホー
ル、12……端子、13……セラミック製ダム、15…
…IC実装用基板、21……集合基板、22……IC実
装用回路パターン、23……グリーンシート、24……
合成樹脂フィルム、25……窓、26……小孔、27…
…治具、28……ガイドピン1 ... Substrate, 2 ... IC bare chip, 3 ... Conductive adhesive, 4 ... IC mounting circuit pattern, 5 ... Conductor wire, 6 ...
… Mold, 7 …… cavity, 8 …… runner, 9 ……
Resin sealing layer, 10 ... Thick film printing frame, 11 ... Through hole, 12 ... Terminal, 13 ... Ceramic dam, 15 ...
... IC mounting board, 21 ... collective board, 22 ... IC mounting circuit pattern, 23 ... green sheet, 24 ...
Synthetic resin film, 25 ... Window, 26 ... Small hole, 27 ...
… Jig, 28… Guide pin
Claims (5)
上に、前記パターンが囲まれる枠状に形成したセラミッ
クグリーンシートを位置合わせして転写、焼成して、基
板上に封止樹脂用ダムを形成してなることを特徴とする
ICパッケージ用基板。1. A ceramic green sheet formed in a frame shape surrounding the pattern is aligned, transferred and fired on a substrate on which an IC mounting circuit pattern is formed to form a sealing resin dam on the substrate. A substrate for an IC package, which is formed.
としてのガラスを含む無機材料と有機バインダーとを含
有するものである請求項1に記載のICパッケージ用基
板。2. The substrate for an IC package according to claim 1, wherein the ceramic green sheet contains an inorganic material containing glass as a main component and an organic binder.
上に、前記パターンが囲まれる枠状に形成したセラミッ
クグリーンシートを位置合わせして転写、焼成して基板
上にダムを形成した後、ICを実装し、しかる後、前記
ダムで囲まれた領域内に硬化性樹脂を注入して実装した
ICを封止することを特徴とするICパッケージの製造
方法。3. A ceramic green sheet formed in a frame shape surrounding the pattern is aligned and transferred onto a substrate on which a circuit pattern for mounting an IC is formed, baked to form a dam on the substrate, and then the IC is formed. Is mounted, and thereafter, a curable resin is injected into the area surrounded by the dam to seal the mounted IC.
セラミックグリーンシートを、複数のIC実装用領域を
有する基板上に、前記格子の各枠により前記領域がそれ
ぞれ囲まれるように位置合わせし、転写、焼成して基板
上に前記各領域を囲むダムを形成した後、各領域におい
てICの実装と硬化性樹脂の注入を行ない、領域ごとに
切り分けて個別のパッケージとすることを特徴とするI
Cパッケージの製造方法。4. A ceramic green sheet formed in a grid pattern on a synthetic resin film is aligned on a substrate having a plurality of IC mounting areas so that each area of the grid is surrounded by each frame of the grid. After transferring and firing to form a dam surrounding each of the regions on the substrate, mounting of an IC and injection of a curable resin are performed in each region, and each region is cut into individual packages.
C package manufacturing method.
ンシートに小孔径のガイド孔を設けておき、グリーンシ
ートの転写に際し、前記基板をガイドピンを立てた治具
に固定し、前記ガイド孔に前記ガイドピンを挿入するこ
とにより位置合わせを行なう請求項4に記載のICパッ
ケージの製造方法。5. A guide hole having a small hole diameter is provided in the ceramic green sheet formed in the lattice shape, and when transferring the green sheet, the substrate is fixed to a jig with a guide pin, and the guide hole is provided with the guide hole. The method of manufacturing an IC package according to claim 4, wherein the alignment is performed by inserting a guide pin.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8091130A JPH09283659A (en) | 1996-04-12 | 1996-04-12 | Ic package board and manufacture of ic package using the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8091130A JPH09283659A (en) | 1996-04-12 | 1996-04-12 | Ic package board and manufacture of ic package using the same |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH09283659A true JPH09283659A (en) | 1997-10-31 |
Family
ID=14017962
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8091130A Pending JPH09283659A (en) | 1996-04-12 | 1996-04-12 | Ic package board and manufacture of ic package using the same |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH09283659A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20000015580A (en) * | 1998-08-31 | 2000-03-15 | 김규현 | Circuit tape for semiconductor package |
JP2003068942A (en) * | 2001-08-23 | 2003-03-07 | Fuji Electric Co Ltd | Mounting substrate and semiconductor device |
-
1996
- 1996-04-12 JP JP8091130A patent/JPH09283659A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20000015580A (en) * | 1998-08-31 | 2000-03-15 | 김규현 | Circuit tape for semiconductor package |
JP2003068942A (en) * | 2001-08-23 | 2003-03-07 | Fuji Electric Co Ltd | Mounting substrate and semiconductor device |
JP4635393B2 (en) * | 2001-08-23 | 2011-02-23 | 富士電機システムズ株式会社 | Mounting substrate and semiconductor device |
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