JPH09270521A - Thin film transistor manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an abnormal shift of the transistor characteristic by the channel doping of boron at specified concn. in a polycrystalline Si of channels to form a light p-type polycrystalline Si. SOLUTION: Islands of nondoped polycrystalline Si film 1-2 are formed on an insulative transparent substrate 1-1, then a p-type impurity, i.e., B is channel- implanted into the Si 1-2 by the ion implanting over the entire surface of a wafer to form a light p-type polycrystalline Si wherein the implanting is set so that the threshold voltage is about IV and the resistivity is not reduced and hence the doping quantity of B is controlled to be 10<12> cm<-2> -10<13> cm<-2> . A gate oxide film 1-4 is formed by the heat oxidation. Then a CMOS structure is formed by the general process. Thus it is possible to prevent an abnormal shift of the transistor characteristic.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an active matrix formed on a transparent insulating substrate or a CMOS (Complementary-M) used for a switching element of a pixel of an image sensor or a driving circuit.
The present invention relates to a CMOS-type polycrystalline silicon thin-film transistor capable of obtaining a large current at a low driving voltage and having the same absolute value of the threshold voltage of both channel transistors in an etal-oxide-semiconductor type polycrystalline silicon thin-film transistor.

[0002]

2. Description of the Related Art In polycrystalline silicon, it is generally considered that defects such as dangling bonds existing at crystal grain boundaries act as trap levels or barriers for carriers (see, for example, Ｙ, John Y. W. et al.). Set
o, J. et al. Appl. Phys. , 46, 5247 (19)
75)) Therefore, in order to improve the performance of the polycrystalline silicon thin film transistor, it is necessary to reduce the defects. (For example, J. Appl. Phys., 53
(2), 1198 (1982)) For this purpose, the above-mentioned defects are terminated with hydrogen. Among them, a typical method is hydrogen plasma treatment (for example, the Japan Society of Applied Physics. Vol. 27, No. 27, p. Q-5, Regarding hydrogen plasma, see Electronic Materials, January, 1981, p. 124) or formation of a plasma nitride film (Technical Research Report of the Institute of Electronics, Communication and Communication Engineers, SSD 83-75, page 23). When these methods are used, the absolute value of the threshold voltage (hereinafter, referred to as Vth) becomes small, and the rise of the sub-threshold region becomes steep.

[0003]

However, in the above-mentioned prior art, the problem of Vth shift cannot be ignored. In other words, there is a problem that the N-channel transistor shifts in the depletion direction and the OFF leak current increases, and the P-channel transistor shifts in the enhancement direction. (Refer to the IEICE Technical Report SSD83-75, page 23.) The cause of this is that a positive fixed charge is formed in the gate oxide film by exposure to plasma, and the channel portion is always induced to be negative. It is thought that there is. Therefore, if the polycrystalline silicon thin film is made P-type in advance, the above-mentioned problem of the shift in transistor characteristics due to the hydrogen plasma treatment can be solved.

The present invention solves the problem of an abnormal shift in transistor characteristics associated with such a hydrogen plasma processing step, a hydrogen ion implantation step, or a plasma nitride film forming step, and has a small absolute value of Vth and a sub-threshold. The rising of the region is sharp, and the absolute value of Vth is almost equal for both the P channel and the N channel.
An object of the present invention is to provide a MOS polycrystalline silicon thin film transistor.

[0005]

According to the present invention, there is provided a CMOS type polycrystalline silicon thin film transistor and a method of manufacturing the same, comprising a C type having an N channel polycrystalline silicon thin film transistor and a P channel polycrystalline thin film transistor on an insulating transparent substrate.
The MOS polycrystalline silicon thin film transistor has a step of channel doping boron before forming a gate electrode, and a step of hydrogen plasma treatment, a step of implanting hydrogen ions, or a step of forming a plasma nitride film after forming the gate electrode.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. In FIG. 1A, an island 1-2 of an undoped polycrystalline silicon thin film is formed on an insulating transparent substrate 1-1.
To form The undoped polycrystalline silicon is formed by low pressure CVD.
Is deposited. Further, the islands 1-2 are formed by photoetching. Then, boron, which is a P-type impurity, is channel-implanted into the polycrystalline silicon by ion implantation over the entire surface of the wafer to form light P-type polycrystalline silicon. 1-3 shows a boron beam. However, V
shift amount th is at about 1 volt, it is necessary to resistivity is set to implantation amount of about not decreased, approximately 10 ¹²
cm ⁻² , to about 10 ¹³ cm ⁻² is appropriate. Subsequently, as shown in FIG. 3B, the ligated oxide film 1-4 is formed by thermal oxidation.
To form There is also a method of performing channel doping after forming the gate oxide film. In this case, damage due to ion implantation into the gate oxide film is considered (for example, see Applied Physics, Vol. 54, No. 12, page 1268, 1985). Is expected to deteriorate. Therefore, it is considered that it is better to perform channel doping before forming the gate oxide film as in this embodiment. FIGS. 1C and 1D show a general process for manufacturing a CMOS structure. Reference numeral 1-5 denotes a gate electrode. Using the gate electrode as a mask, boron and phosphorus are selectively ion-implanted to form source and drain portions. As shown in (d), a P-channel polycrystalline silicon thin film transistor 1-8
And N-channel polycrystalline silicon thin film transistor 1-9
To form 1-6 indicates a boron implantation region, and 1-7 indicates a phosphorus implantation region. In the case of hydrogen ion implantation, this is performed in this state. Next, an interlayer insulating film is formed. When a plasma nitride film Si ₃ N ₄ is used as the interlayer insulating film, hydrogenation of polycrystalline silicon is achieved simultaneously with formation of the interlayer insulating film.
As shown in FIG. 1E, CVDS is applied to the interlayer insulating film 1-10.
When using iO ₂ or the like, a hydrogen plasma process is subsequently performed. Reference numerals 1-11 indicate highly reactive hydrogen radicals generated by hydrogen plasma. Hydrogen plasma can be easily obtained by using a conventional plasma apparatus and H ₂ gas of the parallel plate type. On the other hand, there is no problem even if the hydrogen plasma treatment step is performed after forming the contact electrode.

As described above, according to this embodiment, the N-channel polycrystalline silicon thin film transistor is shifted in the depletion direction by the conventional hydrogen plasma processing,
The abnormal shift of the channel polycrystalline silicon thin film transistor is shifted each enhancement methods problem, channel doping with boron polysilicon channel portion in a low concentration (10 ₁₂ cm ^-2 from 10 ^{13 Cm-2} approximately) Light This can be prevented by using P-type polycrystalline silicon. Therefore, the advantage of reducing the defects of polycrystalline silicon by the hydrogen plasma treatment can be utilized to the utmost. That is, the rise of the sub-threshold region becomes abrupt, the absolute value of Vth is reduced, and moreover, the magnitude of the absolute value of Vth is the same for both N-channel and P-channel. It is possible to realize a thin film transistor. FIG. 2 shows the effect of the present invention on an N-channel polycrystalline silicon thin film transistor. This figure is data obtained by the inventor through experiments. The horizontal axis is the gate-source voltage V _gs , and the vertical axis is the logarithm of the drain current I _DS . The measurement was performed at a drain-source voltage _VDS of 5 V. The curve of the broken line 2-1 is the result of the conventional method, and the curve of the solid line 2-2 is the result of the embodiment of the present invention in which boron channel doping is performed. However, channel doping is performed after the gate oxide film formation, discharge amount is boron 5 × 10 ¹² cm ^-2. As can be seen from these results, in the conventional method, the N-channel polycrystalline silicon thin film transistor abnormally shifts in the depletion direction, whereas the result of the present invention does not shift at all and the effect of the present invention is very large. It is.

For example, when the present invention is applied to an active matrix substrate, an OFF current is small, so that a high-contrast active matrix substrate can be realized. Also, CMOS
Due to its structure, it can be applied to an image sensor in which a shift register circuit (S / R) and a photoelectric conversion element are formed on the same substrate. Large effect is expected. It also contributes to lower power consumption and lower cost. In addition, since the voltage can be reduced, the reliability of the device can be improved.

[0009]

As described above, according to the present invention, an excellent CMOS having a sharp rise, a small Vth, a small OFF leak current, and an almost identical absolute value of the Vth of the N channel and the P channel. Type polycrystalline silicon thin film transistor,
The present invention has a great effect on demand items such as high speed operation, low power consumption and high reliability of devices such as image sensors.

[Brief description of drawings]

FIGS. 1A to 1E show a CMOS according to the present invention;
FIG. 5 is a process drawing of a type polycrystalline silicon thin pus transistor.

FIG. 2 is a transistor characteristic diagram showing an effect of the present invention on an N-channel polycrystalline silicon thin film transistor for comparison with a conventional example.

[Explanation of symbols]

 1-2; polycrystalline silicon 1-8; boron beam 1-5; gate electrode 1-11; hydrogen radical 2-1; transistor curve according to the conventional example 2-2; transistor curve according to the embodiment of the present invention

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[Procedure amendment]

[Submission date] January 8, 1997

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

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[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0001

[Correction method] Change

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[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS (Comp) used for a switching element of a pixel of an active matrix or an image sensor or a driving circuit.
elementary-Metal-Oxide-Sem
The present invention relates to a method for manufacturing an (iconductor) type polycrystalline silicon thin film transistor.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction contents]

[0005]

The present invention provides a method of manufacturing a thin film transistor having a first conductivity type polycrystalline silicon thin film transistor and a second conductivity type polycrystalline silicon thin film transistor, wherein the first conductivity type polycrystalline silicon thin film transistor is provided on an insulating substrate. A first polycrystalline silicon thin film of the crystalline silicon thin film transistor and a second polycrystalline silicon thin film transistor of the second conductivity type.
Both the step of forming the polycrystalline silicon thin film and the low-concentration first conductivity type impurities are doped in both the region of the first polycrystalline silicon thin film that serves as the channel and the region of the second polycrystalline silicon thin film that serves as the channel. A step of forming a gate electrode on the first and second polycrystalline silicon thin films via an insulating film, and selectively doping the first polycrystalline silicon thin film with an impurity of a first conductivity type at a high concentration. Forming a source and a drain of the first and second conductive type polycrystalline silicon thin film transistors by selectively doping the second polycrystalline silicon thin film with a second conductive type impurity at a high concentration. A step of performing hydrogen treatment after forming the source and the drain, the doping amount for doping the first conductivity type impurity to a low concentration is 10 ¹² c
It is characterized by controlling from m ⁻² to 10 ¹³ cm ⁻² .

Claims (1)

[Claims] 1. A CMOS type polycrystalline silicon thin film transistor having an n-channel polycrystalline silicon thin film transistor and a p-channel polycrystalline silicon thin film transistor on an insulating transparent substrate. A method for manufacturing a thin film transistor, comprising: a hydrogen plasma treatment step, a hydrogen ion implantation step, or a plasma nitride film formation step after forming an electrode.